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Journal articles on the topic 'Charge Pump Phase Locked Loop'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

CHANG, ROBERT C., LUNG-CHIH KUO, and HOU-MING CHEN. "A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP." Journal of Circuits, Systems and Computers 14, no. 05 (October 2005): 997–1006. http://dx.doi.org/10.1142/s0218126605002738.

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A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

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2

Charlamov, J., and R. Navickas. "Phase Locked Loop Integrated System." Solid State Phenomena 164 (June 2010): 221–26. http://dx.doi.org/10.4028/www.scientific.net/ssp.164.221.

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CMOS-MEMS integration is an indispensable technique for self-calibration of electromechanical performance to make MEMS devices independent on environmental drift or fabrication errors. The goal of single-chip integration (the “holy grail” for the semiconductor timing industry) would be to include the resonator, the oscillator, the PLL and a temperature compensation circuit (TCC) on a single silicon substrate. The current structure of silicon MEMS-based devices utilizes a stacked-die arrangement, housed in a multi-chip package [1]. MEMS-based timing circuits often use PLLs, which can succumb to phase jitter and noise at higher timing frequencies. The architecture of a charge pump phase locked loop (CPPLL) is proposed in this work. It is discussed how its functional blocks influence the overall system performance. We have performed voltage-controlled oscillator (VCO) phase noise analysis and have determined the relationship between CPPLL and VCO phase noises and have discussed the requirements and results of the accomplished design.

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3

Nanda, Umakanta, Jyotirmayee Sarangi, and Prakash Kumar Rout. "Study of Recent Charge Pump Circuits in Phase Locked Loop." International Journal of Modern Education and Computer Science 8, no. 8 (August 8, 2016): 59–65. http://dx.doi.org/10.5815/ijmecs.2016.08.08.

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4

Wang, San-Fu, Tsuen-Shiau Hwang, and Jhen-Ji Wang. "Phase-locked loop design with fast-digital-calibration charge pump." International Journal of Electronics 103, no. 2 (April 24, 2015): 342–54. http://dx.doi.org/10.1080/00207217.2015.1036371.

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5

Xiang, Qi, Hongxia Liu, and Yulun Zhou. "A Single-Event-Hardened Scheme of Phase-Locked Loop Microsystems for Aerospace Applications." Micromachines 13, no. 12 (November 28, 2022): 2102. http://dx.doi.org/10.3390/mi13122102.

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In order to improve the ability of the phase-locked loop (PLL) microsystem applied in the aerospace environment to suppress the irradiation effect, this study presents an efficient charge pump hardened scheme by using the radiation-hardened-by-design (RHBD) technology. In this study, the sensitivity analysis of the single-event transient (SET) at different nodes of charge pump and different bombardment energies is carried out. Without changing the original structure and loop parameters, a hardened scheme of phase-locked loop to suppress the single-event effect is proposed. A digital control circuit is added between the charge pump and low-pass filter, which greatly reduces the sensitivity of the charge pump to the SET. The classical double-exponential current pulse model is used to simulate the SET effect on the unreinforced and reinforced phase-locked loops, and the reliability of the proposed reinforcement scheme is verified. The simulation results based on the SMIC 130 nm standard complementary metal–oxide–semiconductor (CMOS) process show that the peak value of the transient response fluctuation of the phase-locked loop using the proposed single-event-hardened scheme decreased by 94.2%, the lock recovery time increased by 75.3%, and the maximum phase shift decreased by 90.8%. This shows that the hardened scheme can effectively reduce the sensitivity of the PLL microsystems to the SET effects.

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6

Hanumolu, P. K., M. Brownlee, K. Mayaram, and U. K. Moon. "Analysis of Charge-Pump Phase-Locked Loops." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 9 (September 2004): 1665–74. http://dx.doi.org/10.1109/tcsi.2004.834516.

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7

Curran, Paul F., Chuang Bi, and Orla Feely. "Dynamics of charge-pump phase-locked loops." International Journal of Circuit Theory and Applications 41, no. 11 (April 19, 2012): 1109–35. http://dx.doi.org/10.1002/cta.1814.

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8

Kratyuk, Volodymyr, Pavan Kumar Hanumolu, Un-Ku Moon, and Kartikeya Mayaram. "A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 3 (March 2007): 247–51. http://dx.doi.org/10.1109/tcsii.2006.889443.

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9

Charlamov, Jevgenij. "PLL DESIGN AND INVESTIGATION IN CMOS." Mokslas - Lietuvos ateitis 2, no. 1 (February 28, 2010): 54–58. http://dx.doi.org/10.3846/mla.2010.012.

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In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm2, power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.

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10

Taheri, H. E. "A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop." Engineering, Technology & Applied Science Research 7, no. 2 (April 24, 2017): 1473–77. http://dx.doi.org/10.48084/etasr.1099.

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A low power, low phase noise adaptive bandwidth phase locked loop is presented in this paper. The proposed structure benefits from a novel lock status monitor unit (LSMU) that determines loop operation and loop bandwidth. The loop filter resistance and charge pump current are inversely proportional and bandwidth to reference frequency is maintained fixed. This structure is simulated in 0.18 μm CMOS technology and simulation results are presented.

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11

Zaziabl, Adam. "A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS Process." International Journal of Electronics and Telecommunications 56, no. 4 (November 1, 2010): 411–16. http://dx.doi.org/10.2478/v10177-010-0055-7.

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A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS ProcessDemand of modern measurement systems in submicron CMOS process introduced new challenges in design of low power high frequency clock generation systems. Technical possibilities for clock generation using classical oscillator based on a quartz filter is limited to tens of megahertz. Thus, 1 GHz clock generation is not possible without a frequency multiplier system. It is difficult to achieve, because in submicron process, where the integration of analog and digital blocks poses serious challenges. The proposed solution is a low power charge pump phase-locked loop (CPPLL) with the center frequency of 1 GHz. It combines various modern circuit techniques, whose main aim is to lower power consumption, which is below 800 μW for the whole PLL, while maintaining good noise properties, where the jitter rms is 8.87 ps. The proposed phase-locked loop is designed in 0.18 μm CMOS process.

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12

Can, Sumer, and Yilmaz E. Sahinkaya. "Modeling and simulation of an Analog Charge-Pump Phase Locked Loop." SIMULATION 50, no. 4 (April 1988): 155–60. http://dx.doi.org/10.1177/003754978805000405.

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13

Choi, Y. S., and D. H. Han. "Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 10 (October 2006): 1022–25. http://dx.doi.org/10.1109/tcsii.2006.882122.

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14

WOO, YOUNGSHIN, YOUNG MIN JANG, and MAN YOUNG SUNG. "A NOVEL METHOD FOR HIGH-PERFORMANCE PHASE-LOCKED LOOP." Journal of Circuits, Systems and Computers 13, no. 01 (February 2004): 53–63. http://dx.doi.org/10.1142/s0218126604001271.

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In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5 μm CMOS technology with 5 V supply voltage.

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15

D S, Rajeshwari, P. V Rao, and Ramesh Karmungi. "10Ghz Charge Pump PLL for Low Jitter Applica-tions." International Journal of Engineering & Technology 7, no. 2.12 (April 3, 2018): 348. http://dx.doi.org/10.14419/ijet.v7i2.12.11349.

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This paper presents design and simulation of charge pump architectures for 10GHz Charge Pump Phase locked Loop. Differential delay cell VCO with symmetric load and Programmable frequency divider are efficiently implemented in loop. Able to achieve Peak jitter of the Divider 10ns, Peak jitter of VCO 205ps at 1GHz.Charge pump is analysed in loop by reduced current mismatch using improved high swing cascode structure including start up circuitand it has low turn ON voltage and high ouput impedance to provide stable voltage.Charge pump results current mismatch less than 0.05%.10GHz DPLL is simulated with 65nm techonology, 1.2V and tsmc foundary model files

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16

Zuoding Wang. "An analysis of charge-pump phase-locked loops." IEEE Transactions on Circuits and Systems I: Regular Papers 52, no. 10 (October 2005): 2128–38. http://dx.doi.org/10.1109/tcsi.2005.852934.

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17

Metange, P. N., and K. B. Khanchandani. "Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications." Indonesian Journal of Electrical Engineering and Computer Science 4, no. 2 (November 1, 2016): 397. http://dx.doi.org/10.11591/ijeecs.v4.i2.pp397-405.

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<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications. The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

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18

Gomez-Cruz, Jorge de Jesus, Fernando Sanchez-Hernandez, Luis Guillermo Gomez-Mora, Esdras Juarez-Hernandez, and Esteban Martinez-Guerrero. "Design of a programmable CMOS Charge-Pump for phase-locked loop synthesizers." Procedia Technology 3 (2012): 235–40. http://dx.doi.org/10.1016/j.protcy.2012.03.025.

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19

Zhao, Ranran, Yuming Zhang, Hongliang Lv, and Yue Wu. "Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process." Sensors 22, no. 2 (January 10, 2022): 504. http://dx.doi.org/10.3390/s22020504.

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This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.

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20

Liu, Faen, Zhigong Wang, Zhiqun Li, Qin Li, and Sheng Chen. "Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop." Journal of Semiconductors 35, no. 10 (October 2014): 105006. http://dx.doi.org/10.1088/1674-4926/35/10/105006.

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21

Zhao, Yi-Bo, Chi-Kong Tse, Jiu-Chao Feng, and Ye-Cai Guo. "Application of Memristor-Based Controller for Loop Filter Design in Charge-Pump Phase-Locked Loops." Circuits, Systems, and Signal Processing 32, no. 3 (November 27, 2012): 1013–23. http://dx.doi.org/10.1007/s00034-012-9521-z.

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22

YOSHIOKA, Masahiro, and Nobuo FUJII. "Reduction of Charge Injection and Current-Mismatch Errors of Charge Pump for Phase-Locked Loop." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A, no. 2 (2009): 381–88. http://dx.doi.org/10.1587/transfun.e92.a.381.

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23

Wiegand, C., C. Hedayat, and U. Hilleringmann. "Non-linear behaviour of charge-pump phase-locked loops." Advances in Radio Science 8 (October 1, 2010): 161–66. http://dx.doi.org/10.5194/ars-8-161-2010.

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Abstract. The analysis of the mixed analogue and digital structure of charge-pump phase-locked loops (CP-PLL) is a challenge in modelling and simulation. In most cases the system is designed and characterized using its continuous linear model or its discrete linear model neglecting its non-linear switching behaviour. I.e., the time-varying model is approximated by a time-invariant representation using its average dynamics. Depending on what kind of phase detector is used, the scopes of validity of these approximations are different. Here, a preeminent characterization and simulation technique based on the systems event-driven feature is presented, merging the logical and analogue inherent characteristics of the system. In particular, the high-grade non-linear locking process and the dead-zone are analyzed.

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24

Homayoun, Aliakbar, and Behzad Razavi. "On the Stability of Charge-Pump Phase-Locked Loops." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 6 (June 2016): 741–50. http://dx.doi.org/10.1109/tcsi.2016.2537823.

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25

Leoncini, Mauro, Andrea Bonfanti, Salvatore Levantino, and Andrea L. Lacaita. "Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops." IEEE Transactions on Circuits and Systems I: Regular Papers 65, no. 6 (June 2018): 1968–80. http://dx.doi.org/10.1109/tcsi.2017.2767280.

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26

Faisal, Fahad. "Design Analysis of Charge-Pump Phase Locked Loop with Analogy Lock Signal Generator." International Journal for Research in Applied Science and Engineering Technology V, no. XI (November 13, 2017): 295–304. http://dx.doi.org/10.22214/ijraset.2017.11043.

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27

Babu, K. N. Dinesh, R. Ramaprabha, V. Rajini, and Kamal Bansal. "Charge Pump Phase Locked Loop Synchronization Technique in Grid Connected Solar Photovoltaic Systems." IOSR Journal of Computer Engineering 16, no. 1 (2014): 91–98. http://dx.doi.org/10.9790/0661-16179198.

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28

Hangmann, Christian, Christian Hedayat, and Ulrich Hilleringmann. "Stability Analysis of a Charge Pump Phase-Locked Loop Using Autonomous Difference Equations." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 9 (September 2014): 2569–77. http://dx.doi.org/10.1109/tcsi.2014.2333331.

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29

Li, Zhiqun, Shuangshuang Zheng, and Ningbing Hou. "Design of a high performance CMOS charge pump for phase-locked loop synthesizers." Journal of Semiconductors 32, no. 7 (July 2011): 075007. http://dx.doi.org/10.1088/1674-4926/32/7/075007.

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30

Rahman, Labonnah Farzana, NurHazliza Bt Ariffin, Mamun Bin Ibne Reaz, and Mohammad Marufuzzaman. "High Performance CMOS Charge Pumps for Phase-locked Loop." Transactions on Electrical and Electronic Materials 16, no. 5 (October 25, 2015): 241–49. http://dx.doi.org/10.4313/teem.2015.16.5.241.

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31

Maffezzoni, Paolo, and Salvatore Levantino. "Analysis of VCO Phase Noise in Charge-Pump Phase-Locked Loops." IEEE Transactions on Circuits and Systems I: Regular Papers 59, no. 10 (October 2012): 2165–75. http://dx.doi.org/10.1109/tcsi.2012.2185312.

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32

Ghaderi, Noushin, Hamid Reza Erfani-jazi, and Mehdi Mohseni-Mirabadi. "A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods." Journal of Electrical and Computer Engineering 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/8202581.

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A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a0.18 μmCMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly.

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33

Ali, Ehsan, Abdul Sattar Sand, Farida Memon, Ghulam Mustafa Bhuto, and Nasreen Nizamani. "Stability Consideration of the Voltage Switched Charge-pump Phase Locked Loop using Linear Approach." Research Journal of Applied Sciences, Engineering and Technology 13, no. 3 (August 5, 2016): 257–64. http://dx.doi.org/10.19026/rjaset.13.2939.

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34

Xi, Na. "A low reference spur phase-locked loop realized with dynamic current injection charge pump." IEICE Electronics Express 16, no. 8 (2019): 20190095. http://dx.doi.org/10.1587/elex.16.20190095.

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35

Burbidge, M. J., A. Lechner, G. Bell, and A. M. D. Richardson. "Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers." IEE Proceedings - Circuits, Devices and Systems 151, no. 4 (2004): 337. http://dx.doi.org/10.1049/ip-cds:20040619.

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36

Chen, Y. P., T. D. Loveless, A. L. Sternberg, E. X. Zhang, J. S. Kauppila, B. L. Bhuva, W. T. Holman, et al. "Persistent Laser-Induced Leakage in a 20 nm Charge-Pump Phase-Locked Loop (PLL)." IEEE Transactions on Nuclear Science 64, no. 1 (January 2017): 512–18. http://dx.doi.org/10.1109/tns.2016.2627940.

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37

Xia, Lanhua, Jianhui Wu, Cheng Huang, and Meng Zhang. "Built‐in self‐test structure for fault detection of charge‐pump phase‐locked loop." IET Circuits, Devices & Systems 10, no. 4 (July 2016): 317–21. http://dx.doi.org/10.1049/iet-cds.2015.0224.

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38

Maffezzoni, P., and S. Levantino. "Computing low-frequency noise in charge-pump phase-locked loops." Electronics Letters 47, no. 23 (2011): 1270. http://dx.doi.org/10.1049/el.2011.2712.

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39

Guo, Rui, Zhenghao Lu, Shaogang Hu, Qi Yu, Limei Rong, and Yang Liu. "Design and Verification of a Charge Pump in Local Oscillator for 5G Applications." Electronics 10, no. 9 (April 23, 2021): 1009. http://dx.doi.org/10.3390/electronics10091009.

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A charge pump (CP) that has low current mismatch to reduce the locking time of the Phase-Locked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a charge pump architecture consists of an operational power amplifier (OPA), switches, three D flip-flops (DFFs) and passive devices. A phase error compensation technique is introduced in the charge pump to reduce the locking time. The current mismatch, which is mainly due to the leakage current, is below 1% for a large output voltage headroom of 84% of the supply voltage. An 18.4% reduction in the settling time is realized by the proposed design.

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40

Chen, Yu-Cheng, and Fan-Ren Chang. "An LMI-Based Method for Reference Spur Reduction in Charge-Pump Phase-Locked Loops Containing Loop Delay." Circuits, Systems, and Signal Processing 31, no. 5 (April 10, 2012): 1615–29. http://dx.doi.org/10.1007/s00034-012-9409-y.

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41

Lee, Tzung-Je, and Chua-Chin Wang. "A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators." VLSI Design 2008 (September 24, 2008): 1–8. http://dx.doi.org/10.1155/2008/512946.

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A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper. Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively. By using separate regulators, the area and the power consumption of the regulator can be reduced. Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise. The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process. The peak-to-peak jitter (P2P jitter) of the proposed PLL is measured to be 81.8 ps at 80 MHz when a 250 mVrms supply noise is added. By contrast, the P2P jitter is measured to be 118.2 ps without the two regulators when the same supply noise is coupled.

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42

Park, Jong-Youn, and Hyek-Hwan Choi. "Phase-Locked Loop with a loop filter consisting of a capacitor and a charge pump functioned as resistor." Journal of the Korean Institute of Information and Communication Engineering 16, no. 11 (November 30, 2012): 2495–502. http://dx.doi.org/10.6109/jkiice.2012.16.11.2495.

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43

Burbidge, Martin John, and J. Tijou. "Towards generic charge-pump phase-locked loop, jitter estimation techniques using indirect on chip methods." Integration 40, no. 2 (February 2007): 133–48. http://dx.doi.org/10.1016/j.vlsi.2006.02.004.

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44

Zhongjie, Guo, Liu Youbao, Wu Longsheng, Wang Xihu, and Tang Wei. "Short locking time and low jitter phase-locked loop based on slope charge pump control." Journal of Semiconductors 31, no. 10 (October 2010): 105002. http://dx.doi.org/10.1088/1674-4926/31/10/105002.

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45

Abbas, Waseem, Zubair Mehmood, and Munkyo Seo. "A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS." Electronics 9, no. 9 (September 13, 2020): 1502. http://dx.doi.org/10.3390/electronics9091502.

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A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.

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46

Burbidge, M. J., and A. M. Richardson. "Simple digital test approach for embedded charge-pump phase-locked loops." Electronics Letters 37, no. 22 (2001): 1318. http://dx.doi.org/10.1049/el:20010914.

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47

Gaied, David, and Emad Hegazi. "Charge-Pump Folded Noise Cancelation in Fractional-N Phase-Locked Loops." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 6 (June 2014): 378–82. http://dx.doi.org/10.1109/tcsii.2014.2319691.

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48

Hsu, Jen-Chien, and Chauchin Su. "BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops." IEEE Transactions on Instrumentation and Measurement 57, no. 2 (2008): 276–85. http://dx.doi.org/10.1109/tim.2007.910109.

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49

Lee, Jae-Shin, Min-Sun Keel, Shin-Il Lim, and Suki Kim. "Charge pump with perfect current matching characteristics in phase-locked loops." Electronics Letters 36, no. 23 (2000): 1907. http://dx.doi.org/10.1049/el:20001358.

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50

B. S., Premananda, Dhanush T. N., Vaishnavi S. Parashar, and D. Aneesh Bharadwaj. "Design and Implementation of High Frequency and Low-Power Phase-locked Loop." U.Porto Journal of Engineering 7, no. 4 (November 26, 2021): 70–86. http://dx.doi.org/10.24840/2183-6493_007.004_0006.

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Abstract:

Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.

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