Relevant bibliographies by topics / Charge Pump PLL

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  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Charge Pump PLL'

Author: Grafiati
Published: 3 June 2025
Last updated: 1 August 2025

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Journal articles on the topic "Charge Pump PLL"

1

Hati, A., and B. C. Sarkar. "Pump current modulated charge pump PLL." Electronics Letters 35, no. 18 (1999): 1498. http://dx.doi.org/10.1049/el:19990997.

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Hwang, M. S., J. Kim, and D. K. Jeong. "Reduction of pump current mismatch in charge-pump PLL." Electronics Letters 45, no. 3 (2009): 135. http://dx.doi.org/10.1049/el:20092727.

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3

Park, Sung Sik, Ju Sang Lee, and Sang Dae Yu. "Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (2018): 4120. http://dx.doi.org/10.11591/ijece.v8i6.pp4120-4132.

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In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect c
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Park, Sung Sik, Ju Sang Lee, and Sang Dae Yu. "Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (2018): 4120–32. https://doi.org/10.11591/ijece.v8i6.pp4120-4132.

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In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect c
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D S, Rajeshwari, P. V Rao, and Ramesh Karmungi. "10Ghz Charge Pump PLL for Low Jitter Applica-tions." International Journal of Engineering & Technology 7, no. 2.12 (2018): 348. http://dx.doi.org/10.14419/ijet.v7i2.12.11349.

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This paper presents design and simulation of charge pump architectures for 10GHz Charge Pump Phase locked Loop. Differential delay cell VCO with symmetric load and Programmable frequency divider are efficiently implemented in loop. Able to achieve Peak jitter of the Divider 10ns, Peak jitter of VCO 205ps at 1GHz.Charge pump is analysed in loop by reduced current mismatch using improved high swing cascode structure including start up circuitand it has low turn ON voltage and high ouput impedance to provide stable voltage.Charge pump results current mismatch less than 0.05%.10GHz DPLL is simulat
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N.AshokKumar, Dr, and Dr A.Kavitha. "An Efficient and Novel Design of Loop Filter, Charge Pump and VCO for PLL Using CMOS Technology." International Journal of Engineering & Technology 7, no. 2.20 (2018): 339. http://dx.doi.org/10.14419/ijet.v7i2.20.16729.

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This article presents an occasional energy charge pump, low pass filter and voltage supervised generator for little energy section loop. PLL are generally used for synchronization and regulate of grid- associated power electronic techniques. The article enfolds the whole circuit figure of circle filter, charge pump and voltage restrict oscillator through 1.8v energy stock. This kind uses 0.18um CMOS technology. In recent times, voltage restricted oscillator are employed for phase lock loop. A great viable loop-bandwidth plan method, derivative from a distinct -time PLL model, additional comple
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AshokKumar, N., and A. Kavitha. "An Efficient and Novel Design of Loop Filter, Charge Pump and VCO for PLL Using CMOS Technology." International Journal of Engineering & Technology 7, no. 3.1 (2018): 39. http://dx.doi.org/10.14419/ijet.v7i3.1.16793.

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This article presents an occasional energy charge pump, low pass filter and voltage supervised generator for little energy section loop. PLL are generally used for synchronization and regulate of grid- associated power electronic techniques. The article enfolds the whole circuit figure of circle filter, charge pump and voltage restrict oscillator through 1.8v energy stock. This kind uses 0.18um CMOS technology. In recent times, voltage restricted oscillator are employed for phase lock loop. A great viable loop-bandwidth plan method, derivative from a distinct -time PLL model, additional comple
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Charlamov, Jevgenij. "PLL DESIGN AND INVESTIGATION IN CMOS." Mokslas - Lietuvos ateitis 2, no. 1 (2010): 54–58. http://dx.doi.org/10.3846/mla.2010.012.

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In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm2, power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.
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Gyoung-Tae Roh, Yong Hoon Lee, and Beomsup Kim. "Optimum phase-acquisition technique for charge-pump PLL." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 44, no. 9 (1997): 729–40. http://dx.doi.org/10.1109/82.625005.

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Chen, Y., P. I. Mak, and Y. Zhou. "Self-tracking charge pump for fast-locking PLL." Electronics Letters 46, no. 11 (2010): 755. http://dx.doi.org/10.1049/el.2010.3562.

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Dissertations / Theses on the topic "Charge Pump PLL"

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SINGH, GUNEET. "HIGH-FREQUENCY CHARGE-PUMP BASED PHASE-LOCKED LOOP DESIGN AND IT'S CHARACTERIZATION USING VERILOG-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155077793.

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Yogesh, Mitesh. "A Self-compensated, Bandwidth Tracking Semi-digital PLL Design in 65nm CMOS Technol-ogy." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-85143.

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In a conventional charge-pump based PLL design, the loop parameters such as the band-width, jitter performance, charge-pump current, pull-in range among others govern the ar-chitecture and implementation details of the PLL. Different loop parameter specificationschange with a change in the reference frequency and inmost cases, requires careful re-designof some of the PLL blocks. This thesis describes the implementation of a semi-digital PLLfor high bandwidth applications, which is self-compensated, low-power and exhibits band-width tracking for all reference frequencies between 40 MHz and 1.6 GH
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Scheibe, Niko. "Entwicklung einer monolithisch integrierten 2,44 GHz Phasenregelschleife in der LFoundry 150nm-CMOS Technologie." Master's thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-61765.

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Die Spezifikationen und Toleranzbereiche heutiger Hochgeschwindigkeitsdatenübertragungstechnologien nehmen immer weiter an Komplexität, aufgrund der steigenden Informationsmenge, zu. Zur Verarbeitung von Daten in Frequenzbereichen oberhalb von einem Gigahertz sind Referenzsignale notwendig, welche ein äußerst geringes Phasenrauschen aufweisen um benachbarte Kanäle nicht zu beeinflussen. Diese Referenzsignale werden in Mischerschaltungen zur Modulation oder Demodulation zwischen radio frequency (RF)- und intermediate frequency (IF)-Signalen verwendet. Die benötigte Signalform ist eine Sinusschw
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Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.

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Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analo
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Cheng, Shanfeng. "Design of CMOS integrated phase-locked loops for multi-gigabits serial data links." Texas A&M University, 2006. http://hdl.handle.net/1969.1/4954.

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High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyze
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Chu, Hung-Chen, and 朱宏鎮. "A High-speed Charge Pump with Two Charge Currents for PLL." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/01487085345502572809.

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碩士<br>中華大學<br>電機工程學系碩士班<br>94<br>In this thesis, we design a high speed phase-locked loop (PLL).The circuit is simulated and verified by Hspice with TSMC 0.18μm technology.A PLL consists of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a voltage controlled oscillator (VCO) and a divider. In PFD, we use a novel structure with symmetrical circuits to delete jitter. In CP , we use two charge currents to speed up lock time. In LF, we use a second order RC filter to make up. In VCO, we use the complementary cross-couple LC-tank to make up. In divider, the D flip-flop cir
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Liu, Yu-Ting, and 劉昱廷. "Design of a Charge-Pump PLL for LVDS SerDes." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/12761046667560912152.

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碩士<br>中原大學<br>電子工程研究所<br>103<br>In this paper, we design a PLL for low voltage differential signal(LVDS) serializer/deserializer. We can reduce the area of chip by using charge pump and ring oscillator. Design platform is 0.18μm 1P6M CMOS process. The output frequency is 840MHz at 120MHz input frequency. The power is 5.24mW at 1.8V power supply, setting time is 12μs and jitter is 4.2ps.
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Ma, Yu-hua, and 馬郁華. "Design and Simulation of Dual-Loop Charge-Pump PLL with Fast-Lock." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/92130756545716843425.

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碩士<br>朝陽科技大學<br>資訊工程系碩士班<br>92<br>ABSTRACT Phase-Locked Loop (PLL) is very popular and important in the applications of Integrated circuit field. Examples of the applications that use PLL include clock and data recovery, clock synthesis or synchronization, frequency synthesis, and PLL modulator or de-modulator applications. The basic operating principle of PLL is to synchronize an output signal with a reference or input signal in frequency as well as phase. When the phase error between the oscillator’s output signal and the reference signal is zero, or remains constant that often called locke
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Hu, Eric Wei-Tse. "A 1.8 V 2.5 GHz PLL with on-chip charge pump-based supply regulation." 2005. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=362380&T=F.

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Raghavendra, R. G. "Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector." Thesis, 2009. https://etd.iisc.ac.in/handle/2005/1006.

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Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the number of such challenges vary depending on the process technology employed and the end application. One such challenge that is worth mentioning is the on-chip integration of the second order passive loop filter. The area occupied by the second order passive loop filter is mainly determined by the zero d
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Books on the topic "Charge Pump PLL"

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Hu, Eric Wei-Tse. A 1.8 V 2.5 GHz PLL with on-chip charge pump-based supply regulation. 2005.

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Hu, Eric Wei-Tse. A 1.8 V 2.5 GHz PLL with on-chip charge pump-based supply regulation. 2005.

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Book chapters on the topic "Charge Pump PLL"

1

Yuan, Hengzhou, and Yang Guo. "A High-Matching Low Noise Differential Charge Pump for PLL." In Communications in Computer and Information Science. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5919-4_9.

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Khalid, Nashra, and Ram Chandra Singh Chauhan. "Performance Analysis of Various Charge Pump Topologies for PLL Application." In VLSI, Communication and Signal Processing. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0973-5_25.

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Renukaswamy, Pratap Tumkur, Nereo Markulic, and Jan Craninckx. "A 16 GHz Duty-Cycled Charge Pump PLL-Based Chirp Synthesizer." In PLL Modulation and Mixed-Signal Calibration Techniques for FMCW Radar. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-59773-2_3.

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Roy, Subham, Kirankumar H. Lad, S. Rekha, and T. Laxminidhi. "A Low Mismatch Current Steering Charge Pump for High-Speed PLL." In Proceedings of Second International Conference on Computational Electronics for Wireless Communications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-6661-3_40.

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Hati, Manas Kumar, and Tarun Kanti Bhattacharyya. "A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL." In Progress in VLSI Design and Test. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31494-0_19.

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Prithiviraj, R., and J. Selvakumar. "A Preliminary Study of Oscillators, Phase and Frequency Detector, and Charge Pump for Phase-Locked Loop (PLL) Applications." In Lecture Notes in Electrical Engineering. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7251-2_2.

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Prabaharan, Priyadharshini, Saravanan Kathiah, S. Raju, and Sankaran Aniruddhan. "A Current-Mode-Logic-Based PFD–Charge Pump Circuit for Low-Reference Spur PLLs." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-97-5269-0_4.

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Saldanha, Alan, Vijil Gupta, and Vinod Kumar Joshi. "Comparison of Low Current Mismatch CMOS Charge Pumps for Analog PLLs Using 180 nm Technology." In Advances in Intelligent Systems and Computing. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3600-3_65.

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Timbiano Feraud, Thalia Elvira, Juan Gabriel Mollocana Lara, Pedro José Calderón Coba, and César Iván Álvarez Mendoza. "Carbon Footprint Estimation at the Salesian Continuous Training Center - San Bartolo Using System Dynamics." In Lecture Notes in Networks and Systems. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-87065-1_28.

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Abstract The Carbon Footprint measures greenhouse gas emissions, which are harmful to the environment and contribute to climate change, and is a solution to evaluate the production of GHGs, thus implementing mitigation actions to counteract their environmental impacts. This study focused on evaluating GHG emissions mitigation strategies at the Salesian Center for Continuing Education in San Bartolo. Data, obtained through interviews and utility bills, covered electricity, water and fuel consumption, as well as paper, plastic and organic waste. A system dynamics model was applied to identify th
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"Time amplified charge pump PLL." In Phase-Locked Frequency Generation and Clocking: Architectures and circuits for modern wireless and wireline systems. Institution of Engineering and Technology, 2020. http://dx.doi.org/10.1049/pbcs064e_ch23.

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Conference papers on the topic "Charge Pump PLL"

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Ding, Zhenfeng, and Jianyang Zhou. "A High-Output-Swing and Low-Current-Mismatch Charge Pump for PLL." In 2024 IEEE 18th International Conference on Anti-counterfeiting, Security, and Identification (ASID). IEEE, 2024. https://doi.org/10.1109/asid63618.2024.10839664.

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Enache, Andrei, Florin Drăghici, and Gheorghe Brezeanu. "A Calibration Technique of Charge-Pump PLL Readout Circuit for SiC-MOS Capacitor Hydrogen Sensors." In 2024 International Semiconductor Conference (CAS). IEEE, 2024. http://dx.doi.org/10.1109/cas62834.2024.10736881.

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Singhal, Archana, Jyoti Sharma, Dheeraj Singh Rajput, Dharmendra Boolchandani, and C. Periasamy. "Design and Analysis of Fast Settling Wideband PLL Using a Novel Low Mismatch Current Charge Pump." In 2024 IEEE Third International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES). IEEE, 2024. http://dx.doi.org/10.1109/icpeices62430.2024.10719110.

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Sun, Depeng, Feng Bu, Qixian Ye, et al. "19.11 A 13GHz Charge-Pump PLL Achieving $\mathbf{15.8}\mathbf{fs}_{\mathbf{rms}}$ Integrated Jitter and -98.5dBc Reference Spur." In 2025 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2025. https://doi.org/10.1109/isscc49661.2025.10904662.

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Li, Fanyang, Shuwen Wu, and Kaiji Liu. "A Low-Voltage and LDO-Less Wireless Pressure Sensor Readout System with Current Mode Pseudo PLL and Charge Pump Powered UWB Data Transmission for Implantable Health Monitoring." In 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2024. http://dx.doi.org/10.1109/mwscas60917.2024.10658898.

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Luo, Pu. "A chopped charge pump of PLL." In 2015 Joint International Mechanical, Electronic and Information Technology Conference. Atlantis Press, 2015. http://dx.doi.org/10.2991/jimet-15.2015.191.

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Wu, Xiu-Long, Jun-Ning Chen, Dao-Ming Ke, and Xing-Jian Zhang. "Design of High-Speed Charge-Pump in PLL." In 2008 4th International Conference on Wireless Communications, Networking and Mobile Computing (WiCOM). IEEE, 2008. http://dx.doi.org/10.1109/wicom.2008.555.

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Liu, Xiaoming, Jing Jin, Dongpo Chen, and Jianjun Zhou. "Operational amplifiers used in PLL charge pump circuits." In 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2010. http://dx.doi.org/10.1109/icsict.2010.5667665.

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Fazeel, H. Md Shuaeb, Leneesh Raghavan, Chandrasekaran Srinivasaraman, and Manish Jain. "Reduction of Current Mismatch in PLL Charge Pump." In 2009 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2009. http://dx.doi.org/10.1109/isvlsi.2009.45.

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Xiaoliang Xu, Huihua Liu, and Weifeng Tan. "Parameters design of 1.25GHz low jitter charge pump PLL." In 2011 International Conference on Electric Information and Control Engineering (ICEICE). IEEE, 2011. http://dx.doi.org/10.1109/iceice.2011.5777576.

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