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Journal articles on the topic 'Charge Pump PLL'

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Published: 3 June 2025

Last updated: 1 August 2025

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1

Hati, A., and B. C. Sarkar. "Pump current modulated charge pump PLL." Electronics Letters 35, no. 18 (1999): 1498. http://dx.doi.org/10.1049/el:19990997.

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2

Hwang, M. S., J. Kim, and D. K. Jeong. "Reduction of pump current mismatch in charge-pump PLL." Electronics Letters 45, no. 3 (2009): 135. http://dx.doi.org/10.1049/el:20092727.

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3

Park, Sung Sik, Ju Sang Lee, and Sang Dae Yu. "Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (2018): 4120. http://dx.doi.org/10.11591/ijece.v8i6.pp4120-4132.

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In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect c

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4

Park, Sung Sik, Ju Sang Lee, and Sang Dae Yu. "Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (2018): 4120–32. https://doi.org/10.11591/ijece.v8i6.pp4120-4132.

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In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect c

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5

D S, Rajeshwari, P. V Rao, and Ramesh Karmungi. "10Ghz Charge Pump PLL for Low Jitter Applica-tions." International Journal of Engineering & Technology 7, no. 2.12 (2018): 348. http://dx.doi.org/10.14419/ijet.v7i2.12.11349.

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This paper presents design and simulation of charge pump architectures for 10GHz Charge Pump Phase locked Loop. Differential delay cell VCO with symmetric load and Programmable frequency divider are efficiently implemented in loop. Able to achieve Peak jitter of the Divider 10ns, Peak jitter of VCO 205ps at 1GHz.Charge pump is analysed in loop by reduced current mismatch using improved high swing cascode structure including start up circuitand it has low turn ON voltage and high ouput impedance to provide stable voltage.Charge pump results current mismatch less than 0.05%.10GHz DPLL is simulat

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6

N.AshokKumar, Dr, and Dr A.Kavitha. "An Efficient and Novel Design of Loop Filter, Charge Pump and VCO for PLL Using CMOS Technology." International Journal of Engineering & Technology 7, no. 2.20 (2018): 339. http://dx.doi.org/10.14419/ijet.v7i2.20.16729.

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This article presents an occasional energy charge pump, low pass filter and voltage supervised generator for little energy section loop. PLL are generally used for synchronization and regulate of grid- associated power electronic techniques. The article enfolds the whole circuit figure of circle filter, charge pump and voltage restrict oscillator through 1.8v energy stock. This kind uses 0.18um CMOS technology. In recent times, voltage restricted oscillator are employed for phase lock loop. A great viable loop-bandwidth plan method, derivative from a distinct -time PLL model, additional comple

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7

AshokKumar, N., and A. Kavitha. "An Efficient and Novel Design of Loop Filter, Charge Pump and VCO for PLL Using CMOS Technology." International Journal of Engineering & Technology 7, no. 3.1 (2018): 39. http://dx.doi.org/10.14419/ijet.v7i3.1.16793.

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This article presents an occasional energy charge pump, low pass filter and voltage supervised generator for little energy section loop. PLL are generally used for synchronization and regulate of grid- associated power electronic techniques. The article enfolds the whole circuit figure of circle filter, charge pump and voltage restrict oscillator through 1.8v energy stock. This kind uses 0.18um CMOS technology. In recent times, voltage restricted oscillator are employed for phase lock loop. A great viable loop-bandwidth plan method, derivative from a distinct -time PLL model, additional comple

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8

Charlamov, Jevgenij. "PLL DESIGN AND INVESTIGATION IN CMOS." Mokslas - Lietuvos ateitis 2, no. 1 (2010): 54–58. http://dx.doi.org/10.3846/mla.2010.012.

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In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm2, power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.

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9

Gyoung-Tae Roh, Yong Hoon Lee, and Beomsup Kim. "Optimum phase-acquisition technique for charge-pump PLL." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 44, no. 9 (1997): 729–40. http://dx.doi.org/10.1109/82.625005.

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10

Chen, Y., P. I. Mak, and Y. Zhou. "Self-tracking charge pump for fast-locking PLL." Electronics Letters 46, no. 11 (2010): 755. http://dx.doi.org/10.1049/el.2010.3562.

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11

Ali, E., D. Narwani, A. M. Bughio, N. Nizamani, S. H. Siyal, and A. R. Khatri. "Analyzing the Impact of Loop Parameter Variations on the Transient Response of Second Order Voltage- Switched CP-PLL." Engineering, Technology & Applied Science Research 11, no. 1 (2021): 6687–90. https://doi.org/10.48084/etasr.3969.

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The analysis of the behavior of Charge Pump Phase-Locked Loop (CP-PLL) is a challenging task due to its mixed-signal architecture. Out of its two types, i.e. Current Switched CP-PLL (CSCP-PLL) and Voltage Switched CP-PLL (VSCP-PLL), the prior produces symmetrical pump currents, resulting in an appropriate transient performance to be analyzed. The loop parameters are important to set the gain, target frequency, and assure the stability of the system. The more important is the bandwidth of the loop, which is dependent on the loop filter parameters to perform stable operation and locking time. In

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12

CHANG, ROBERT C., LUNG-CHIH KUO, and HOU-MING CHEN. "A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP." Journal of Circuits, Systems and Computers 14, no. 05 (2005): 997–1006. http://dx.doi.org/10.1142/s0218126605002738.

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A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can b

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13

An, Seong-Jin, and Yong-shig Choi. "Loop Filter Voltage Variation Compensated PLL with Charge Pump." Journal of the Korea Institute of Information and Communication Engineering 20, no. 10 (2016): 1935–40. http://dx.doi.org/10.6109/jkiice.2016.20.10.1935.

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14

Van Paemel, M. "Analysis of a charge-pump PLL: a new model." IEEE Transactions on Communications 42, no. 7 (1994): 2490–98. http://dx.doi.org/10.1109/26.297861.

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15

Joram, N., R. Wolf, and F. Ellinger. "High swing PLL charge pump with current mismatch reduction." Electronics Letters 50, no. 9 (2014): 661–63. http://dx.doi.org/10.1049/el.2014.0804.

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16

Mestice, Marco, Gabriele Ciarpi, Daniele Rossi, and Sergio Saponara. "An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments." Electronics 13, no. 4 (2024): 744. http://dx.doi.org/10.3390/electronics13040744.

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Among all the functions that electronics currently perform, clock synthesis has a backbone role. Charge pump phase-locked loops (CP-PLL) are widely used to accomplish clock synthesis thanks to their versatility. One of the most critical parts of CP-PLLs is the charge pump, which greatly influences the system’s performance. Even though several high-performance charge pumps have been proposed in the past, with the quick spread of electronics in all the engineering fields, the design of such electronic devices has encountered several additional challenges dictated by external environmental condit

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17

Wang, Kai Yu, Zhe Nan Tang, and Tao Ge. "The Design and Simulation of a CMOS Digital PLL." Applied Mechanics and Materials 48-49 (February 2011): 1227–30. http://dx.doi.org/10.4028/www.scientific.net/amm.48-49.1227.

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In this paper, the charge-pump PLL structure is well analyzed. By using top-down method, the digital PLL is designed from frequency phase detector, charge pump, loop filter, VCO to frequency divider. Based on 0.5μm CMOS mixed signal process, the schematic and layout design is finished on Cadence IC 5.1.4.1, and Hspice is used for the simulation. The layout verification and parasitic extraction is completed on industry mainstream Calibre software. Simulation results show that the digital PLL is with a 100MHz center frequency, the locking range is between 20MHz~60MHz, the locking time is less th

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18

Ali, E., D. Narwani, A. M. Bughio, N. Nizamani, S. H. Siyal, and A. R. Khatri. "Analyzing the Impact of Loop Parameter Variations on the Transient Response of Second Order Voltage-Switched CP-PLL." Engineering, Technology & Applied Science Research 11, no. 1 (2021): 6687–90. http://dx.doi.org/10.48084/etasr.3969.

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The analysis of the behavior of Charge Pump Phase-Locked Loop (CP-PLL) is a challenging task due to its mixed-signal architecture. Out of its two types, i.e. Current Switched CP-PLL (CSCP-PLL) and Voltage Switched CP-PLL (VSCP-PLL), the prior produces symmetrical pump currents, resulting in an appropriate transient performance to be analyzed. The loop parameters are important to set the gain, target frequency, and assure the stability of the system. The more important is the bandwidth of the loop, which is dependent on the loop filter parameters to perform stable operation and locking time. In

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19

Wei, Xueming, Renchuan Yin, Lingli Hou, Weilin Xu, and Baolin Wei. "Design and Analysis of the Self-Biased PLL with Adaptive Calibration for Minimum of the Charge Pump Current Mismatch." Electronics 11, no. 14 (2022): 2133. http://dx.doi.org/10.3390/electronics11142133.

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A digital adaptive mismatch calibration (DAMC) circuit is proposed to decrease the output jitter of phase-locked loop (PLL). After amplifying the phase error with a linear time amplifier (TA), the DAMC adopts a successive approximation pulse width calibration method to reduce the mismatch current of the charge pump. The PLL prototype is fabricated in a 40nm process, the static phase error of the proposed PLL can be reduced from 358 ps to 10 ps at a 50 MHz reference clock approximately, and the RMS jitter of the PLL output is reduced from 4.91 ps to 3.59 ps, and the extended DAMC area only occu

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20

Ma, Kezheng, Rene Van Leuken, Maja Vidojkovic, et al. "A Precise and High Speed Charge-Pump PLL Model Based on SystemC/SystemC-AMS." International Journal of Electronics and Telecommunications 58, no. 3 (2012): 225–32. http://dx.doi.org/10.2478/v10177-012-0031-5.

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Abstract The Phase Locked Loop (PLL) has become an important part of electrical systems. When designing a PLL, an efficient and reliable simulation platform for system evaluation is needed. However, the closed loop simulation of a PLL is time consuming. To address this problem, in this paper, a new PLL model containing both digital and analog parts based on SystemC/SystemC-AMS (BETA version) is presented. Many imperfections such as Voltage Control Oscillator (VCO) noise or reference jitter are included in this model. By comparing with the Matlab model, the SystemC/SystemC-AMS model can dramati

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21

Guo, Aiying, Shiwei Qin, and Maoxiang Xu. "A charge pump phase-locked loop with low phase noise based on ring oscillator." Journal of Physics: Conference Series 2810, no. 1 (2024): 012003. http://dx.doi.org/10.1088/1742-6596/2810/1/012003.

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Abstract This paper presents a low-phase-noise charge pump phase-locked loop (PLL) based on a ring oscillator. It uses a 4-stage ring oscillator to provide orthogonal signals and exhibit a phase noise of -102 dBc/Hz at a carrier offset of 1 MHz. When powered by a 1.2 V DC supply, the static current of the PLL is less than 4 mA. The PLL is driven by a 40 MHz clock source and outputs a square wave at 2.56 GHz, with a phase noise of -94.8 dBc/Hz at 1 MHz offset. The circuit is implemented using a 55 nm CMOS process, with a final layout area of only 0.06 mm2.

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22

Bo Zhao and Huazhong Yang. "Supply-Noise Interactions Among Submodules Inside a Charge-Pump PLL." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 4 (2015): 771–75. http://dx.doi.org/10.1109/tvlsi.2014.2317710.

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23

Sadeghi, Vahideh Sadat, and Hossein Miar-Naimi. "A new fast locking charge pump PLL: analysis and design." Analog Integrated Circuits and Signal Processing 74, no. 3 (2013): 569–75. http://dx.doi.org/10.1007/s10470-012-0018-2.

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24

Cai, Qingsong, Zhong Yang, Minglei Zhang, Xiaoyun Jia, and Xiaohua Fan. "A fast-settling charge-pump PLL with constant loop bandwidth." Analog Integrated Circuits and Signal Processing 94, no. 1 (2017): 19–26. http://dx.doi.org/10.1007/s10470-017-1083-3.

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25

Yu, Cao, Min Su Kim, Hyung Chul Kim, and Youn Goo Yang. "A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application." Advanced Materials Research 457-458 (January 2012): 1178–82. http://dx.doi.org/10.4028/www.scientific.net/amr.457-458.1178.

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A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.

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26

Xiang, Qi, Hongxia Liu, and Yulun Zhou. "A Single-Event-Hardened Scheme of Phase-Locked Loop Microsystems for Aerospace Applications." Micromachines 13, no. 12 (2022): 2102. http://dx.doi.org/10.3390/mi13122102.

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In order to improve the ability of the phase-locked loop (PLL) microsystem applied in the aerospace environment to suppress the irradiation effect, this study presents an efficient charge pump hardened scheme by using the radiation-hardened-by-design (RHBD) technology. In this study, the sensitivity analysis of the single-event transient (SET) at different nodes of charge pump and different bombardment energies is carried out. Without changing the original structure and loop parameters, a hardened scheme of phase-locked loop to suppress the single-event effect is proposed. A digital control ci

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27

Guo, Rui, Zhenghao Lu, Shaogang Hu, Qi Yu, Limei Rong, and Yang Liu. "Design and Verification of a Charge Pump in Local Oscillator for 5G Applications." Electronics 10, no. 9 (2021): 1009. http://dx.doi.org/10.3390/electronics10091009.

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A charge pump (CP) that has low current mismatch to reduce the locking time of the Phase-Locked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a charge pump architecture consists of an operational power amplifier (OPA), switches, three D flip-flops (DFFs) and passive devices. A phase error compensation technique is introduced in the charge pump to reduce the locking time. The current mismatch, which is mainly due to the leakage current, is below 1% for a large output voltage headroom of 84% of

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28

Sahani, Jagdeep Kaur, Anil Singh та Alpana Agarwal. "A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology". Journal of Circuits, Systems and Computers 29, № 09 (2019): 2050142. http://dx.doi.org/10.1142/s021812662050142x.

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This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differentia

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29

Chen, Min, Yuntao Liu, Zhichao Li, Jingbo Xiao, and Jie Chen. "A low jitter supply regulated charge pump PLL with self-calibration." Journal of Semiconductors 37, no. 1 (2016): 015006. http://dx.doi.org/10.1088/1674-4926/37/1/015006.

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30

Koithyar, Aravinda, and T. K. Ramesh. "Analysis of Deadbeat Control for an Integer-N Charge-pump PLL." Procedia Computer Science 70 (2015): 392–98. http://dx.doi.org/10.1016/j.procs.2015.10.048.

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31

., Prathima S. R. "VLSI IMPLEMENTATION OF CHARGE PUMP PLL WITH LOW PHASE NOISE VCO." International Journal of Research in Engineering and Technology 07, no. 06 (2018): 127–37. http://dx.doi.org/10.15623/ijret.2018.0706017.

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32

Zhao, C., D. Guo, Q. Chen, et al. "A low noise 5.12 GHz PLL ASIC in 55 nm for NICA multi purpose detector project." Journal of Instrumentation 17, no. 09 (2022): C09003. http://dx.doi.org/10.1088/1748-0221/17/09/c09003.

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Abstract This paper presents the design and the test results of a low noise PLL ASIC for the optical data transmission system in NICA MPD project. In the proposed PLL, a novel charge pump circuit uses two feedback operational amplifiers to obtain low leakage current and reduce dynamic mismatch. A LC-VCO circuit combines the two-step capacitor tuning structure and the novel capacitor array unit to obtain a reasonable frequency range and an optimized Q factor performance. The PLL ASIC has been fabricated in a 55 nm CMOS process. The test results show that the PLL ASIC outputs the 5.12 GHz clock

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33

B. S., Premananda, Dhanush T. N., Vaishnavi S. Parashar, and D. Aneesh Bharadwaj. "Design and Implementation of High Frequency and Low-Power Phase-locked Loop." U.Porto Journal of Engineering 7, no. 4 (2021): 70–86. http://dx.doi.org/10.24840/2183-6493_007.004_0006.

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Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence

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34

Kucharski, M., and F. Herzel. "Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs." Advances in Radio Science 13 (November 3, 2015): 133–39. http://dx.doi.org/10.5194/ars-13-133-2015.

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Abstract. This paper presents a numerical comparison of charge pumps (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL). We consider a PLL architecture, where two parallel CPs with DC offset are used. The CP for VCO fine tuning is biased at the output to keep the VCO gain constant. For this specific architecture, only one transistor per CP is relevant for phase detector linearity. This can be an nMOSFET, a pMOSFET or a SiGe HBT, depending on the design. The HBT-based CP shows the highest linearity, whereas all charge pumps show similar devic

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35

Osmany, S. A., F. Herzel, K. Schmalz, and W. Winkler. "Phase noise and jitter modeling for fractional-N PLLs." Advances in Radio Science 5 (June 13, 2007): 313–20. http://dx.doi.org/10.5194/ars-5-313-2007.

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Abstract. We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filtered by the PLL operation. We express the rms phase error (jitter) in terms of phase noise of the reference, the VCO phase noise and the third-order loop filter parameters. In addition, we consider OFDM systems, where the PLL phase noise is reduced by digital signal processing after down-

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36

Amit Deshmukh, Alpana, Radheshyam Gamad, and Deepak Kumar Mishra. "Implementation of Phase Locked Loop for FM Demodulator Circuit." International Journal of Engineering & Technology 7, no. 4 (2019): 6519–22. http://dx.doi.org/10.14419/ijet.v7i4.28025.

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This paper aims to implement the phase locked loop for the FM demodulator circuit in Intermediate frequency band. Implementation of the proposed design is done using Simulink; further simulation is presented using Matlab as well as a comparative analysis of VCO parameters using charge pump, linearized and baseband are discussed. Charge pump based PLL design achieved phase noise of -120 dBc/Hz at 10 MHz offset frequency. Paper also presented FM demodulated output for 5000 kHz sampling frequency and 2000 KHz carrier frequency at 50 Hz deviation frequency. Simulation results are reported in tabul

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37

Wiegand, C., C. Hedayat, and U. Hilleringmann. "Non-linear behaviour of charge-pump phase-locked loops." Advances in Radio Science 8 (October 1, 2010): 161–66. http://dx.doi.org/10.5194/ars-8-161-2010.

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Abstract. The analysis of the mixed analogue and digital structure of charge-pump phase-locked loops (CP-PLL) is a challenge in modelling and simulation. In most cases the system is designed and characterized using its continuous linear model or its discrete linear model neglecting its non-linear switching behaviour. I.e., the time-varying model is approximated by a time-invariant representation using its average dynamics. Depending on what kind of phase detector is used, the scopes of validity of these approximations are different. Here, a preeminent characterization and simulation technique

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38

Shepherd, Paul, Ashfaqur Rahman, Shamim Ahmed, A. Matt Francis, Jim Holmes, and H. Alan Mantooth. "500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (2014): 000076–83. http://dx.doi.org/10.4071/hitec-tp15.

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Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and

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39

Ghaderi, Noushin, Hamid Reza Erfani-jazi, and Mehdi Mohseni-Mirabadi. "A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods." Journal of Electrical and Computer Engineering 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/8202581.

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A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a0.18 μmCMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-les

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40

Chen, Yating, Yan Han, and Sihui Wang. "A high swing charge pump with current mismatch reduction for PLL applications." IEICE Electronics Express 18, no. 4 (2021): 20200434. http://dx.doi.org/10.1587/elex.18.20200434.

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41

Vafadar, Mohammad, and Habib Adrang. "Transient Analysis of Second-Order Charge Pump PLL for Phase Step Input." International Journal of Scientific Engineering and Technology 4, no. 8 (2015): 407–12. http://dx.doi.org/10.17950/ijset/v4s8/801.

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42

HAN, Jeonghoon, Masaya MIYAHARA, and Akira MATSUZAWA. "Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator." IEICE Transactions on Electronics E97.C, no. 4 (2014): 316–24. http://dx.doi.org/10.1587/transele.e97.c.316.

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43

Loke, A. L. S., R. K. Barnes, T. T. Wee, et al. "A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking." IEEE Journal of Solid-State Circuits 41, no. 8 (2006): 1894–907. http://dx.doi.org/10.1109/jssc.2006.875289.

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44

Ali, E., F. Haddad, W. Rahajandraibe, N. Nizamani, C. Hangmann, and C. Hedayat. "Autonomous Event Driven Model of Second Order Voltage Switched Charge Pump PLL." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 12 (2020): 2903–7. http://dx.doi.org/10.1109/tcsii.2020.2992601.

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Yoon, Kwangho, and Wonchan Kim. "Charge pump boosting technique for power noise immune high-speed PLL implementation." Electronics Letters 34, no. 15 (1998): 1445. http://dx.doi.org/10.1049/el:19981057.

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Liu, P., P. Sun, J. Jung, and D. Heo. "PLL charge pump with adaptive body-bias compensation for minimum current variation." Electronics Letters 48, no. 1 (2012): 16. http://dx.doi.org/10.1049/el.2011.2835.

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Park, Jung-woong, Ho-yong Choi, and Nam-soo Kim. "Two-stage feedback-looped charge-pump for spur reduction in CMOS PLL." Analog Integrated Circuits and Signal Processing 83, no. 2 (2015): 143–48. http://dx.doi.org/10.1007/s10470-015-0517-z.

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Lee, Tzung-Je, and Chua-Chin Wang. "A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators." VLSI Design 2008 (September 24, 2008): 1–8. http://dx.doi.org/10.1155/2008/512946.

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A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper. Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively. By using separate regulators, the area and the power consumption of the regulator can be reduced. Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise. The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process. The peak-to-peak jitter (P2P jitter) of the proposed PLL is measu

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Abbas, Waseem, Zubair Mehmood, and Munkyo Seo. "A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS." Electronics 9, no. 9 (2020): 1502. http://dx.doi.org/10.3390/electronics9091502.

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A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured p

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Ting, Yang, Nian Wei, and Chang Xia. "Frequency Source Design of Fast Locking Laser Range Radar." Journal of Physics: Conference Series 2395, no. 1 (2022): 012047. http://dx.doi.org/10.1088/1742-6596/2395/1/012047.

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Abstract Given the bad ranging precision in continuous wave laser range radar systems because of the large jitter of the main oscillator frequency source, this paper introduces the fast locking method, which is based on Field Programmable Gate Array (FPGA) and modified mixed Charge Pump Phase Locked Loop (CPPLL), effectively improving the locking time of PLL frequency source. The input frequency is generated by a temperature compensation quartz crystal oscillator with high stability frequency (TCXO). It improves the PLL performance using the two-order active filter, reduces the phase detector

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