Log in

Relevant bibliographies by topics / Checking circuit / Journal articles

To see the other types of publications on this topic, follow the link: Checking circuit.

Journal articles on the topic 'Checking circuit'

Author: Grafiati

Published: 4 June 2021

Last updated: 14 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Checking circuit.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Gavrilenkov, Sergey I., Elizaveta O. Petrenko, and Evgeny V. Arbuzov. "A Digital Device for Automatic Checking of Homework Assignments in the Digital Circuits Course." ITM Web of Conferences 35 (2020): 04009. http://dx.doi.org/10.1051/itmconf/20203504009.

Full text

Abstract:

This paper considers a digital device for automatic checking of homework assignments in the digital circuits course. The assignment is to make a digital circuit corresponding to a given logical expression; the circuit is comprised of elementary logic gates. The process of manual testing the built circuit is very labor-intensive because checking a circuit with N inputs variables requires checking the correctness of the output variable for 2N cases. We propose automating this pro-cess with a special digital device. The device is comprised of a microcontroller connected to the circuit tested. The

APA, Harvard, Vancouver, ISO, and other styles

2

Gu, Yu Wan, Guo Dong Shi, Shi Yan Xie, and Yu Qiang Sun. "Sequential Circuit Equivalence Checking Method Based on Minimizing Automation." Advanced Materials Research 204-210 (February 2011): 251–54. http://dx.doi.org/10.4028/www.scientific.net/amr.204-210.251.

Full text

Abstract:

A parallel checking method is proposed in the paper, in order to improve the speed of sequential circuit checking. The graph form of sequential circuits is isomorphic to finite state machine; a parallel sequential circuit equivalence checking method is designed using parallel minimization method of finite state machine. At last, the effectiveness and feasibility of the method is proved with an instance.

APA, Harvard, Vancouver, ISO, and other styles

3

Busaba, Fadi, and Parag K. Lala. "Techniques for Self-Checking Combinational Logic Synthesis." VLSI Design 2, no. 3 (1994): 209–21. http://dx.doi.org/10.1155/1994/29238.

Full text

Abstract:

This paper presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit error at the output. If the outputs are encoded using Berger code or m-out-of-n code, then the proposed technique will enable on-line detection of faults in the circuit. An algorithm for indicating whether a certain fault at an input will create bidirectional error at the output is presented. An input encoding algorithm and an output encoding algorithm that ensure that every fault will either produce single bit error o

APA, Harvard, Vancouver, ISO, and other styles

4

Fan, Quan Run, Feng Pan, and Xin Dong Duan. "Using Logic Synthesis and Circuit Reasoning for Equivalence Checking." Advanced Materials Research 201-203 (February 2011): 836–40. http://dx.doi.org/10.4028/www.scientific.net/amr.201-203.836.

Full text

Abstract:

The existing SAT based algorithms combines two circuits into a miter, and then convert the miter into a CNF formula. After that, a SAT solver is invoked to check the satisfiability of the CNF formula. However, when a miter is converted into CNF formula, the structure information of the circuit is lost. Therefore,we are motivated to solve the problem of miter satisfiability using circuit reasoning. We use logic synthesis first to simplify the circuit, and then use a backtracking method to check the satisfiability of the miter. The preliminary experimental result sindicate that our approach is e

APA, Harvard, Vancouver, ISO, and other styles

5

Morosow, A., V. V. Saposhnikov, Vl V. Saposhnikov, and M. Goessel. "Self-Checking Combinational Circuits with Unidirectionally Independent Outputs." VLSI Design 5, no. 4 (1998): 333–45. http://dx.doi.org/10.1155/1998/20389.

Full text

Abstract:

In this paper we propose a structure dependent method for the systematic design of a self-checking circuit which is well adapted to the fault model of single gate faults and which can be used in test mode.According to the fault model considered, maximal groups of independent and unidirectionally independent outputs of an arbitrarily given combinational circuit are determined. A parity bit is added to every group of independent outputs. A few additional outputs are added to every group of unidirectionally independent outputs. In the error free case, these groups of unidirectional independent ou

APA, Harvard, Vancouver, ISO, and other styles

6

Khan, Wilayat, Farrukh Aslam Khan, Abdelouahid Derhab, and Adi Alhudhaif. "CoCEC: An Automatic Combinational Circuit Equivalence Checker Based on the Interactive Theorem Prover." Complexity 2021 (May 25, 2021): 1–12. http://dx.doi.org/10.1155/2021/5525539.

Full text

Abstract:

Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean functions, is often desired when reliable and correct hardware components are required. The most common approaches to equivalence checking are based on simulation and model checking, which are constrained due to the popular memory and state explosion problems. Furthermore, such tools are often not user-friendly, thereby making it tedious to check the equivalence of large formulas or circuits. An alternative is to use mathematical tools, called interactive theorem provers, to prove the equivalence of

APA, Harvard, Vancouver, ISO, and other styles

7

Burch, J. R., E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill. "Symbolic model checking for sequential circuit verification." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 4 (1994): 401–24. http://dx.doi.org/10.1109/43.275352.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Busaba, Fadi, Parag K. Lala, and Alvernon Walker. "On Self-Checking Design of CMOS Circuits for Multiple Faults." VLSI Design 7, no. 2 (1998): 151–61. http://dx.doi.org/10.1155/1998/37237.

Full text

Abstract:

A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally self-checking. Experiemntal results show the overhead, delay and power consumption fo

APA, Harvard, Vancouver, ISO, and other styles

9

Kini, MVittal, MarkS Myers, and Sunil Shenoy. "4821271 Methods and circuits for checking integrated circuit chips having programmable outputs." Microelectronics Reliability 29, no. 6 (1989): iii—iv. http://dx.doi.org/10.1016/0026-2714(89)90153-4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Pan, Zhong Liang, and Ling Chen. "A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams." Applied Mechanics and Materials 29-32 (August 2010): 1040–45. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.1040.

Full text

Abstract:

The formal verification is able to check whether the implementation of a circuit design is functionally equivalent to an earlier version described at the same level of abstraction, it can show the correctness of a circuit design. A new circuit verification method based on cone-oriented circuit partitioning and decision diagrams is presented in this paper. First of all, the structure level of every signal line in a circuit is computed. Secondly, the circuit is partitioned into a lot of cone structures. The multiple-valued decision diagram corresponding to every cone structure is generated. The

APA, Harvard, Vancouver, ISO, and other styles

11

Sapozhnikov, Valeriy, Vladimir Sapozhnikov, Dmitriy Efanov, and Ruslan Abdullaev. "The specificities of organization of concurrent error detection systems for combinational circuits based on polynomial codes." Proceedings of Petersburg Transport University, no. 3 (September 20, 2018): 432–45. http://dx.doi.org/10.20295/1815-588x-2018-3-432-445.

Full text

Abstract:

Objective: To study the speciﬁcities of polynomial codes application during the organization of concurrent error detection systems for combinational logic circuits of automation and computer engineering. Methods: The methods of information theory and coding, the theory of discrete devices and diagnostic engineering of discrete systems were applied. Results: The possibilities of using polynomial codes in the process of combinational logic circuits control organization were analyzed. Some essential properties, inherent in generator polynomials, which make it possible to synthesize self-checking

APA, Harvard, Vancouver, ISO, and other styles

12

Stankovic, Tatjana, Mile Stojcev, and Goran Djordjevic. "On VHDL synthesis of self-checking two-level combinational circuits." Facta universitatis - series: Electronics and Energetics 17, no. 1 (2004): 69–79. http://dx.doi.org/10.2298/fuee0401069s.

Full text

Abstract:

Concurrent error detection (CED) is an important technique in the design of system in which dependability and data integrity are important. Using the separable code for CED has the advantage that no decoding is needed to get the normal output bits. In this paper, we address the problem of synthesizing totally self-checking two level combinational circuits starting from a VHDL description. Three schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a totally self-checking comparator. The second scheme for synthesizing combinational circuit

APA, Harvard, Vancouver, ISO, and other styles

13

Metra, Cecilia, Michele Favalli, and Bruno Riccò. "Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits." VLSI Design 11, no. 1 (2000): 23–34. http://dx.doi.org/10.1155/2000/42016.

Full text

Abstract:

In this paper we propose signal coding and CMOS gates that are suitable to self-checking circuits with combinational functional blocks implemented also by next generation, very deep submicron technology. In particular, our functional blocks satisfy the Strongly Fault-Secure property with respect to a wide set of possible, internal faults including not only conventional stuck-ats, but also transistor stuck-ons, transistor stuck-opens, resistive bridgings, delays, crosstalks and transient faults, that are very likely to affect next generation ICs. Compared to alternative, existing solutions, tha

APA, Harvard, Vancouver, ISO, and other styles

14

Sun, Tingting, Zihua Song, Yanghua Tian, et al. "Basolateral amygdala input to the medial prefrontal cortex controls obsessive-compulsive disorder-like checking behavior." Proceedings of the National Academy of Sciences 116, no. 9 (2019): 3799–804. http://dx.doi.org/10.1073/pnas.1814292116.

Full text

Abstract:

Obsessive-compulsive disorder (OCD) affects ∼1 to 3% of the world’s population. However, the neural mechanisms underlying the excessive checking symptoms in OCD are not fully understood. Using viral neuronal tracing in mice, we found that glutamatergic neurons from the basolateral amygdala (BLAGlu) project onto both medial prefrontal cortex glutamate (mPFCGlu) and GABA (mPFCGABA) neurons that locally innervate mPFCGlu neurons. Next, we developed an OCD checking mouse model with quinpirole-induced repetitive checking behaviors. This model demonstrated decreased glutamatergic mPFC microcircuit a

APA, Harvard, Vancouver, ISO, and other styles

15

Zhou, Ning, Xinyan Gao, Jinzhao Wu, Jianchao Wei, and Dakui Li. "Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions." Journal of Applied Mathematics 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/194574.

Full text

Abstract:

We introduce an approach exploiting the power of polynomial ring algebra to perform SystemVerilog assertion verification over digital circuit systems. This method is based on Groebner bases theory and sequential properties checking. We define a constrained subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using Groebner bases for concurrent SVAs checking. Case studies show that computer algebra can provide canonical symbolic representations for b

APA, Harvard, Vancouver, ISO, and other styles

16

ZHAO, Yang, Tao LV, Hua-Wei LI, and Xiao-Wei LI. "A Novel Circuit SAT Solver in Unbounded Model Checking." Chinese Journal of Computers 32, no. 6 (2009): 1110–18. http://dx.doi.org/10.3724/sp.j.1016.2009.01110.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Burgholzer, Lukas, and Robert Wille. "QCEC: A JKQ tool for quantum circuit equivalence checking." Software Impacts 7 (February 2021): 100051. http://dx.doi.org/10.1016/j.simpa.2020.100051.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Busaba, F. Y., and P. K. Lala. "Self-checking sequential circuit design usingm-out-of-ncodes." Electronics Letters 29, no. 1 (1993): 7–9. http://dx.doi.org/10.1049/el:19930005.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Li, Ming-Cui, and Ri-Gui Zhou. "Novel Synthesis Methodology for Fault Tolerant Reversible Circuits by Bounded Model Checking for Linear Temporal Logic." Journal of Circuits, Systems and Computers 24, no. 06 (2015): 1550091. http://dx.doi.org/10.1142/s0218126615500917.

Full text

Abstract:

Reversible circuit is of interest due to the characteristics of low energy consumption. This paper proposes a new scheme for synthesizing fault tolerant reversible circuits. A two-step method is put forward to convert an irreversible function into a parity-preserving reversible circuit. By introducing model checking for linear temporal logic, we construct a finite state machine to synthesize small reversible gates from elementary 1-qubit and 2-qubit gates, which is more automatic than the methods proposed previously. Constrains are increased so as to reduce the synthesis time in the two step m

APA, Harvard, Vancouver, ISO, and other styles

20

Xu, Yongsheng, Guowu Yang, Zhengwei Chang, Desheng Zheng, and Wensheng Guo. "Terminal Satisfiability in GSTE." Journal of Applied Mathematics 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/725275.

Full text

Abstract:

Generalized symbolic trajectory evaluation(GSTE) is an extension of symbolic trajectory evaluation (STE) and a method of model checking. GSTE specifications are given as assertion graphs. There are four efficient methods to verify whether a circuit model obeys an assertion graph in GSTE, Model Checking Strong Satisfiability (SMC), Model Checking Normal Satisfiability (NMC), Model Checking Fair Satisfiability (FMC), and Model Checking Terminal Satisfiability (TMC). SMC, NMC, and FMC have been proved and applied in industry, but TMC has not. This paper gives a six-tuple definition and presents a

APA, Harvard, Vancouver, ISO, and other styles

21

Avaritsiotis, J. N. "Thick Film Circuit Layout and Extraction of Parameters Using The Magic Layout Editor." Active and Passive Electronic Components 14, no. 2 (1990): 67–80. http://dx.doi.org/10.1155/1990/36026.

Full text

Abstract:

A Technology file for the Magic layout editor has been developed in order to enable thick film circuit designers to evolve fast solutions for layout with design rule checking, and plotting of the masks of multilayer hybrid circuits. The hybrid design system developed provides for device placement, and automatic routing techniques, in thick film circuits. Device placement is done by recalling from the library the pad pattern that corresponds to the device to be positioned. Automatic routing is implemented not only in multilayered circuits but also in single-layer technology (i.e. two possible t

APA, Harvard, Vancouver, ISO, and other styles

22

BISSOMBOLO, Abel, Takashi FURUYAMA, Toshiro SHIRABE, Naoko FUYUNO, Tsuyoshi HARA, and Sukeyuki MORI. "A "Checking System" for Circuit Control of Fluorite Processing Plants." RESOURCES PROCESSING 43, no. 4 (1996): 173–80. http://dx.doi.org/10.4144/rpsj1986.43.173.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Sapozhnikov, Valeriy, Vladimir Sapozhnikov, Dmitriy Efanov, and Dmitriy Pyvovarov. "Application of constant-weight code "1-out-if-5" for the organization of combinational circuits check." Proceedings of Petersburg Transport University, no. 2 (June 20, 2017): 307–19. http://dx.doi.org/10.20295/1815-588x-2017-2-307-319.

Full text

Abstract:

Objective: To study specificities of “1-out of-5”equilibrium code application in the process of concurrent error detection of combinational logic circuits organization. Methods: Information and coding theories, as well as technical diagnostics of discrete systems were applied. Results: It was suggested to apply a “1-out of-5”equilibrium code in organizing of combinational circuits control by means of Boolean complement method, the tester of which has a simple structure and needs five testing patterns for its full check. The calculation method of Boolean complement functions was given; the form

APA, Harvard, Vancouver, ISO, and other styles

24

Dai, Zhi Quan, Yong Guan, Sheng Zhen Jin, Zhi Ping Shi, Xiao Juan Li, and Jie Zhang. "SpaceWire State Machine Verification Based on Model Checking." Applied Mechanics and Materials 55-57 (May 2011): 2192–96. http://dx.doi.org/10.4028/www.scientific.net/amm.55-57.2192.

Full text

Abstract:

SpaceWire is a high-speed data transmission bus standard proposed by ESA for the aerospace applications. Hosted by the National Astronomical Observatories, Chinese Academy of Sciences, the Space Solar Telescope project takes the SpaceWire bus standard as space communication link. The SpaceWire communication circuit implemented by our group is a part of the SST project. In order to improve the fault detection and fault correction capacity and the reliability of the SpaceWire bus, we add a more error analysis and data storage module into the original six state modules of the standard protocol in

APA, Harvard, Vancouver, ISO, and other styles

25

Kim, Hyunho. "Passive device embedded substrate for application of RF module." Circuit World 42, no. 2 (2016): 84–88. http://dx.doi.org/10.1108/cw-07-2015-0033.

Full text

Abstract:

Purpose The purpose of this study is to form fabrication and electrical characteristics of passive device embedded substrate that is embedded chip bead inductor and chip capacitor inside substrate for the application of radio frequency (RF) modules. Design/methodology/approach Passive device embedded substrate was fabricated using embedding process that consists of lamination process, laser drilling at the electrode Cu pads of passive components, electro-less Cu plating formation process such as photolithography, electrolytic Cu plating and etching. Impedance and capacitance characteristics of

APA, Harvard, Vancouver, ISO, and other styles

26

Ding, Zai Ming, and Jin Feng Liu. "Study and Design of Checking and Testing Car for Whole Circuit." Applied Mechanics and Materials 575 (June 2014): 554–57. http://dx.doi.org/10.4028/www.scientific.net/amm.575.554.

Full text

Abstract:

With the extensive application of electronic, computer and electromechanical integration technology in the automobile industry, the concept and mode of detecting and repairing to auto have a fundamental shift. So the corresponding professional teaching methods should be improved. In view of the present situation that automobile teaching equipment is not suitable for the new situation, we study and design the checking and testing car for whole circuit. The car based on a typical vehicle has a further development. And it has a new design, compact structure and convenient operating way, which als

APA, Harvard, Vancouver, ISO, and other styles

27

Thornton, M. A., R. Drechsler, and W. Günther. "Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs." VLSI Design 14, no. 1 (2002): 53–64. http://dx.doi.org/10.1080/10655140290009800.

Full text

Abstract:

A probabilistic equivalence checking method is developed based on the use of partial Haar Spectral Diagrams (HSDs). Partial HSDs are defined and used to represent a subset of Haar spectral coefficients for two Boolean functions. The resulting coefficients are then used to compute and to iteratively refine the probability that two functions are equivalent. This problem has applications in both logic synthesis and verification. The method described here can be useful for the case where two candidate functions require extreme amounts of memory for a complete BDD representation. Experimental resul

APA, Harvard, Vancouver, ISO, and other styles

28

Busaba, Fadi Y., and Parag K. Lala. "Self-checking combinational circuit design for single and unidirectional multibit error." Journal of Electronic Testing 5, no. 1 (1994): 19–28. http://dx.doi.org/10.1007/bf00971960.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Liu, Huiqun, Kai Zhu, and D. F. Wong. "FPGA Partitioning with Complex Resource Constraints." VLSI Design 11, no. 3 (2000): 219–35. http://dx.doi.org/10.1155/2000/12198.

Full text

Abstract:

In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Increm

APA, Harvard, Vancouver, ISO, and other styles

30

Wang, Qiang, Sheng Li Song, and Wei Zhao. "A Method to Measure Rotary Speed and Torque Using JC Sensors." Advanced Materials Research 142 (October 2010): 170–73. http://dx.doi.org/10.4028/www.scientific.net/amr.142.170.

Full text

Abstract:

A method for rotary speed and torque measuring using JC sensors was introduced in the paper. The approximate sine signals output by JC sensors are transformed into rectangular signals by the transform circuit. The checking circuit consists of an 8031 singlechip, it determines the rotary speed by measuring the frequency of the rectangular signals, and determines torque by measuring their pulse width.

APA, Harvard, Vancouver, ISO, and other styles

31

Majidov, Abdullo Sh, and Yury P. Gusev. "METHOD OF ASYNCHRONOUS ENGINES EQUIVALENCY FOR CALCULATING SHORT CIRCUIT CURRENT IN A SYSTEM OF BALANCE-OF-PLANT NEEDS." Vestnik Chuvashskogo universiteta, no. 3 (August 25, 2020): 102–15. http://dx.doi.org/10.47026/1810-1909-2020-3-102-115.

Full text

Abstract:

In short-circuiting in power plants of balance-of-power plant needs three-phase asynchronous motors with a short-closed rotor have a significant influence on the nature of the process and the magnitude of the short circuit current. In the system of balance-of-plant needs it is necessary to take into account the components of short circuit current from asynchronous motors when selecting and checking switches, as well as when selecting and checking current-carrying parts (cables, complete current wires, etc.) not only at the initial moment of the short circuit, but at the time of its shutdown as

APA, Harvard, Vancouver, ISO, and other styles

32

Haghparast, Majid, and Soghra Shoaei. "Design of a New Parity Preserving Reversible Full Adder." Journal of Circuits, Systems and Computers 24, no. 01 (2014): 1550006. http://dx.doi.org/10.1142/s0218126615500061.

Full text

Abstract:

Power dissipation is one of the important issues in VLSI design. Reversible logic has zero power dissipation; therefore, nowadays, researchers attend to it in order to optimize the internal power consumption. On the other hand, fault tolerance is a solution for error detection in digital systems. In many systems, fault tolerance is achieved by parity checking. This article proposes a new parity-preserving reversible full adder circuit. For many years, researchers assumed that the quantum cost (QC) of the parity-preserving reversible full adder is 11. In this article we offered a new parity-pre

APA, Harvard, Vancouver, ISO, and other styles

33

Chowdhury, Kuladeep Roy, Debduti De, and Sourangshu Mukhopadhyay. "Parity Checking and Generating Circuit with Nonlinear Material in All-Optical Domain." Chinese Physics Letters 22, no. 6 (2005): 1433–35. http://dx.doi.org/10.1088/0256-307x/22/6/037.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Cheema, M. S., and P. K. Lala. "Totally self-checking CMOS circuit design for breaks and stuck-on faults." IEEE Journal of Solid-State Circuits 27, no. 8 (1992): 1203–6. http://dx.doi.org/10.1109/4.148330.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Peng, Yun Feng, Chang Shu, and Xiang Lin Tan. "Study of Audio Circuit Board Testing System of some Station Based on DSP." Applied Mechanics and Materials 513-517 (February 2014): 3203–6. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.3203.

Full text

Abstract:

In this paper, the developed audio circuit board testing system of some station based on DSP is used to realizing the auto acquisition and testing of the parameters of audio signal, and we use touching screen to realize man-machine interactive and real-time display testing results. The detecting process accurate and quick , so it can be widely used in the testing , checking, maintenance, fault location and so on of the stations audio circuit board.

APA, Harvard, Vancouver, ISO, and other styles

36

Gao, Xinyan, Ning Zhou, Jinzhao Wu, and Dakui Li. "Wu’s Characteristic Set Method for SystemVerilog Assertions Verification." Journal of Applied Mathematics 2013 (2013): 1–14. http://dx.doi.org/10.1155/2013/740194.

Full text

Abstract:

We propose a verification solution based on characteristic set of Wu’s method towards SystemVerilog assertion checking over digital circuit systems. We define a suitable subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using characteristic set of polynomial system. This symbolic algebraic approach is a useful supplement to the existent verification methods based on simulation.

APA, Harvard, Vancouver, ISO, and other styles

37

Tarnick, Steffen. "Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability." VLSI Design 5, no. 4 (1998): 347–56. http://dx.doi.org/10.1155/1998/67574.

Full text

Abstract:

In self-checking systems, checkers usually do not receive all code words during normal operation. Missing code words may prevent a checker from achieving the totally self-checking property. The paper presents a novel approach to the design of embedded parity and two-rail checkers that allows a checker to receive all code words irrespective of the set of code words that is provided by the functional circuit. A checker gets all code words by an LFSR while at the same time it monitors the output of the functional circuit. Additionally, the LFSR is able to capture the error patterns of noncode wor

APA, Harvard, Vancouver, ISO, and other styles

38

Liu, Jia Xin, Shu Yu Liu, and Wei Zhao. "Research on Computer Control System of Automobile Safe Checking Process." Advanced Materials Research 403-408 (November 2011): 1285–90. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1285.

Full text

Abstract:

According to the national standard GB7258-2004 “The Safety Technology Qualification of the Automobile Run”, the Computer control system of automobile safe checking process we designed can gathers the data of stage meter exactly. It can process and store the data by computer then display and print the result of the examination. This subject mainly emphasizes on the design of the system hardware, mainly include develop a set of stable and dependable analog signal processing circuit and simulation.

APA, Harvard, Vancouver, ISO, and other styles

39

Li, Xiao Hu, Yu Jie Wang, Hai Bo Jia, and Jie Liu. "Study of Control and Detection on Firing Circuit." Applied Mechanics and Materials 214 (November 2012): 725–29. http://dx.doi.org/10.4028/www.scientific.net/amm.214.725.

Full text

Abstract:

To improve the firing circuit security and reliability, methods of control and detection was put forward for firing circuit. The electronic information relevant knowledge is applied to blasting engineering technology, including signal transmission technology, signal emitting and receiving technology and computer technology, etc. Through judging the digital signal to send and receive and using computer technology, network connections and detonating situation can be showed indirectly. So methods can reach. Besides, that can attain other purposes have, such as monitoring network, checking the sit

APA, Harvard, Vancouver, ISO, and other styles

40

Shakhmatov, Evgeniy V., and Ilya A. Popelnyuk. "ON THE CHOICE OF THE PARAMETERS OF VIBRATION DAMPERS FOR HYDRAULIC CIRCUITS OF CONTROL SYSTEMS." Journal of Dynamics and Vibroacoustics 6, no. 2 (2020): 20–25. http://dx.doi.org/10.18287/2409-4579-2020-6-2-20-25.

Full text

Abstract:

The article deals with the problem of choosing OF the parameters of vibration dampers for hydraulic circuits of control systems, taking into account the provision of dynamic accuracy of the system after their installation. The concept of a correction factor, which is the ratio of Laplace images of the corresponding parameters of the working medium in the hydraulic circuit before and after the damper installation is introduced. A dependence that associate the relative deviation of the system-controlled parameter with the correction factor is obtained. A condition for checking the effectiveness

APA, Harvard, Vancouver, ISO, and other styles

41

Kutsak, Nina Yu, and Vladislav V. Podymov. "Formal Verification of Three-Valued Digital Waveforms." Modeling and Analysis of Information Systems 26, no. 3 (2019): 332–50. http://dx.doi.org/10.18255/1818-1015-2019-3-332-350.

Full text

Abstract:

We investigate a formal verification problem (mathematically rigorous correctness checking) for digital waveforms used in practical development of digital microelectronic devices (digital circuits) at early design stages. According to modern methodologies, a digital circuit design starts at high abstraction levels provided by hardware description languages (HDLs). One of essential steps of an HDLbased circuit design is an HDL code debug, similar to the same step of program development in means and importance. A popular way of an HDL code debug is based on extraction and analysis of a waveform,

APA, Harvard, Vancouver, ISO, and other styles

42

Willis, Jack. "Amplifier Performance in Terms of Two-Port Parameters." International Journal of Electrical Engineering & Education 35, no. 1 (1998): 47–70. http://dx.doi.org/10.1177/002072099803500105.

Full text

Abstract:

At high frequencies the complexity of the circuit representing a feedback amplifier is such that the concept of a feedback loop becomes meaningless, and an alternative means of checking the stability of the amplifier is needed. Representing the network as a two-port realises such a solution.

APA, Harvard, Vancouver, ISO, and other styles

43

Zhou, Ning, Jinzhao Wu, and Xinyan Gao. "Algebraic Verification Method for SEREs Properties via Groebner Bases Approaches." Journal of Applied Mathematics 2013 (2013): 1–10. http://dx.doi.org/10.1155/2013/272781.

Full text

Abstract:

This work presents an efficient solution using computer algebra system to perform linear temporal properties verification for synchronous digital systems. The method is essentially based on both Groebner bases approaches and symbolic simulation. A mechanism for constructing canonical polynomial set based symbolic representations for both circuit descriptions and assertions is studied. We then present a complete checking algorithm framework based on these algebraic representations by using Groebner bases. The computational experience result in this work shows that the algebraic approach is a qu

APA, Harvard, Vancouver, ISO, and other styles

44

Zapletina, M. A., D. V. Zhukov, and S. V. Gavrilov. "Boolean Satisfiability Methods for Modern Computer-Aided Design Problems in Microelectronics." Proceedings of Universities. ELECTRONICS 25, no. 6 (2020): 525–38. http://dx.doi.org/10.24151/1561-5405-2020-25-6-525-538.

Full text

Abstract:

Currently, the methods based on a Boolean satisfiability (SAT) problem are one of the efficient approaches to solving the problem of Boolean matching and the equivalence checking of digital circuits. In combination with classic routing algorithms and optimization techniques, the SAT methods demonstrate the results exceeding the classic routing algorithms by the operation speed and the quality of obtained results. In the paper, the analysis of the modern practice of using the SAT methods in the CAD systems for VLSI has been performed. The examples of modern SAT approaches to the problems of the

APA, Harvard, Vancouver, ISO, and other styles

45

Da-hai, Liu, Chen Zhuo-min, and Wu Song-tao. "The Design of Circuit for Checking Short in HT-7U Superconducting Tokamak device." Plasma Science and Technology 2, no. 3 (2000): 323–27. http://dx.doi.org/10.1088/1009-0630/2/3/010.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Mehra, Rekha, Shikha Jaiswal, and H. K. Dixit. "Parity checking and generating circuit with semiconductor optical amplifier in all-optical domain." Optik 124, no. 21 (2013): 4744–45. http://dx.doi.org/10.1016/j.ijleo.2013.01.089.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Zhang, Xiaoqing. "Transient Simulation of Wind Turbine Towers under Lightning Stroke." Mathematical Problems in Engineering 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/142765.

Full text

Abstract:

A simulation algorithm is proposed in this paper for lightning transient analysis of the wind turbine (WT) towers. In the proposed algorithm, the tower body is first subdivided into a discrete multiconductor system. A set of formulas are given to calculate the electrical parameters of the branches in the multiconductor system. By means of the electrical parameters, each branch unit in the multiconductor system is replaced as a coupledπ-type circuit and the multiconductor system is converted into a circuit model. Then, the lightning transient responses can be obtained in different parts on the

APA, Harvard, Vancouver, ISO, and other styles

48

Sun, Xin, Yan Li, Fang Xu Han, and Jian Li. "Computation and Analysis of Static and Dynamic Radial Stability of Power Transformer Inner Winding." Advanced Materials Research 986-987 (July 2014): 1926–29. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1926.

Full text

Abstract:

In this paper, the size of winding electromagnetic force after short circuit has been acquired through leakage field calculation and analysis on power transformer, and based on the computation results, the radial stability experimental results of large capacity power transformer inner winding short-circuit model were compared to the simulation values to guide actual product analysis and checking. With the accumulated simulation experience on this model, then a type of sfz9-80MVA power transformer inner coil static and dynamic stability has been checked to confirm the radial instability phenome

APA, Harvard, Vancouver, ISO, and other styles

49

Provelengios, George, Daniel Holcomb, and Russell Tessier. "Mitigating Voltage Attacks in Multi-Tenant FPGAs." ACM Transactions on Reconfigurable Technology and Systems 14, no. 2 (2021): 1–24. http://dx.doi.org/10.1145/3451236.

Full text

Abstract:

Recent research has exposed a number of security issues related to the use of FPGAs in embedded system and cloud computing environments. Circuits that deliberately waste power can be carefully crafted by a malicious cloud FPGA user and deployed to cause denial-of-service and fault injection attacks. The main defense strategy used by FPGA cloud services involves checking user-submitted designs for circuit structures that are known to aggressively consume power. Unfortunately, this approach is limited by an attacker’s ability to conceive new designs that defeat existing checkers. In this work, o

APA, Harvard, Vancouver, ISO, and other styles

50

Yang, Guowu, William N. N. Hung, Xiaoyu Song, and Wensheng Guo. "A Transformation-Based Approach to Implication of GSTE Assertion Graphs." Journal of Applied Mathematics 2013 (2013): 1–7. http://dx.doi.org/10.1155/2013/709071.

Full text

Abstract:

Generalized symbolic trajectory evaluation (GSTE) is a model checking approach and has successfully demonstrated its powerful capacity in formal verification of VLSI systems. GSTE is an extension of symbolic trajectory evaluation (STE) to the model checking ofω-regular properties. It is an alternative to classical model checking algorithms where properties are specified as finite-state automata. In GSTE, properties are specified as assertion graphs, which are labeled directed graphs where each edge is labeled with two labeling functions: antecedent and consequent. In this paper, we show the co

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!