Relevant bibliographies by topics / Chip multicore

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Chip multicore'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 February 2022

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Journal articles on the topic "Chip multicore"

1

Geer, D. "Chip makers turn to multicore processors." Computer 38, no. 5 (2005): 11–13. http://dx.doi.org/10.1109/mc.2005.160.

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Park, Hyeongbae, Jing-Zhe Xu, Kil Hyun Kim, and Ju Sung Park. "On-Chip Debug Architecture for Multicore Processor." ETRI Journal 34, no. 1 (2012): 44–54. http://dx.doi.org/10.4218/etrij.12.0111.0172.

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Das, Sukanta, and Biplab K. Sikdar. "A Scalable Test Structure for Multicore Chip." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 1 (2010): 127–37. http://dx.doi.org/10.1109/tcad.2009.2034349.

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Lamela, Adrián, Óscar G. Ossorio, Guillermo Vinuesa, and Benjamín Sahelices. "Off-chip prefetching based on Hidden Markov Model for non-volatile memory architectures." PLOS ONE 16, no. 9 (2021): e0257047. http://dx.doi.org/10.1371/journal.pone.0257047.

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Non-volatile memory technology is now available in commodity hardware. This technology can be used as a backup memory for an external dram cache memory without needing to modify the software. However, the higher read and write latencies of non-volatile memory may exacerbate the memory wall problem. In this work we present a novel off-chip prefetch technique based on a Hidden Markov Model that specifically deals with the latency problem caused by complexity of off-chip memory access patterns. Firstly, we present a thorough analysis of off-chip memory access patterns to identify its complexity i
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Francois, Veronique, and Francois Laramee. "Multicore Fiber Optimization for Application to Chip-to-Chip Optical Interconnects." Journal of Lightwave Technology 31, no. 24 (2013): 4022–28. http://dx.doi.org/10.1109/jlt.2013.2280555.

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Xiao, Chun Hua, Zhang Qin Huang, and Da Li. "An Embedded Multicore Platform Exploration in Video Application Utilizing FPGA." Advanced Materials Research 505 (April 2012): 329–37. http://dx.doi.org/10.4028/www.scientific.net/amr.505.329.

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Multi-processor is not a new technology, but with the development of modern silicon technology, it is possible to integrate multiple cores in a single chip package, which is called multicore processor. Whether in the desktop personal machine, or embedded applications, multicore processor has been a general trend, due to the requirement of high performance and design problems in single-core processor. Surrounded multi-screen provides a better sense of reality, which is widely used in the surveillance, military, exhibitions, and so on. With the advantages in parallel processing, multicore techno
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Li, Shuo, Gao Chao Xu, Yu Shuang Dong, and Feng Wu. "The Review of Cache Partitioning in Multi-Core Processor." Key Engineering Materials 439-440 (June 2010): 1223–29. http://dx.doi.org/10.4028/www.scientific.net/kem.439-440.1223.

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With the development of microelectronics technology, Chip Multi-Processor (CMP) or multi-core design has become a mainstream choice for major microprocessor vendors. But in a chip-multiprocessor with a shared cache structure , the competing accesses from different applications degrade the system performance , resulting in non-optimal performance and non-predicting executing time. Cache partitioning techniques can exclusively partition the shared cache among multiple competing applications. In this paper, we first introduce the problems caused by Cache pollution in multicore processor structure
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Kornaros, Georgios, and Dionisios Pnevmatikatos. "A survey and taxonomy of on-chip monitoring of multicore systems-on-chip." ACM Transactions on Design Automation of Electronic Systems 18, no. 2 (2013): 1–38. http://dx.doi.org/10.1145/2442087.2442088.

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Xu, Jing-Zhe, Hyeongbae Park, Seungpyo Jung, and Ju Sung Park. "Easily Adaptable On-Chip Debug Architecture for Multicore Processors." ETRI Journal 35, no. 2 (2013): 301–10. http://dx.doi.org/10.4218/etrij.13.0112.0487.

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Awadalla, Medhat, and Hanan Konsowa. "Performance Enhancement of Multicore Architecture." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 4 (2015): 669. http://dx.doi.org/10.11591/ijece.v5i4.pp669-684.

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Multicore processors integrate several cores on a single chip. The fixed architecture of multicore platforms often fails to accommodate the inherent diverse requirements of different applications. The permanent need to enhance the performance of multicore architecture motivates the development of a dynamic architecture. To address this issue, this paper presents new algorithms for thread selection in fetch stage. Moreover, this paper presents three new fetch stage policies, EACH_LOOP_FETCH, INC-FETCH, and WZ-FETCH, based on Ordinary Least Square (OLS) regression statistic method. These new fet
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Dissertations / Theses on the topic "Chip multicore"

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Rosas, Ham Demian. "Dynamic scheduling in multicore processors." Thesis, University of Manchester, 2012. https://www.research.manchester.ac.uk/portal/en/theses/dynamic-scheduling-in-multicore-processors(c96d6641-ba16-44d2-9da5-34c41fd15956).html.

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The advent of multi-core processors, particularly with projections that numbers of cores will continue to increase, has focused attention on parallel programming. It is widely recognized that current programming techniques, including those that are used for scientific parallel programming, will not allow the easy formulation of general purpose applications. An area which is receiving interest is the use of programming styles which do not have side-effects. Previous work on parallel functional programming demonstrated the potential of this to permit the easy exploitation of parallelism. This th
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Al, Khatib Iyad. "Performance Analysis of Application-Specific Multicore Systems on Chip." Doctoral thesis, KTH, Elektronik- och datorsystem, ECS, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4779.

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The last two decades have witnessed the birth of revolutionary technologies in data communications including wireless technologies, System on Chip (SoC), Multi Processor SoC (MPSoC), Network on Chip (NoC), and more. At the same time we have witnessed that performance does not always keep pace with expectations in many services like multimediaservices and biomedical applications. Moreover, the IT market has suffered from some crashes. Hence, this triggered us to think of making use of available technologies and developing new ones so that the performance level is suitable for given applications
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Kundan, Shivam. "Contention-Aware and Power-Constrained Scheduling for Chip Multicore Processors." OpenSIUC, 2019. https://opensiuc.lib.siu.edu/theses/2620.

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The parallel nature of process execution on chip multiprocessors (CMPs) has considerably boosted levels of application performance in the past decade. Generally, a certain number of computing resources are shared among the several cores of a CMP, such as shared last-level caches, shared-buses, and shared-memory. This ensures architectural simplicity while also boosting performance for multi-threaded applications. However, a consequence of sharing computing resources is that concurrently executing applications may suffer performance degradation if their collective resource requirements exceed t
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Sikder, Md Ashif Iqbal. "Emerging Technologies in On-Chip and Off-Chip Interconnection Network." Ohio University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1469028996.

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Feliu, Pérez Josué. "Contention-Aware Scheduling for SMT Multicore Processors." Doctoral thesis, Universitat Politècnica de València, 2017. http://hdl.handle.net/10251/79081.

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The recent multicore era and the incoming manycore/manythread era generate a lot of challenges for computer scientists going from productive parallel programming, over network congestion avoidance and intelligent power management, to circuit design issues. The ultimate goal is to squeeze out as much performance as possible while limiting power and energy consumption and guaranteeing a reliable execution. The increasing number of hardware contexts of current and future systems makes the scheduler an important component to achieve this goal, as there is often a combinatorial amount of different
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Rose, Benjamin Aaron. "Intra- and Inter-chip Communication Support for Asymmetric Multicore Processors with Explicitly Managed Memory Hierarchies." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/32824.

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The use of asymmetric multi-core processors with on-chip computational accelerators is becoming common in a variety of environments ranging from scientific computing to enterprise applications. The focus of current research has been on making efficient use of individual systems, and porting applications to asymmetric processors. The use of these asymmetric processors, like the Cell processor, in a cluster setting is the inspiration for the Cell Connector framework presented in this thesis. Cell Connector adopts a streaming approach for providing data to compute nodes with high computing potent
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Iqbal, Arshad. "VoIP Server HW/SW Codesign for Multicore Computing." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-94203.

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Modern technologies are growing and Voice over Internet Protocol (VoIP) technology is able to function in heterogeneous networks. VoIP gained wide popularity because it offers cheap calling rates compared to traditional telephone system and the number of VoIP subscribers has increased significantly in recent years. End users need reliable and acceptable call quality in real time communication with best Quality of Service (QoS). Server complexity is increasing to handle all client requests simultaneously and needs huge processing power. VoIP Servers will increase processing power but the engine
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Unlu, Eren. "Dynamic Bandwidth allocation algorithms for an RF on-chip interconnect." Thesis, CentraleSupélec, 2016. http://www.theses.fr/2016SUPL0006/document.

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Avec l’augmentation du nombre de cœurs, les problèmes de congestion sont commencé avec les interconnexions conventionnelles. Afin de remédier à ces défis, WiNoCoD projet (Wired RF Network-on-Chip Reconfigurable-on-Demand) a été initié par le financement de l’Agence Nationale de Recherche (ANR). Ce travail de thèse contribue à WiNoCoD projet. Une structure de contrôleur de RF est proposé pour l’interconnexion OFDMA de WiNoCoD et plusieurs algorithmes d’allocation de bande passante efficaces (distribués et centralisés) sont développés, concernant les demandes et contraintes très spécifiques de l
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Sigurðsson, Páll Axel. "Predictable Multiprocessor Platform for Safety- Critical Real- Time Systems." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-302139.

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Multicore systems excel at providing concurrent execution of applications, giving true parallelism where all cores can execute sequences of machine instructions at the same time. However, multicore systems come with their own sets of problems, most notably when cores in a system (or core tiles) share hardware components such as memory modules or Input/Output (IO) peripherals. This increased level of complexity makes it especially difficult to design and verify safety- critical systems that require real- time operation, such as flight controllers in airplanes and airbag controllers in the autom
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Polster, Robert. "Architecture of Silicon Photonic Links." Thesis, Paris 11, 2015. http://www.theses.fr/2015PA112177/document.

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Les futurs calculateurs de haute performance (HPC) devront faire face à deux défis majeurs : la densité de la bande passante d'interconnexion et les problématiques de consommation d'énergie. La photonique silicium est aujourd’hui perçue comme une solution solide pour aborder ces questions, tant du fait de ses performances que de sa viabilité économique en raison de sa compatibilité directe avec la microélectronique CMOS. Actuellement, une tendance de fond conduit à remplacer les interconnexions métalliques par des liens optiques ; cette évolution a été initiée sur des liaisons grandes distance
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Books on the topic "Chip multicore"

1

Abderazek, Ben A. Multicore systems on chip. Transworld Research Network, 2007.

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Ben Abdallah, Abderazek. Advanced Multicore Systems-On-Chip. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2.

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Multicore systems on-chip: Practical software/hardware design. Atlantis Press/World Scientific, 2010.

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Abdallah, Abderazek Ben. Multicore Systems On-Chip: Practical Software/Hardware Design. Atlantis Press, 2010. http://dx.doi.org/10.2991/978-94-91216-33-6.

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Ben Abdallah, Abderazek. Multicore Systems On-Chip: Practical Software/Hardware Design. Atlantis Press, 2013. http://dx.doi.org/10.2991/978-94-91216-92-3.

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Ali-Reza, Adl-Tabatabai, and Tichy Walter F, eds. Fundamentals of multicore software development. CRC Press, 2012.

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Multi-objective design space exploration of multiporcessor SoC architectures: The MULTICUBE approach. Springer, 2011.

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Abdallah, Abderazek Ben. Advanced Multicore Systems-On-Chip: Architecture, On-Chip Network, Design. Springer, 2018.

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Abdallah, Abderazek Ben. Advanced Multicore Systems-On-Chip: Architecture, On-Chip Network, Design. Springer, 2017.

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Pankratius, Victor, Ali-Reza Adl-Tabatabai, and Walter Tichy. Fundamentals of Multicore Software Development. Taylor & Francis Group, 2017.

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Book chapters on the topic "Chip multicore"

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Stollon, Neal. "Infineon Multicore Debug Solution." In On-Chip Instrumentation. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7563-8_14.

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Ben Abdallah, Abderazek. "Multicore SoC Organization." In Advanced Multicore Systems-On-Chip. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2_3.

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Carro, Luigi, and Mateus Beck Rutzig. "Multicore Systems on Chip." In Handbook of Signal Processing Systems. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-6859-2_17.

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Ben Abdallah, Abderazek. "Multicore SoCs Design Methods." In Advanced Multicore Systems-On-Chip. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2_2.

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Ben Abdallah, Abderazek. "Advanced Multicore SoC Interconnects." In Advanced Multicore Systems-On-Chip. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2_5.

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Uchiyama, Kunio, Fumio Arakawa, Hironori Kasahara, et al. "Chip Implementations." In Heterogeneous Multicore Processor Technologies for Embedded Systems. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0284-8_4.

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Ben Abdallah, Abderazek. "Multicore SoC Organization." In Multicore Systems On-Chip: Practical Software/Hardware Design. Atlantis Press, 2013. http://dx.doi.org/10.2991/978-94-91216-92-3_3.

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Ben Abdallah, Abderazek. "Introduction to Multicore Systems On-Chip." In Advanced Multicore Systems-On-Chip. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2_1.

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Ben Abdallah, Abderazek. "Multicore SoC On-Chip Interconnection Networks." In Advanced Multicore Systems-On-Chip. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2_4.

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Ben Abdallah, Abderazek. "Power Optimization Techniques for Multicore SoCs." In Advanced Multicore Systems-On-Chip. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2_8.

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Conference papers on the topic "Chip multicore"

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Graf, Marleson, and Luiz C. V. dos Santos. "Shared Memory Verification for Multicore Chip Designs." In Concurso de Teses e Dissertações da SBC. Sociedade Brasileira de Computação, 2021. http://dx.doi.org/10.5753/ctd.2021.15760.

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A multicore chip usually provides a shared memory abstraction implemented by a cache coherence protocol. On-chip coherence can scale gracefully as the number of cores grows, and it plays a major role for general purpose applications. Besides, multicore architectures are likely to relax constraints on store atomicity and on the ordering between loads and stores. As a result, the validation of shared memory faces two main challenges: the higher number of valid execution behaviors and the larger coherence protocol's state space. This dissertation faces those challenges and targets an important de
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Virtanen, Janne, Lauri Matilainen, Erno Salminen, and Timo D. Hamalainen. "Implementation of Multicore communications API." In 2014 International Symposium on System-on-Chip (SoC). IEEE, 2014. http://dx.doi.org/10.1109/issoc.2014.6972434.

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Marculescu, Radu. "Power management in multicore systems-on-chip." In 2010 International Conference on Green Computing (Green Comp). IEEE, 2010. http://dx.doi.org/10.1109/greencomp.2010.5598271.

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Taha, Tarek M., Raqibul Hasan, and Chris Yakopcic. "Memristor crossbar based multicore neuromorphic processors." In 2014 27th IEEE International System-on-Chip Conference (SOCC). IEEE, 2014. http://dx.doi.org/10.1109/socc.2014.6948959.

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"Session TP1C: NoC & multicore architecture." In 2015 28th IEEE International System-on-Chip Conference (SOCC). IEEE, 2015. http://dx.doi.org/10.1109/socc.2015.7406963.

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Beldianu, Spiridon F., and Sotirios G. Ziavras. "Efficient on-chip vector processing for multicore processors." In 2013 International Symposium on System-on-Chip (SoC). IEEE, 2013. http://dx.doi.org/10.1109/issoc.2013.6675260.

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Kostygov, D. V., A. M. Gruzlikov, N. V. Kolesov, and M. V. Tolmacheva. "A Power Efficient Multicore Control System on Chip." In 2019 III International Conference on Control in Technical Systems (CTS). IEEE, 2019. http://dx.doi.org/10.1109/cts48763.2019.8973274.

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Gupta, Man Prakash, Minki Cho, Saibal Mukhopadhyay, and Satish Kumar. "An Investigation of Power Migration Policies for Many-Core Processors to Manage On-Chip Thermal Profile." In ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems. ASMEDC, 2011. http://dx.doi.org/10.1115/ipack2011-52094.

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Transition from single core to multicore technology has brought daunting challenge for thermal management of microprocessor chips. The issue of power dissipation in next generation chip will be far more critical as further transition from multicore to many-core processors is soon to be expected. It is very important to obtain uniform on-chip thermal profile with low peak temperature for improved performance and reliability of many-core processors. In this paper, a proactive thermal management technique called ‘power multiplexing’ is explored for many-core processors. Power multiplexing involve
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Skeie, Tor, Frank Olaf Sem-Jacobsen, Samuel Rodrigo, Jose Flich, Davide Bertozzi, and Simone Medardoni. "Flexible DOR routing for virtualization of multicore chips." In 2009 International Symposium on System-on-Chip - SOC 2009. IEEE, 2009. http://dx.doi.org/10.1109/socc.2009.5335673.

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Brunelli, Claudio, Roberto Airoldi, and Jari Nurmi. "Implementation and benchmarking of FFT algorithms on multicore platforms." In 2010 International Symposium on System-on-Chip - SOC. IEEE, 2010. http://dx.doi.org/10.1109/issoc.2010.5625561.

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