Relevant bibliographies by topics / Chip Multiprocessor Designs

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Chip Multiprocessor Designs'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Chip Multiprocessor Designs"

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Balston, Kyle, Mehdi Karimibiuki, Alan J. Hu, Andre Ivanov, and Steven J. E. Wilton. "Post-silicon code coverage for multiprocessor system-on-chip designs." IEEE Transactions on Computers 62, no. 2 (February 2013): 242–46. http://dx.doi.org/10.1109/tc.2012.163.

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Kao, Chi-Chou, and Yi-Ciang Lin. "Designs of Low Power Snoop for Multiprocessor System on Chip." Journal of Signal Processing Systems 88, no. 1 (April 4, 2016): 83–89. http://dx.doi.org/10.1007/s11265-016-1135-4.

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Madl, G., S. Pasricha, N. Dutt, and S. Abdelwahed. "Cross-Abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs." IEEE Transactions on Industrial Informatics 5, no. 3 (August 2009): 241–56. http://dx.doi.org/10.1109/tii.2009.2026896.

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Li, Xinyu, and Omar Hammami. "An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography." International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/631490.

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Embedded system design is increasingly based on single chip multiprocessors because of the high performance and flexibility requirements. Embedded multiprocessors on FPGA provide the additional flexibility by allowing customization through addition of hardware accelerators on FPGA when parallel software implementation does not provide the expected performance. And the overall multiprocessor architecture is still kept for additional applications. This provides a transition to software only parallel implementation while avoiding pure hardware implementation. An automatic design flow is proposed well suited for data flow signal processing exhibiting both pipelining and data parallel mode of execution. Fork-Join model-based software parallelization is explored to find out the best parallelization configuration. C-based synthesis coprocessor is added to improve performance with more hardware resource usage. The Triple Data Encryption Standard (TDES) cryptographic algorithm on a 48-PE single-chip distributed memory multiprocessor is selected as an application example of the flow.
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Tafesse, Bisrat, and Venkatesan Muthukumar. "Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration." VLSI Design 2013 (July 11, 2013): 1–16. http://dx.doi.org/10.1155/2013/936181.

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Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.
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Tsai, Wen-Chung, Ying-Cherng Lan, Yu-Hen Hu, and Sao-Jie Chen. "Networks on Chips: Structure and Design Methodologies." Journal of Electrical and Computer Engineering 2012 (2012): 1–15. http://dx.doi.org/10.1155/2012/509465.

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for on-chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.
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Akturk, Ismail, and Ozcan Ozturk. "Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design." Journal of Electronic Testing 29, no. 2 (April 2013): 177–84. http://dx.doi.org/10.1007/s10836-013-5373-0.

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Xin, Yin, and Guozhi Song. "Design of a Novel Wireless NoC Architecture for Chip Multiprocessor." Journal of Physics: Conference Series 2331, no. 1 (August 1, 2022): 012012. http://dx.doi.org/10.1088/1742-6596/2331/1/012012.

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Abstract The Network on chip is a new communication method of System on Chip. It is the main part of multi-core technology. A large number of embedded cores can be combined on a single chip. Due to the multi-hop characteristics of communication, there are some problems in the design of traditional NoC, such as high latency and power consumption. Thus, to handle the communication problem of long-distance transmission of traditional NoC, wireless Networks on Chip (WiNoC) has been proposed. Using WiNoC to design the multi-core System on Chip can significantly reduce the latency and energy consumption of the network. The advantage of using wireless network on chip is to replace the multi-hop path of traditional network on chip with wireless single hop link. However, due to the limited space on the chip and the cost, it is very important to determine the optimal number and correct location of wireless hubs. In this paper, we propose a new method to obtain the optimum configuration of a WiNoC by using the Co-evolutionary Algorithms (CA) and a wireless NoC architecture based on mesh. This work examines the effect of VC and sub-net size on WiNoC performance efficiency and energy under different packet injection rate (PIR) and the number of cores (64, 144 and 256). The simulation experiment of the algorithm proposed in the whole architecture has been implemented on the Noxim platform.
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Wolf, W., A. A. Jerraya, and G. Martin. "Multiprocessor System-on-Chip (MPSoC) Technology." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 10 (October 2008): 1701–13. http://dx.doi.org/10.1109/tcad.2008.923415.

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Hammond, Lance, Mark Willey, and Kunle Olukotun. "Data speculation support for a chip multiprocessor." ACM SIGPLAN Notices 33, no. 11 (November 1998): 58–69. http://dx.doi.org/10.1145/291006.291020.

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Dissertations / Theses on the topic "Chip Multiprocessor Designs"

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Barrow-Williams, Nick. "Proximity coherence for chip-multiprocessors." Thesis, University of Cambridge, 2011. https://www.repository.cam.ac.uk/handle/1810/241042.

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Many-core architectures provide an efficient way of harnessing the growing numbers of transistors available in modern fabrication processes; however, the parallel programs run on these platforms are increasingly limited by the energy and latency costs of communication. Existing designs provide a functional communication layer but do not necessarily implement the most efficient solution for chip-multiprocessors, placing limits on the performance of these complex systems. In an era of increasingly power limited silicon design, efficiency is now a primary concern that motivates designers to look again at the challenge of cache coherence. The first step in the design process is to analyse the communication behaviour of parallel benchmark suites such as Parsec and SPLASH-2. This thesis presents work detailing the sharing patterns observed when running the full benchmarks on a simulated 32-core x86 machine. The results reveal considerable locality of shared data accesses between threads with consecutive operating system assigned thread IDs. This pattern, although of little consequence in a multi-node system, corresponds to strong physical locality of shared data between adjacent cores on a chip-multiprocessor platform. Traditional cache coherence protocols, although often used in chip-multiprocessor designs, have been developed in the context of older multi-node systems. By redesign- ing coherence protocols to exploit new patterns such as the physical locality of shared data, improving the efficiency of communication, specifically in chip-multiprocessors, is possible. This thesis explores such a design - Proximity Coherence - a novel scheme in which L1 load misses are optimistically forwarded to nearby caches via new dedicated links rather than always being indirected via a directory structure.
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Karlsson, Martin. "Memory System Design for Chip-Multiprocessors." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Universitetsbiblioteket [distributör], 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-6250.

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NEMETH, JASON. "Location Cache Design and Performance Analysis for Chip Multiprocessors." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1217472041.

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Amstutz, Christian. "Mapping to a Time-predictable Multiprocessor System-on-Chip." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-121296.

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Traditional design methods could not cope with the recent development of multiprocessorsystems-on-chip (MPSoC). Especially, hard real-time systems that requiretime-predictability are cumbersome to develop. What is needed, is an efficient, automaticprocess that abstracts away all the implementation details. ForSyDe, a designmethodology developed at KTH, allows this on the system modelling side. The NoCSystem Generator, another project at KTH, has the ability to create automaticallycomplex systems-on-chip based on a network-on-chip on an FPGA. Both of themsupport the synchronous model of computation to ensure time-predictability. Inthis thesis, these two projects are analysed and modelled. Considering the characteristicsof the projects and exploiting the properties of the synchronous model ofcomputation, a mapping process to map processes to the processors at the differentnetwork nodes of the generated system-on-chip was developed. The mapping processis split into three steps: (1) Binding processes to processors, (2) Placement of theprocessors on net network nodes, and (3) scheduling of the processes on the nodes.An implementation of the mapping process is described and some synthetic exampleswere mapped to show the feasibility of algorithms.
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Hamwi, Khawla. "Low Power Design Methodology and Photonics Networks on Chip for Multiprocessor System on Chip." Thesis, Brest, 2013. http://www.theses.fr/2013BRES0029.

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Les systèmes multiprocesseurs sur puce (MPSoC)s sont fortement émergent comme principaux composants dans les systèmes embarqués à hautes performances. La principale complexité dans la conception et l’implémentation des MPSoC est la communication entre les cœurs. Les réseaux sur puce (NoC) sont considérés comme la solution pour cet effet. ITRS prédit que des centaines de cœurs seront utilisées dans la génération future de système sur puce (SoC), ce qui va donc augmenter les coûts de l’évolutivité, de bande passante et de l’implémentation des réseaux sur puce (NoC)s. Ces problèmes sont présents dans diverses tendances technologiques dans le domaine des semiconducteurs et de la photonique. Cette thèse préconise l'utilisation de la synthèse NoC comme l'approche la plus appropriée pour exploiter ces tendances technologiques et rattraper les exigences des applications. A partir de plusieurs méthodologies de conception basées sur la technologie FPGA et des techniques d'estimation basse énergie (HLS) pour plusieurs IPs, nous proposons une implémentation ASIC basée sur la technologie 3D Tezzaron. Multi-FPGA technologie est utilisée pour valider la conception MPSoC avec 64 processeurs Butterfly NoC. La synthèse NoC est basée sur le regroupement de maîtres et d’esclaves générant des architectures asymétriques avec un soutien approprié pour les demandes très haut débit par optique NoC (ONoC), tandis que les demandes de bande passante inférieure sont traitées par électronique NoC. Une programmation linéaire est proposée comme une solution pour la synthèse NoC
Multiprocessor systems on chip (MPSoC)s are strongly emerging as main components in high performance embedded systems. Several challenges can be determined in MPSoC design like the challenge which comes from interconnect infrastructure. Network-on-Chip (NOC) with multiple constraints to be satisfied is a promising solution for these challenges. ITRS predicts that hundreds of cores will be used in future generation system on chip (SoC) and thus raises the issue of scalability, bandwidth and implementation costs for NoCs. These issues are raised within the various technological trends in semiconductors and photonics. This PhD thesis advocates the use of NoC synthesis as the most appropriate approach to exploit these technological trends catch up with the applications requirements. Starting with several design methodologies based on FPGA technology and low power estimation techniques (HLS) for several IPs, we propose an ASIC implementation based on 3D Tezzaron technology. Multi-FPGA technology is used to validate MPSoC design with up to 64 processors with Butterfly NoC. NoC synthesis is based on a clustering of masters and slaves generating asymmetric architectures with appropriate support for very high bandwidth requests through Optical NoC (ONoC) while lower bandwidth requests are processed by electronic NoC. A linear programming is proposed as a solution to the NoC synthesis
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Lodde, Mario. "Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors." Doctoral thesis, Universitat Politècnica de València, 2014. http://hdl.handle.net/10251/35325.

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La jerarquía de caches y la red en el chip (NoC) son dos componentes clave de los chip multiprocesadores (CMPs). La mayoría del trafico en la NoC se debe a mensajes que las caches envían según lo que establece el protocolo de coherencia. La cantidad de trafico, el porcentaje de mensajes cortos y largos y el patrón de trafico en general varían dependiendo de la geometría de las caches y del protocolo de coherencia. La arquitectura de la NoC y la jerarquía de caches están de hecho firmemente acopladas, y estos dos componentes deben ser diseñados y evaluados conjuntamente para estudiar como el variar uno afecta a las prestaciones del otro. Además, cada componente debe ajustarse a los requisitos y a las oportunidades del otro, y al revés. Normalmente diferentes clases de mensajes se envían por diferentes redes virtuales o por NoCs con diferente ancho de banda, separando mensajes largos y cortos. Sin embargo, otra clasificación de los mensajes se puede hacer dependiendo del tipo de información que proveen: algunos mensajes, como las peticiones de datos, necesitan campos para almacenar información (dirección del bloque, tipo de petición, etc.); otros, como los mensajes de reconocimiento (ACK), no proporcionan ninguna información excepto por el ID del nodo destino: solo proveen una información de tipo temporal, en el sentido que la recepción de un ACK indica que el nodo fuente ha recibido el mensaje al que está contestando con el ACK y completado todas las operaciones determinadas por el protocolo de coherencia. Esta segunda clase de mensaje no necesita de mucho ancho de banda: la latencia es mucho mas importante, dado que el nodo destino esta típicamente bloqueado esperando la recepción de ellos. En este trabajo de tesis se desarrolla una red dedicada para trasmitir la segunda clase de mensajes; la red es muy sencilla y rápida, y permite la entrega de los ACKs con una latencia de pocos ciclos de reloj. Reduciendo la latencia y el trafico en la NoC debido a los ACKs, es posible: -acelerar la fase de invalidación en fase de escritura en un sistema que usa un protocolo de coherencia basado en directorios -mejorar las prestaciones de un protocolo de coerencia basado en broadcast, hasta llegar a prestaciones comparables con las de un protocolo de directorios pero sin el coste de área debido a la necesidad de almacenar el directorio -implementar un mapeado dinámico de bloques a las caches de ultimo nivel de forma eficiente, con el objetivo de acercar cuanto al máximo los bloques a los cores que los utilizan El objetivo final es obtener un co-diseño de NoC y jerarquía de caches que minimice los problemas de escalabilidad de los protocolos de coherencia. Como gran objetivo final, se pretende la implementación de un CMP con ubicación dinámica de los recursos de cache y red, tal que estos recursos se puedan particionar de forma eficiente e independiente para asignar diferentes particiones a diferentes aplicaciones en un entorno virtualizado.
Lodde, M. (2014). Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/35325
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An, Xin. "High Level Design and Control of Adaptive Multiprocessor Systems-on-Chip." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00904884.

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La conception de systèmes embarqués modernes est de plus en plus complexe, car plus de fonctionnalités sont intégrées dans ces systèmes. En même temps, afin de répondre aux exigences de calcul tout en conservant une consommation d'énergie de faible niveau, MPSoCs sont apparus comme les principales solutions pour tels systèmes embarqués. En outre, les systèmes embarqués sont de plus en plus adaptatifs, comme l'adaptabilité peut apporter un certain nombre d'avantages, tels que la flexibilité du logiciel et l'efficacité énergétique. Cette thèse vise la conception sécuritaire de ces MPSoCs adaptatifs. Tout d'abord, chaque configuration de système doit être analysée en ce qui concerne ses propriétés fonctionnelles et non fonctionnelles. Nous présentons un cadre abstraite de conception et d'analyse qui permet des décisions d'implémentation rapide et rentable. Ce cadre est conçu comme un support de raisonnement intermédiaire pour les environnements de co-conception de logiciel / matériel au niveau de système. Il peut élaguer l'espace de conception à sa plus grande portée, et identifier les candidats de solutions de conception de manière rapide et efficace. Dans ce cadre, nous utilisons un codage basé sur l'horloge abstraite pour modéliser les comportements du système. Différents scénarios d'applications de mapping et de planification sur MPSoCs sont analysés via les traces d'horloge qui représentent les simulations du système. Les propriétés d'intérêt sont l'exactitude du comportement fonctionnel, la performance temporelle et la consommation d'énergie. Deuxièmement, la gestion de la reconfiguration de MPSoCs adaptatifs doit être abordée. Nous sommes particulièrement intéressés par les MPSoCs implémentés sur des architectures reconfigurables (ex. FPGAs) qui offrent une bonne flexibilité et une efficacité de calcul pour les MPSoCs adaptatifs. Nous proposons un cadre général de conception basé sur la technique de la synthèse de contrôleurs discrets (DCS) pour résoudre ce problème. L'avantage principal de cette technique est qu'elle permet une synthèse d'un contrôleur automatique selon une spécification des objectifs de contrôle. Dans ce cadre, le comportement de reconfiguration du système est modélisé en termes d'automates synchrones en parallèle. Le problème de calcul de la gestion reconfiguration selon de multiples objectifs concernant, par exemple, les usages des ressources, la performance et la consommation d'énergie, est codé comme un problème de DCS. Le langage de programmation BZR existant et l'outil Sigali sont employés pour effectuer DCS et générer un contrôleur qui satisfait aux exigences du système. Finalement, nous étudions deux façons différentes de combiner les deux cadres de conception proposées pour MPSoCs adaptatifs. Tout d'abord, ils sont combinés pour construire un flot de conception complet pour MPSoCs adaptatifs. Deuxièmement, ils sont combinés pour présenter la façon dont le manager run-time calculé par le second cadre peut être intégré dans le premier cadre afin de réaliser des simulations et des analyses combinées de MPSoCs adaptatifs.
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Khasawneh, Shadi Turki. "Low-power high-performance register file design for chip multiprocessors." Diss., Online access via UMI:, 2006.

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Esteve, García Albert. "Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors." Doctoral thesis, Universitat Politècnica de València, 2017. http://hdl.handle.net/10251/86136.

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Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by a single thread, i.e., private. Recent proposals leverage this observation to improve many aspects of chip multiprocessors, such as reducing coherence overhead or the access latency to distributed caches. The effectiveness of those proposals depends to a large extent on the amount of detected private data. However, the mechanisms proposed so far either do not consider either thread migration or the private use of data within different application phases, or do entail high overhead. As a result, a considerable amount of private data is not detected. In order to increase the detection of private data, this thesis proposes a TLB-based mechanism that is able to account for both thread migration and private application phases with low overhead. Classification status in the proposed TLB-based classification mechanisms is determined by the presence of the page translation stored in other core's TLBs. The classification schemes are analyzed in multilevel TLB hierarchies, for systems with both private and distributed shared last-level TLBs. This thesis introduces a page classification approach based on inspecting other core's TLBs upon every TLB miss. In particular, the proposed classification approach is based on exchange and count of tokens. Token counting on TLBs is a natural and efficient way for classifying memory pages. It does not require the use of complex and undesirable persistent requests or arbitration, since when two ormore TLBs race for accessing a page, tokens are appropriately distributed classifying the page as shared. However, TLB-based ability to classify private pages is strongly dependent on TLB size, as it relies on the presence of a page translation in the system TLBs. To overcome that, different TLB usage predictors (UP) have been proposed, which allow a page classification unaffected by TLB size. Specifically, this thesis introduces a predictor that obtains system-wide page usage information by either employing a shared last-level TLB structure (SUP) or cooperative TLBs working together (CUP).
La mayor parte de los datos referenciados por aplicaciones paralelas y secuenciales que se ejecutan enCMPs actuales son referenciadas por un único hilo, es decir, son privados. Recientemente, algunas propuestas aprovechan esta observación para mejorar muchos aspectos de los CMPs, como por ejemplo reducir el sobrecoste de la coherencia o la latencia de los accesos a cachés distribuidas. La efectividad de estas propuestas depende en gran medida de la cantidad de datos que son considerados privados. Sin embargo, los mecanismos propuestos hasta la fecha no consideran la migración de hilos de ejecución ni las fases de una aplicación. Por tanto, una cantidad considerable de datos privados no se detecta apropiadamente. Con el fin de aumentar la detección de datos privados, proponemos un mecanismo basado en las TLBs, capaz de reclasificar los datos a privado, y que detecta la migración de los hilos de ejecución sin añadir complejidad al sistema. Los mecanismos de clasificación en las TLBs se han analizado en estructuras de varios niveles, incluyendo TLBs privadas y con un último nivel de TLB compartido y distribuido. Esta tesis también presenta un mecanismo de clasificación de páginas basado en la inspección de las TLBs de otros núcleos tras cada fallo de TLB. De forma particular, el mecanismo propuesto se basa en el intercambio y el cuenteo de tokens (testigos). Contar tokens en las TLBs supone una forma natural y eficiente para la clasificación de páginas de memoria. Además, evita el uso de solicitudes persistentes o arbitraje alguno, ya que si dos o más TLBs compiten para acceder a una página, los tokens se distribuyen apropiadamente y la clasifican como compartida. Sin embargo, la habilidad de los mecanismos basados en TLB para clasificar páginas privadas depende del tamaño de las TLBs. La clasificación basada en las TLBs se basa en la presencia de una traducción en las TLBs del sistema. Para evitarlo, se han propuesto diversos predictores de uso en las TLBs (UP), los cuales permiten una clasificación independiente del tamaño de las TLBs. En concreto, esta tesis presenta un sistema mediante el que se obtiene información de uso de página a nivel de sistema con la ayuda de un nivel de TLB compartida (SUP) o mediante TLBs cooperando juntas (CUP).
La major part de les dades referenciades per aplicacions paral·leles i seqüencials que s'executen en CMPs actuals són referenciades per un sol fil, és a dir, són privades. Recentment, algunes propostes aprofiten aquesta observació per a millorar molts aspectes dels CMPs, com és reduir el sobrecost de la coherència o la latència d'accés a memòries cau distribuïdes. L'efectivitat d'aquestes propostes depen en gran mesura de la quantitat de dades detectades com a privades. No obstant això, els mecanismes proposats fins a la data no consideren la migració de fils d'execució ni les fases d'una aplicació. Per tant, una quantitat considerable de dades privades no es detecta apropiadament. A fi d'augmentar la detecció de dades privades, aquesta tesi proposa un mecanisme basat en les TLBs, capaç de reclassificar les dades com a privades, i que detecta la migració dels fils d'execució sense afegir complexitat al sistema. Els mecanismes de classificació en les TLBs s'han analitzat en estructures de diversos nivells, incloent-hi sistemes amb TLBs d'últimnivell compartides i distribuïdes. Aquesta tesi presenta un mecanisme de classificació de pàgines basat en inspeccionar les TLBs d'altres nuclis després de cada fallada de TLB. Concretament, el mecanisme proposat es basa en l'intercanvi i el compte de tokens. Comptar tokens en les TLBs suposa una forma natural i eficient per a la classificació de pàgines de memòria. A més, evita l'ús de sol·licituds persistents o arbitratge, ja que si dues o més TLBs competeixen per a accedir a una pàgina, els tokens es distribueixen apropiadament i la classifiquen com a compartida. No obstant això, l'habilitat dels mecanismes basats en TLB per a classificar pàgines privades depenen de la grandària de les TLBs. La classificació basada en les TLBs resta en la presència d'una traducció en les TLBs del sistema. Per a evitar-ho, s'han proposat diversos predictors d'ús en les TLBs (UP), els quals permeten una classificació independent de la grandària de les TLBs. Específicament, aquesta tesi introdueix un predictor que obté informació d'ús de la pàgina a escala de sistema mitjançant un nivell de TLB compartida (SUP) or mitjançant TLBs cooperant juntes (CUP).
Esteve García, A. (2017). Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/86136
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Hegde, Sridhar. "Design enhancement and applications development for a hybrid, heterogeneous single-chip multiprocessor archtecture." Lexington, Ky. : [University of Kentucky Libraries], 2004. http://lib.uky.edu/ETD/ukyelen2004t00224/MastersThesis.pdf.

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Thesis (M.S.) --University of Kentucky, 2004.
Title from document title page (viewed on August 11, 2005) Document formatted into pages; contains: ix, 358 p. : ill. Includes abstract and vita. Includes bibliographical references (p. 354-357).
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Books on the topic "Chip Multiprocessor Designs"

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Gerd, Ascheid, Leupers Rainer, and SpringerLink (Online service), eds. Multiprocessor Systems on Chip: Design Space Exploration. New York, NY: Springer Science+Business Media, LLC, 2011.

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A, Jerraya Ahmed, and Wolf Wayne Hendrix, eds. Multiprocessor systems on chips. Amsterdam: Morgan Kaufmann, 2005.

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Hübner, Michael. Multiprocessor system-on-chip: Hardware design and tool integration. New York: Springer, 2011.

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Popovici, Katalin, Frédéric Rousseau, Ahmed A. Jerraya, and Marilyn Wolf. Embedded Software Design and Programming of Multiprocessor System-on-Chip. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-5567-8.

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Inc, ebrary, ed. System-level modelling and design space exploration for multiprocessor embedded system-on-chip architectures. Amsterdam: Amsterdam University Press, 2006.

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Multi-objective design space exploration of multiporcessor SoC architectures: The MULTICUBE approach. New York: Springer, 2011.

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Popovici, Katalin. Embedded software design and programming of multiprocessor system-on-chip: Simulink and SystemC case studies. New York: Springer, 2010.

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Ascheid, Gerd, Rainer Leupers, and Torsten Kempf. Multiprocessor Systems on Chip: Design Space Exploration. Springer New York, 2014.

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Multiprocessor systems-on-chips. San Francisco, CA: Morgan Kaufmann, 2004.

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Wolf, Wayne, and Ahmed Jerraya. Multiprocessor Systems-On-Chips. Elsevier Science & Technology Books, 2004.

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Book chapters on the topic "Chip Multiprocessor Designs"

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Reis, Ricardo. "Design Tools and Methods for Chip Physical Design." In Multiprocessor System-on-Chip, 155–66. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6460-1_7.

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Kempf, Torsten, Gerd Ascheid, and Rainer Leupers. "Principles of Design Space Exploration." In Multiprocessor Systems on Chip, 23–47. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8153-0_3.

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Grammatikakis, Miltos D., George Kornaros, and Marcello Coppola. "Power‐Aware Multicore SoC and NoC Design." In Multiprocessor System-on-Chip, 167–93. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6460-1_8.

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Pham, Dac, Jim Holt, and Sanjay Deshpande. "Embedded Multicore Systems: Design Challenges and Opportunities." In Multiprocessor System-on-Chip, 197–222. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6460-1_9.

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Göhringer, Diana, Michael Hübner, and Jürgen Becker. "Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support." In Multiprocessor System-on-Chip, 127–51. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6460-1_6.

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Javaid, Haris, and Sri Parameswaran. "Design Space Exploration of Pipelined MPSoCs." In Pipelined Multiprocessor System-on-Chip for Multimedia, 85–100. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-01113-4_5.

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Li, Cheng, Paul V. Gratz, and Samuel Palermo. "Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors." In More than Moore Technologies for Next Generation Computer Design, 155–86. New York, NY: Springer New York, 2015. http://dx.doi.org/10.1007/978-1-4939-2163-8_7.

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Popovici, Katalin, Frédéric Rousseau, Ahmed A. Jerraya, and Marilyn Wolf. "System Architecture Design." In Embedded Software Design and Programming of Multiprocessor System-on-Chip, 93–121. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-5567-8_3.

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Popovici, Katalin, Frédéric Rousseau, Ahmed A. Jerraya, and Marilyn Wolf. "Virtual Architecture Design." In Embedded Software Design and Programming of Multiprocessor System-on-Chip, 123–50. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-5567-8_4.

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Popovici, Katalin, Frédéric Rousseau, Ahmed A. Jerraya, and Marilyn Wolf. "Virtual Prototype Design." In Embedded Software Design and Programming of Multiprocessor System-on-Chip, 183–206. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-5567-8_6.

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Conference papers on the topic "Chip Multiprocessor Designs"

1

Yoo, Junhee, Sungjoo Yoo, and Kiyoung Choi. "Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency." In the 46th Annual Design Automation Conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1629911.1630118.

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Raksapatcharawong, Mongkol, and Timothy Mark Pinkston. "A System Demonstration of Progressive Deadlock Recovery Routing based on Optoelectronic/VLSI Chips." In Optics in Computing. Washington, D.C.: Optica Publishing Group, 1997. http://dx.doi.org/10.1364/oc.1997.othd.18.

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We present a system demonstration of a sequential deadlock recovery-based scheme [1] employing a circulating token to guarantee mutual exclusive access to deadlock buffers. This system allows us to evaluate the design and implementation of a multiprocessor network router using free-space optical interconnects. The system is designed based on our CMOS-SEED chip—OMNI [2] and GaAs-based chip—WARRP [3]. These two chips are employed to implement asynchronous optical token-based resource arbitration and deadlock recovery via channel preemption, respectively. With an external node controller, this experimental system is capable of demonstrating a high-performance bandwidth-efficient deadlock recovery-based multiprocessor network router.
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Schoeberl, Martin. "Time-predictable chip-multiprocessor design." In 2010 44th Asilomar Conference on Signals, Systems and Computers. IEEE, 2010. http://dx.doi.org/10.1109/acssc.2010.5757923.

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Pinkston, Timothy Mark, Mongkol Raksapatcharawong, and Yungho Choi. "Smart-Pixel Implementation of Network Router Deadlock Handling Mechanisms." In Optics in Computing. Washington, D.C.: Optica Publishing Group, 1997. http://dx.doi.org/10.1364/oc.1997.othb.2.

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We present WARRP: the core deadlock handling circuitry for a fully adaptive, deadlock recovery-based multiprocessor network router. This chip primarily demonstrates the integration of complex deadlock recovery circuitry and free-space optical channels on a monolithic GaAs-based chip. We report the design and implementation of the first generation, bit-serial, torus-connected chip employing 1400 transistors and 6 LED/photodetector pairs.
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Tmimi, M., S. D'Amico, J.-M. Duchamp, Ph Ferrari, and Ph Galy. "10Gbps Length adaptive on-chip RF serial link for Network on Chips and Multiprocessor chips applications." In 2019 International Conference on IC Design and Technology (ICICDT). IEEE, 2019. http://dx.doi.org/10.1109/icicdt.2019.8790923.

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Otoom, Mwaffaq, and JoAnn M. Paul. "Chip-level programming of heterogeneous multiprocessors." In 2015 10th International Design & Test Symposium (IDT). IEEE, 2015. http://dx.doi.org/10.1109/idt.2015.7396730.

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Njoroge, Njuguna, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, and Kunle Olukotun. "ATLAS: A Chip-Multiprocessor with Transactional Memory Support." In Design, Automation & Test in Europe Conference. IEEE, 2007. http://dx.doi.org/10.1109/date.2007.364558.

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Zhang, Lide, Lan S. Bai, Robert P. Dick, Li Shang, and Russ Joseph. "Process variation characterization of chip-level multiprocessors." In the 46th Annual Design Automation Conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1629911.1630092.

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Bobda, Chritophe, Thomas Haller, Felix Muehlbauer, Dennis Rech, and Simon Jung. "Design of adaptive multiprocessor on chip systems." In the 20th annual conference. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1284480.1284531.

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Loukil, Kais, Nader Ben Amor, Yassine Aoudni, and Mohamed Abid. "Design of Real Time Multiprocessor System on Chip." In 2007 2nd International Design and Test Workshop. IEEE, 2007. http://dx.doi.org/10.1109/idt.2007.4437444.

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