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Journal articles on the topic 'Chip Multiprocessor Designs'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Balston, Kyle, Mehdi Karimibiuki, Alan J. Hu, Andre Ivanov, and Steven J. E. Wilton. "Post-silicon code coverage for multiprocessor system-on-chip designs." IEEE Transactions on Computers 62, no. 2 (February 2013): 242–46. http://dx.doi.org/10.1109/tc.2012.163.

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2

Kao, Chi-Chou, and Yi-Ciang Lin. "Designs of Low Power Snoop for Multiprocessor System on Chip." Journal of Signal Processing Systems 88, no. 1 (April 4, 2016): 83–89. http://dx.doi.org/10.1007/s11265-016-1135-4.

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3

Madl, G., S. Pasricha, N. Dutt, and S. Abdelwahed. "Cross-Abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs." IEEE Transactions on Industrial Informatics 5, no. 3 (August 2009): 241–56. http://dx.doi.org/10.1109/tii.2009.2026896.

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4

Li, Xinyu, and Omar Hammami. "An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography." International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/631490.

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Embedded system design is increasingly based on single chip multiprocessors because of the high performance and flexibility requirements. Embedded multiprocessors on FPGA provide the additional flexibility by allowing customization through addition of hardware accelerators on FPGA when parallel software implementation does not provide the expected performance. And the overall multiprocessor architecture is still kept for additional applications. This provides a transition to software only parallel implementation while avoiding pure hardware implementation. An automatic design flow is proposed well suited for data flow signal processing exhibiting both pipelining and data parallel mode of execution. Fork-Join model-based software parallelization is explored to find out the best parallelization configuration. C-based synthesis coprocessor is added to improve performance with more hardware resource usage. The Triple Data Encryption Standard (TDES) cryptographic algorithm on a 48-PE single-chip distributed memory multiprocessor is selected as an application example of the flow.

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5

Tafesse, Bisrat, and Venkatesan Muthukumar. "Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration." VLSI Design 2013 (July 11, 2013): 1–16. http://dx.doi.org/10.1155/2013/936181.

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Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.

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Tsai, Wen-Chung, Ying-Cherng Lan, Yu-Hen Hu, and Sao-Jie Chen. "Networks on Chips: Structure and Design Methodologies." Journal of Electrical and Computer Engineering 2012 (2012): 1–15. http://dx.doi.org/10.1155/2012/509465.

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for on-chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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7

Akturk, Ismail, and Ozcan Ozturk. "Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design." Journal of Electronic Testing 29, no. 2 (April 2013): 177–84. http://dx.doi.org/10.1007/s10836-013-5373-0.

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8

Xin, Yin, and Guozhi Song. "Design of a Novel Wireless NoC Architecture for Chip Multiprocessor." Journal of Physics: Conference Series 2331, no. 1 (August 1, 2022): 012012. http://dx.doi.org/10.1088/1742-6596/2331/1/012012.

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Abstract The Network on chip is a new communication method of System on Chip. It is the main part of multi-core technology. A large number of embedded cores can be combined on a single chip. Due to the multi-hop characteristics of communication, there are some problems in the design of traditional NoC, such as high latency and power consumption. Thus, to handle the communication problem of long-distance transmission of traditional NoC, wireless Networks on Chip (WiNoC) has been proposed. Using WiNoC to design the multi-core System on Chip can significantly reduce the latency and energy consumption of the network. The advantage of using wireless network on chip is to replace the multi-hop path of traditional network on chip with wireless single hop link. However, due to the limited space on the chip and the cost, it is very important to determine the optimal number and correct location of wireless hubs. In this paper, we propose a new method to obtain the optimum configuration of a WiNoC by using the Co-evolutionary Algorithms (CA) and a wireless NoC architecture based on mesh. This work examines the effect of VC and sub-net size on WiNoC performance efficiency and energy under different packet injection rate (PIR) and the number of cores (64, 144 and 256). The simulation experiment of the algorithm proposed in the whole architecture has been implemented on the Noxim platform.

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9

Wolf, W., A. A. Jerraya, and G. Martin. "Multiprocessor System-on-Chip (MPSoC) Technology." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 10 (October 2008): 1701–13. http://dx.doi.org/10.1109/tcad.2008.923415.

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10

Hammond, Lance, Mark Willey, and Kunle Olukotun. "Data speculation support for a chip multiprocessor." ACM SIGPLAN Notices 33, no. 11 (November 1998): 58–69. http://dx.doi.org/10.1145/291006.291020.

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11

Olukotun, Kunle, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang. "The case for a single-chip multiprocessor." ACM SIGPLAN Notices 31, no. 9 (September 1996): 2–11. http://dx.doi.org/10.1145/248209.237140.

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12

Genbrugge, Davy, and Lieven Eeckhout. "Chip Multiprocessor Design Space Exploration through Statistical Simulation." IEEE Transactions on Computers 58, no. 12 (December 2009): 1668–81. http://dx.doi.org/10.1109/tc.2009.77.

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13

Mane, V. V., and U. L. Bombale. "Design of Real Time Multiprocessor System on Chip." International Journal of Computer Applications 1, no. 24 (February 25, 2010): 36–38. http://dx.doi.org/10.5120/562-739.

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14

Ozturk, Ozcan, Mahmut Kandemir, Mary J. Irwin, and Sri H. K. Narayanan. "Compiler directed network-on-chip reliability enhancement for chip multiprocessors." ACM SIGPLAN Notices 45, no. 4 (April 13, 2010): 85–94. http://dx.doi.org/10.1145/1755951.1755902.

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15

DeVuyst, Matthew, Ashish Venkat, and Dean M. Tullsen. "Execution migration in a heterogeneous-ISA chip multiprocessor." ACM SIGPLAN Notices 47, no. 4 (June 2012): 261–72. http://dx.doi.org/10.1145/2248487.2151004.

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16

Bhattacharjee, Abhishek, and Margaret Martonosi. "Inter-core cooperative TLB for chip multiprocessors." ACM SIGPLAN Notices 45, no. 3 (March 5, 2010): 359–70. http://dx.doi.org/10.1145/1735971.1736060.

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17

Paul, J. M., D. E. Thomas, and A. Bobrek. "Scenario-oriented design for single-chip heterogeneous multiprocessors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 8 (August 2006): 868–80. http://dx.doi.org/10.1109/tvlsi.2006.878474.

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18

Nagalaxmi, T., Dr E. Sreenivasa Rao, and Dr P. Chandrasekhar. "Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC." International Journal of Communication Networks and Information Security (IJCNIS) 14, no. 1s (January 8, 2023): 37–53. http://dx.doi.org/10.17762/ijcnis.v14i1s.5590.

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The Network on Chip is appropriate where System-on-Chip technology is scalable and adaptable. The Network on Chip is a new communication architecture with a number of benefits, including scalability, flexibility, and reusability, for applications built on Multiprocessor System on a Chip (MPSoC). However, the design of efficient NoC fabric with high performance is critically complex because of its architectural parameters. Identifying a suitable scheduling algorithm to resolve arbitration among ports to obtain high-speed data transfer in the router is one of the most significant phases while designing a Network on chip based Multiprocessor System on a Chip. Low latency, throughput, space utilization, energy consumption, and reliability for Network on chip fabric are all determined by the router. The performance of the NoC system is hampered by the deadlock issues that plague conventional routing algorithms. This work develops a novel routing algorithm to address the deadlock problem. In this paper, a deterministic shortest path deadlock-free routing method is developed based on the analysis of the Turn Model. In the 2D-mesh structure, the algorithm uses separate routing methods for the odd and even columns. This minimizes the number of paths for a single channel, congestion, and latency. Two test scenarios—one with and one without a load test—were used to evaluate the proposed model. For a zero-load network, three clock cycles are utilized to transfer the packets. For the load network, five clocks are utilized to transfer the packets. The latency is measured for both cases without load and with load test and the corresponding latency is 3ns and 7ns respectively.The proposed method has an 18.57Mbps throughput. The area and power utilization for the proposed method are 69% (IO utilization) and 0.128W respectively. In order to validate the proposed method, the latency is compared with existing work and 50% latency is reduced both with and without congestion load.

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19

Changyun Zhu, Zhenyu Gu, Li Shang, R. P. Dick, and R. Joseph. "Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 8 (August 2008): 1479–92. http://dx.doi.org/10.1109/tcad.2008.925793.

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20

Banaiyanmofrad, Abbas, Gustavo Girão, and Nikil Dutt. "NoC-based fault-tolerant cache design in chip multiprocessors." ACM Transactions on Embedded Computing Systems 13, no. 3s (March 2014): 1–26. http://dx.doi.org/10.1145/2567939.

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21

Nemeth, Jason, Rui Min, Wen-Ben Jone, and Yiming Hu. "Location Cache Design and Performance Analysis for Chip Multiprocessors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 1 (January 2011): 104–17. http://dx.doi.org/10.1109/tvlsi.2009.2028429.

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22

GONG, Rui, Kui DAI, and Zhi-Ying WANG. "Chip Multiprocessor Execution Model for Soft Error Tolerance." Chinese Journal of Computers 31, no. 11 (October 16, 2009): 2047–59. http://dx.doi.org/10.3724/sp.j.1016.2008.02047.

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23

Pham, Phi-Hung, Junyoung Song, Jongsun Park, and Chulwoo Kim. "Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 1 (January 2013): 173–77. http://dx.doi.org/10.1109/tvlsi.2011.2181545.

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24

Ye, Yaoyao, Jiang Xu, Baihan Huang, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu, and Zhe Wang. "3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 4 (April 2013): 584–96. http://dx.doi.org/10.1109/tcad.2012.2228739.

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25

Chen, Guangyu, Feihui Li, and Mahmut Kandemir. "Compiler-directed application mapping for NoC based chip multiprocessors." ACM SIGPLAN Notices 42, no. 7 (July 13, 2007): 155–57. http://dx.doi.org/10.1145/1273444.1254796.

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26

Son, Seung Woo, Mahmut Kandemir, Mustafa Karakoy, and Dhruva Chakrabarti. "A compiler-directed data prefetching scheme for chip multiprocessors." ACM SIGPLAN Notices 44, no. 4 (February 14, 2009): 209–18. http://dx.doi.org/10.1145/1594835.1504208.

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27

Nikitin, Nikita, Javier de San Pedro, and Jordi Cortadella. "Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 10 (October 2013): 1569–82. http://dx.doi.org/10.1109/tcad.2013.2272539.

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28

El-Kustaban, Amin, and Abdullah Qahtan. "Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System." Journal of Science and Technology 20, no. 2 (December 11, 2015): 22–34. http://dx.doi.org/10.20428/jst.v20i2.937.

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Computer designers utilize the recent huge advances in Very Large Scale Integration (VLSI) to get Chip Multiprocessor (CMP) by placing several processors on the same chip die. The CMP is the dominant architecture to improve the performance of the current computing systems. However, accessing a shared data by several processors is a primary challenge in CMP. The data consistency must be reached among all memory hierarchies to ensure correct behavior and higher performance. This paper, proposed a CMP with an efficient multilevel cache system, which enhances miss rate and latency (penalty) by designing and implementation of different write policies with two levels of cache. The proposed system is implemented and tested using Hardware Description Language (VHDL) on Altera’s FPGA chip. The results show that a combination of write-through without buffer for the first level and write-back for the second level offers a clear improvement on the multilevel cache system performance.

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29

S, Kendaganna Swamy, Anand Jatti, and Uma B. V. "Reconfigurable High Performance Secured NoC Design Using Hierarchical Agent-based Monitoring System." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (December 1, 2018): 4164. http://dx.doi.org/10.11591/ijece.v8i6.pp4164-4174.

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With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on chip architecture with hierarchical agent based monitoring system for enhancing the performance of network based multiprocessor system on chip against faulty links and nodes. These distributed agents provide healthy status and congestion information of the network. This status information is used for further packet routing in the network with the help of XY routing algorithm. The functionality of Agent is enhanced not only to work as information provider but also to take decision for packet to either pass or stop to the processing element by setting the firewall in order to provide security. Proposed design provides a better performance and area optimization by avoiding deadlock and live lock as compared to existing approaches over network design.

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30

Valls, Joan J., Alberto Ros, Julio Sahuquillo, and Maria E. Gomez. "PS-Cache: an energy-efficient cache design for chip multiprocessors." Journal of Supercomputing 71, no. 1 (September 13, 2014): 67–86. http://dx.doi.org/10.1007/s11227-014-1288-5.

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31

Ben Mouhoub, Riad, and Omar Hammami. "MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution." EURASIP Journal on Embedded Systems 2006, no. 1 (2006): 054074. http://dx.doi.org/10.1186/1687-3963-2006-054074.

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32

Chen, Xianmin, and Niraj K. Jha. "Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles." ACM Journal on Emerging Technologies in Computing Systems 11, no. 1 (October 6, 2014): 1–16. http://dx.doi.org/10.1145/2629576.

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33

Ben Mouhoub, Riad, and Omar Hammami. "MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution." EURASIP Journal on Embedded Systems 2006 (2006): 1–14. http://dx.doi.org/10.1155/es/2006/54074.

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34

Awadalla, Medhat, and Ahmed M. Sadek. "An Efficient Cache Organization for On-Chip Multiprocessor Networks." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 3 (June 1, 2015): 503. http://dx.doi.org/10.11591/ijece.v5i3.pp503-517.

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To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes another challenging issue. In most System-on-Chip applications, a shared bus interconnection which needs an arbitration logic to serialize several bus access requests, is adopted to communicate with each integrated processing unit because of its low-cost and simple control characteristics. This paper focuses on the interconnection design issues of area, power and performance of chip multi-processors with shared cache memory. It shows that having shared cache memory contributes to the performance improvement, however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. New interconnection mechanisms are needed to address these issues. This paper proposes an architectural paradigm in an attempt to gain the advantages of having shared cache with the avoidance of penalty imposed by the crossbar interconnect. The proposed architecture achieves smaller area occupation allowing more space to add additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper presents a modified cache coherence algorithm called Tuned-MESI. It is based on the typical MESI cache coherence algorithm however it is tuned and tailored for the suggested architecture. The achieved results of the conducted simulated experiments show that the developed architecture produces less broadcast operations compared to the typical algorithm.

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35

Tutsch, Dietmar, and Daniel Lüdtke. "Chip Multiprocessor Traffic Models Providing Consistent Multicast and Spatial Distributions." SIMULATION 84, no. 2-3 (February 2008): 61–73. http://dx.doi.org/10.1177/0037549708091638.

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36

Cannella, Emanuele, Onur Derin, Paolo Meloni, Giuseppe Tuveri, and Todor Stefanov. "Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks." VLSI Design 2012 (March 4, 2012): 1–17. http://dx.doi.org/10.1155/2012/987209.

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System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we propose an approach to enable the run-time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter-tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes and have been implemented on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run-time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real-life case study.

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37

Foroozannejad, Mohammad H., Matin Hashemi, Alireza Mahini, Bevan M. Baas, and Soheil Ghiasi. "Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 5 (May 2014): 752–62. http://dx.doi.org/10.1109/tcad.2014.2299958.

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38

Kavitha, Thandapani, Gopalswamy Maheswaran, Joly Maheswaran, and Chandramohan K. Pappa. "Optical network on chip: design of wavelength routed optical ring architecture." Bulletin of Electrical Engineering and Informatics 12, no. 1 (February 1, 2023): 167–75. http://dx.doi.org/10.11591/eei.v12i1.4294.

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Network on chip (NoC) technology has now achieved a mature stage of development as a result of their use as a key component in many successful commercial devices. As multiprocessors continue to scale, these ship based electronic networks are more challenging to meet their power budget communication requirements. Innovative technology is emerging with the aim of offering shorter latencies and greater bandwidth with lower power consumption. Ring topology provides superior results among the all wavelength routed topologies in the chip optical network. In this paper, we proposed an optical ring network-on-chip (ORNoC) architecture which is contention free. Communication matrix is used to assign a single waveguide/wavelength pair to implement simultaneous communications. The design constraints for the proposed architecture will be wavelength reused on a single waveguide for multiple communications. We imply automatic wavelength/waveguide assignment for effective design and will prove that the proposed architecture can connect more number of nodes and less wavelengths per waveguide.

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39

S, Kendaganna Swamy, Anand Jatti, and Uma B. V. "Design and implementation of secured agent based NoC using shortest path routing algorithm." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 2 (April 1, 2019): 950. http://dx.doi.org/10.11591/ijece.v9i2.pp950-959.

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Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.

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40

Göhringer, Diana, Thomas Perschke, Michael Hübner, and Jürgen Becker. "A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip." International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/395018.

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Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.

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41

DRACH, N., A. GEFFLAUT, P. JOUBERT, and A. SEZNEC. "ABOUT CACHE ASSOCIATIVITY IN LOW-COST SHARED MEMORY MULTI-MICROPROCESSORS." Parallel Processing Letters 05, no. 03 (September 1995): 475–87. http://dx.doi.org/10.1142/s0129626495000436.

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Sizes of on-chip caches on current commercial microprocessors range from 16 Kbytes to 36 Kbytes. These microprocessors can be directly used in the design of a low cost single-bus shared memory multiprocessors without using any second-level cache. In this paper, we explore the viability of such a multi-microprocessor. Simulations results clearly establish that performance of such a system will be quite poor if on-chip caches are direct-mapped. On the other hand, when the on-chip caches are partially associative, the achieved level of performance is quite promising. In particular, two recently proposed innovative cache structures, the skewed-associative cache organization and the semi-unified cache organization are shown to work fine.

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42

Meyer, B. H., J. J. Pieper, J. M. Paul, J. E. Nelson, S. M. Pieper, and A. G. Rowe. "Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors." IEEE Transactions on Computers 54, no. 6 (June 2005): 684–97. http://dx.doi.org/10.1109/tc.2005.103.

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43

Zhang, Ying, Samuel Irving, Lu Peng, Xin Fu, David Koppelman, Weihua Zhang, and Jesse Ardonne. "Design space exploration for device and architectural heterogeneity in chip-multiprocessors." Microprocessors and Microsystems 40 (February 2016): 88–101. http://dx.doi.org/10.1016/j.micpro.2015.07.012.

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44

Li, Feihui, Chrysostomos Nicopoulos, Thomas Richardson, Yuan Xie, Vijaykrishnan Narayanan, and Mahmut Kandemir. "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory." ACM SIGARCH Computer Architecture News 34, no. 2 (May 2006): 130–41. http://dx.doi.org/10.1145/1150019.1136497.

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Roca, Antoni, Carles Hernandez, Mario Lodde, and José Flich. "Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems." Computers & Electrical Engineering 45 (July 2015): 374–85. http://dx.doi.org/10.1016/j.compeleceng.2015.04.020.

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Määttä, Sanna, Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Manfred Glesner, Jari Nurmi, and Fernando Moraes. "Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms." International Journal of Embedded and Real-Time Communication Systems 1, no. 1 (January 2010): 86–101. http://dx.doi.org/10.4018/jertcs.2010103005.

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Abstract:

Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

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Li, Shuo, Gao Chao Xu, Yu Shuang Dong, and Feng Wu. "The Review of Cache Partitioning in Multi-Core Processor." Key Engineering Materials 439-440 (June 2010): 1223–29. http://dx.doi.org/10.4028/www.scientific.net/kem.439-440.1223.

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With the development of microelectronics technology, Chip Multi-Processor (CMP) or multi-core design has become a mainstream choice for major microprocessor vendors. But in a chip-multiprocessor with a shared cache structure , the competing accesses from different applications degrade the system performance , resulting in non-optimal performance and non-predicting executing time. Cache partitioning techniques can exclusively partition the shared cache among multiple competing applications. In this paper, we first introduce the problems caused by Cache pollution in multicore processor structure; then present the different methods of Cache partitioning in multicore processor structure¬ －－categorizing them based on the different metrics. And finally, we discuss some possible directions for future research in the area.

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Mohammad, Khader, Ahsan Kabeer, and Tarek Taha. "On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding." VLSI Design 2014 (May 6, 2014): 1–14. http://dx.doi.org/10.1155/2014/801241.

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In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high volume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount of data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory bus. This paper addresses the problem of the high-power consumption of the on-chip data buses, exploring a framework for memory data bus power consumption minimization approach. A comprehensive analysis of the existing bus power minimization approaches is provided based on the performance, power, and area overhead consideration. A novel approaches for reducing the power consumption for the on-chip bus is introduced. In particular, a serialization-widening (SW) of data bus with frequent value encoding (FVE), called the SWE approach, is proposed as the best power savings approach for the on-chip cache data bus. The experimental results show that the SWE approach with FVE can achieve approximately 54% power savings over the conventional bus for multicore applications using a 64-bit wide data bus in 45 nm technology.

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Mittal, Shaily, and Nitin. "Memory Map: A Multiprocessor Cache Simulator." Journal of Electrical and Computer Engineering 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/365091.

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Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an optimal manner. Memory map is a multiprocessor simulator to choreograph data flow in individual caches of multiple processors and shared memory systems. This simulator allows user to specify cache reconfigurations and number of processors within the application program and evaluates cache miss and hit rate for each configuration phase taking into account reconfiguration costs. The code is open source and in java.

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Horak, Michael N., Steven M. Nowick, Matthew Carlberg, and Uzi Vishkin. "A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 4 (April 2011): 494–507. http://dx.doi.org/10.1109/tcad.2011.2114970.

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