Relevant bibliographies by topics / Chip-package

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Chip-package'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 February 2022

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Journal articles on the topic "Chip-package"

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Baba, Shinji, Naoto Ueda, and Osamu Nakagawa. "Chip Scale Package." Journal of SHM 11, no. 5 (1995): 15–19. http://dx.doi.org/10.5104/jiep1993.11.5_15.

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Wakabayashi, Shinichi, and Tetsuya Koyama. "Chip Size Package." Journal of SHM 11, no. 5 (1995): 3–8. http://dx.doi.org/10.5104/jiep1993.11.5_3.

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Ghaffarian, Reza. "Chip scale package issues." Microelectronics Reliability 40, no. 7 (2000): 1157–61. http://dx.doi.org/10.1016/s0026-2714(00)00041-x.

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Yerman, AlexanderJ. "4538170 Power chip package." Microelectronics Reliability 26, no. 3 (1986): 594. http://dx.doi.org/10.1016/0026-2714(86)90686-4.

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Jeong, Young-Hyun, Kang-Hoon Cho, You-In Choung, and Sang-Chul Park. "Scheduling Methodology for MCP(Multi-chip Package) with Layer Sequence Constraint in Semiconductor Package." Journal of the Korea Society for Simulation 26, no. 1 (2017): 69–75. http://dx.doi.org/10.9709/jkss.2017.26.1.069.

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Yasunaga, M., S. Baba, M. Matsuo, H. Matsushima, S. Nakao, and T. Tachikawa. "Chip scale package: "a lightly dressed LSI chip"." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A 18, no. 3 (1995): 451–57. http://dx.doi.org/10.1109/95.465135.

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Iwasaki, Hiroshi. "CSTP(Chip Scale Thin Package)." Journal of SHM 11, no. 5 (1995): 26–31. http://dx.doi.org/10.5104/jiep1993.11.5_26.

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van Driel, W. D., D. G. Yang, and G. Q. Zhang. "On chip–package stress interaction." Microelectronics Reliability 48, no. 8-9 (2008): 1268–72. http://dx.doi.org/10.1016/j.microrel.2008.06.039.

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Koshido, Yoshihiro. "Chip-size package piezoelectric component." Journal of the Acoustical Society of America 120, no. 5 (2006): 2403. http://dx.doi.org/10.1121/1.2395113.

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TAKAI, Tadashi. "Trend of BGACSPKGD. Flip-Chip Chip Size/Scale Package." Journal of Japan Institute of Electronics Packaging 1, no. 5 (1998): 398–400. http://dx.doi.org/10.5104/jiep.1.398.

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Dissertations / Theses on the topic "Chip-package"

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Mehrotra, Gaurav. "Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22594.

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Tang, Zhenming. "Interfacial reliability of Pb-free flip-chip BGA package." Diss., Online access via UMI:, 2008.

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Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008.<br>Includes bibliographical references.
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Koh, Sau W. "Fatigue modeling of nano-structured chip-to-package interconnections." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28263.

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Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Rao R. Tummala; Committee Co-Chair: Ashok Saxena; Committee Member: Karl Jacob; Committee Member: Suresh Sitaraman; Committee Member: Thomas H. Sanders, Jr.
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Michielsen, Wim. "VCOs for future generations of wireless radio transceivers." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-492.

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Winter, Matthias [Verfasser]. "Integration kapazitiver Silizium-Mikrofone in ein Chip Scale Package / Matthias Winter." Aachen : Shaker, 2011. http://d-nb.info/1071529609/34.

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Shen, Meigen. "Concurrent chip and package design for radio and mixed-signal systems." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-476.

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Paydenkar, Chetan S. "Flip chip assembly process development, process characterization, and reliability assessment of polymer stud grid array-chip scaled package." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/19141.

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Neysmith, Jordan M. "A modular, direct chip attach, wafer level MEMS package : architecture and processing." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/17559.

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Yi, Ming. "Transient simulation for multiscale chip-package structures using the Laguerre-FDTD scheme." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53856.

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The high-density integrated circuit (IC) gives rise to geometrically complex multiscale chip-package structures whose electromagnetic performance is difficult to predict. This motivates this dissertation to work on an efficient full-wave transient solver that is capable of capturing all the electromagnetic behaviors of such structures with high accuracy and reduced computational complexity compared to the existing methods. In this work, the unconditionally stable Laguerre-FDTD method is adopted as the core algorithm for the transient full-wave solver. As part of this research, skin-effect is rigorously incorporated into the solver which avoids dense meshing inside conductor structures and significantly increases computational efficiency. Moreover, as an alternative to typical planar interconnects for next generation high-speed ICs, substrate integrated waveguide, is investigated. Conductor surface roughness is efficiently modeled to accurately capture its high-frequency loss behavior. To further improve the computational performance of chip-package co-simulation, a novel transient non-conformal domain decomposition method has been proposed. Large-scale chip-package structure can be efficiently simulated by decomposing the computational domain into subdomains with independent meshing strategy. Numerical results demonstrate the capability, accuracy and efficiency of the proposed methods.
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Duo, Xinzhong. "System-on-package solutions for multi-band RF front end." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-482.

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Books on the topic "Chip-package"

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Estonia) Baltic Electronics Conference (7th 2000 Tallinn. Baltic Electronics Conference: Electronic materials and package technologies, semiconductor devices and simulation, integrated electronics and chip design, instrumentation and system design, test, diagnostics, and fault tolerance, telecommunication and optical transmission, biomedical electronics, power electronics, education and training : BEC 2000 : October 8-11, 2000, Tallinn, Estonia : conference proceedings. The University, 2000.

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Lee, Ricky S. W., Ricky S. Lee, and John H. Lau. Chip Scale Package: Design, Materials, Process, Reliability, and Applications. McGraw-Hill Professional, 1999.

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Lee, Ricky S. W., Ricky S. Lee, and John H. Lau. Chip Scale Package: Design, Materials, Process, Reliability, and Applications. McGraw-Hill Professional, 1999.

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McAlpine, Kenneth B. The Ultimate Soundtracker? Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780190496098.003.0006.

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In the early days of home computing, writing music was as much a technical as a creative process. This chapter explores how the launch of a software music package, Ultimate Soundtracker, for Commodore’s Amiga created a new, symbolic way to compose and edit music. It was sample-based and structured music using a grid-style interface that could be navigated using the computer keyboard, and its music files distributed both, making it easy to share—and copy—others’ musical ideas. This ‘open-source’ approach allowed nonprogrammers and nonmusicians to experiment with music making and for the sound to promulgate. This was also the period from which the term ‘chiptune’ emerged; the Amiga’s sample-based chipset allowed it to create other sounds beside raw electronic waveforms, and chiptune was used to highlight tracks written in the 8-bit sound chip style.
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Book chapters on the topic "Chip-package"

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Totta, Paul A., Subash Khadpe, Nicholas G. Koopman, Timothy C. Reiley, and Michael J. Sheaffer. "Chip-To-Package Interconnections." In Microelectronics Packaging Handbook. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6037-1_2.

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Viswanadham, Puligandla, Tom Chung, and Steven O. Dunford. "Chip Scale Package Technology." In Area Array Interconnection Handbook. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4615-1389-6_18.

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Koopman, Nicholas G., Timothy C. Reiley, and Paul A. Totta. "Chip-to-Package Interconnections." In Microelectronics Packaging Handbook. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4613-1069-3_6.

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Ghaffarian, Reza. "Chip Scale Package Assembly Reliability." In Area Array Interconnection Handbook. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4615-1389-6_23.

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Verghese, Nishath K., Timothy J. Schmerbeck, and David J. Allstot. "Modeling Chip/Package Power Distribution." In Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2239-3_8.

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Yeh, Meng Kao, and Wei-Xun Zhong. "Vibration Reliability in Flip Chip Package." In Key Engineering Materials. Trans Tech Publications Ltd., 2005. http://dx.doi.org/10.4028/0-87849-978-4.899.

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Qu, Shichun, and Yong Liu. "Fan-In Wafer-Level Chip-Scale Package." In Wafer-Level Chip-Scale Packaging. Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4939-1556-9_2.

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Qu, Shichun, and Yong Liu. "Fan-Out Wafer-Level Chip-Scale Package." In Wafer-Level Chip-Scale Packaging. Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4939-1556-9_3.

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Qu, Shichun, and Yong Liu. "Stackable Wafer-Level Analog Chip-Scale Package." In Wafer-Level Chip-Scale Packaging. Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4939-1556-9_4.

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Fischer-Hirchert, Ulrich H. P. "From Chip Design to the Optimum Package." In Photonic Packaging Sourcebook. Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-642-25376-8_12.

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Conference papers on the topic "Chip-package"

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Hsieh, Ming-Che, KeonTaek Kang, HangChul Choi, and YoungCheol Kim. "Thin profile flip chip package-on-package development." In 2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). IEEE, 2016. http://dx.doi.org/10.1109/impact.2016.7799981.

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Kuo, Po Chen, Cheng Hsiao Wang, Kai Kuang Ho, Kuo Ming Chen, Chung Yen Wu, and Ching Li Yang. "14 nm chip package interaction development with Cu pillar bump flip chip package." In 2015 IEEE 65th Electronic Components and Technology Conference (ECTC). IEEE, 2015. http://dx.doi.org/10.1109/ectc.2015.7159567.

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Khang Choong Yong, Wil Choon Song, Bok Eng Cheah, and Mohd Fadzil Ain. "Signaling analysis of inter-chip I/O package routing for Multi-Chip Package." In 2012 4th Asia Symposium on Quality Electronic Design (ASQED 2012). IEEE, 2012. http://dx.doi.org/10.1109/acqed.2012.6320509.

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Zheng, Ji, and Henry Lee. "Chip package-system co-design." In 2009 International SoC Design Conference (ISOCC). IEEE, 2009. http://dx.doi.org/10.1109/socdc.2009.5423783.

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Chua, Tiffany, Sarkis Babikian, Liang Wu, G. P. Li, and Mark Bachman. "Package-on-package for chip cooling with embedded fluidics." In 2012 IEEE 62nd Electronic Components and Technology Conference (ECTC). IEEE, 2012. http://dx.doi.org/10.1109/ectc.2012.6249051.

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Uchibori, C. J., Michael Lee, Xuefeng Zhang, et al. "Impact of Cu∕low-k Interconnect Design on Chip Package Interaction in Flip Chip Package." In STRESS-INDUCED PHENOMENA IN METALLIZATION: Tenth International Workshop on Stress-Induced Phenomena in Metallization. AIP, 2009. http://dx.doi.org/10.1063/1.3169258.

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Suzuki, Yasuhiro, Yuuji Kayashima, Takehiko Maeda, Yoshihiro Matsuura, Tomohisa Sekiguchi, and Akio Watanabe. "Development of thin Flip-Chip BGA for Package on Package." In 2007 Proceedings 57th Electronic Components and Technology Conference. IEEE, 2007. http://dx.doi.org/10.1109/ectc.2007.373769.

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Hsieh, Ming-Che. "Advanced flip chip package on package technology for mobile applications." In 2016 17th International Conference on Electronic Packaging Technology (ICEPT). IEEE, 2016. http://dx.doi.org/10.1109/icept.2016.7583181.

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Lee, Ren-Jie, and Hung-Ming Chen. "A package pin-block planner considering chip-package interconnects optimization." In 2009 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS). IEEE, 2009. http://dx.doi.org/10.1109/edaps.2009.5404013.

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Hsieh, Ming-Che, Stanley Lin, Ian Hsu, Chi-Yuan Chen, and NamJu Cho. "Fine pitch high bandwidth flip chip package-on-package development." In 2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition. IEEE, 2017. http://dx.doi.org/10.23919/empc.2017.8346847.

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