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Mehrotra, Gaurav. "Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22594.
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Tang, Zhenming. "Interfacial reliability of Pb-free flip-chip BGA package." Diss., Online access via UMI:, 2008.
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Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008.<br>Includes bibliographical references.
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Koh, Sau W. "Fatigue modeling of nano-structured chip-to-package interconnections." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28263.
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Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Rao R. Tummala; Committee Co-Chair: Ashok Saxena; Committee Member: Karl Jacob; Committee Member: Suresh Sitaraman; Committee Member: Thomas H. Sanders, Jr.
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Michielsen, Wim. "VCOs for future generations of wireless radio transceivers." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-492.
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Winter, Matthias [Verfasser]. "Integration kapazitiver Silizium-Mikrofone in ein Chip Scale Package / Matthias Winter." Aachen : Shaker, 2011. http://d-nb.info/1071529609/34.
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Shen, Meigen. "Concurrent chip and package design for radio and mixed-signal systems." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-476.
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Paydenkar, Chetan S. "Flip chip assembly process development, process characterization, and reliability assessment of polymer stud grid array-chip scaled package." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/19141.
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Neysmith, Jordan M. "A modular, direct chip attach, wafer level MEMS package : architecture and processing." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/17559.
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Yi, Ming. "Transient simulation for multiscale chip-package structures using the Laguerre-FDTD scheme." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53856.
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The high-density integrated circuit (IC) gives rise to geometrically complex multiscale chip-package structures whose electromagnetic performance is difficult to predict. This motivates this dissertation to work on an efficient full-wave transient solver that is capable of capturing all the electromagnetic behaviors of such structures with high accuracy and reduced computational complexity compared to the existing methods.
In this work, the unconditionally stable Laguerre-FDTD method is adopted as the core algorithm for the transient full-wave solver. As part of this research, skin-effect is rigorously incorporated into the solver which avoids dense meshing inside conductor structures and significantly increases computational efficiency. Moreover, as an alternative to typical planar interconnects for next generation high-speed ICs, substrate integrated waveguide, is investigated. Conductor surface roughness is efficiently modeled to accurately capture its high-frequency loss behavior. To further improve the computational performance of chip-package co-simulation, a novel transient non-conformal domain decomposition method has been proposed. Large-scale chip-package structure can be efficiently simulated by decomposing the computational domain into subdomains with independent meshing strategy. Numerical results demonstrate the capability, accuracy and efficiency of the proposed methods.
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Duo, Xinzhong. "System-on-package solutions for multi-band RF front end." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-482.
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Tsai, Kun-Ru, and 蔡坤儒. "reilability of flip-chip package." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/24977408487582831079.
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碩士<br>國立臺灣大學<br>機械工程學研究所<br>94<br>In study the reliability of electronic packages from mechanics point of view, the analytical of stress and strain obtained from finite element analysis and fatigue life prediction based on a Coffin-Manson equation are always constant values. However, the real outcomes of package life have probability distributions and frequently plotted in Weibull probability papers. In order to find out this contradiction, we suppose two kind of possible causes to investigate. One is the geometric parameters of a flip-chip package are random variables. The other is parameters of the Coffin-Manson equation are also random variables. The method of investigation is using finite element software to simulate a flip-chip package on thermal-cyclic loading. Then the cyclic equivalent inelastic strain range of a certain type of flip-chip package is found, and the fatigue life of the package is determined base on a Coffin-Manson equation. It is found that among different geometric parameters, the radius of solder bump affects the fatigue life of the package the most when considering the actually manufacturing tolerance. Considering parameters of the Coffin-Manson equation are random variables, we found the exponent parameter affects the fatigue life distribution more than the other parameter.
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Lee, Hsu-Chieh, and 李緒頡. "A Chip-Package-Board Codesign Methodology." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/48940177718280905195.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>99<br>In today''s IC production, the design processes of chip, package, and board are separate from each other. However, the lack of information from other domains dramatically increases the design difficulty and reduces the quality of the product. Especially, while most current IC''s still resides on a Printed Circuit Board (PCB), the PCB is usually not considered during the design of chip and package, which makes the PCB routing very difficult to complete with satisfying quality. As a result, PCB routing often becomes the bottleneck of the whole design flow, which significantly lengthens the time to market and reduces the profit margin.
In this thesis, we provide an extensive survey about the previous works on flip-chip RDL routing and PCB escape routing. We systematically introduce the methods and analyze their strengths and weaknesses in detail. After that, we propose a chip-package-board codesign methodology that provides cross-domain information integration. Our codesign flow has four major procedures: (1) inverse escape routing for board signal-ball assignment, (2) package aware I/O placement that reduces the RDL routing congestion, (3) RDL bump reassignment that balances the routing congestion of RDL and board, and (4) RDL and escape routing that completes the flow. Experimental results show that our codesign flow successfully complete the routing for all test cases while the traditional flow and other two board-driven flows all fail at either RDL routing or PCB escape routing.
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Lee, Jia-Shan, and 李佳賢. "Reliability analysis of flip chip package." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/44762572316649063537.
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碩士<br>國立中央大學<br>機械工程研究所<br>92<br>As the IC manufacturing technology improved,the electronic devices become small and light . Because the volume of the bump decreases,it suffers high current density and electrical field . The electromigration due to current crowding can not be ignored . Different bump shapes have different current density distribution and affect the current crowding position. For solving the electromigration caused by current density, investigating the relation between bump shape and current distribution is needed.
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Yu-KaiChen and 陳俞凱. "Molded Underfill for Flip Chip Package." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/54872767669755939896.
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碩士<br>國立成功大學<br>工程科學系碩博士班<br>101<br>Air trap in a molded underfill package always exists. It is an annoying problem and needed further investigation. In this research, the mold filling phenomenon of molded underfill (MUF) was investigated through numerical method. The carrier was a flip chip BGA (FC BGA) package. Moldex3D software was used as the tool. The resin was modeled as a reaction fluid. Cure kinetics and viscosity was measured and modeled. Kamal’s model was used for the cure kinetics. Castro Macosko’s model was used for the viscosity model.
The simulation results were compared with the experiment results and were found the short shot results agreed well with the experiments. The simulation results also showed that the locations of the air trap for each package could be accurately predicted if the simulation was well setup. The size of trapped air voids could also be well predicted if Boyle's Law was used as the constitutive model for the compressed air and considered air vent effect. The simulation results could serve as a good reference for engineers to alleviate the MUF air trap problems.
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Lee, Ren-Jie, and 李仁傑. "Algorithms for Chip-Package-Board Codesign." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/45606062599353937939.
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博士<br>國立交通大學<br>電子研究所<br>98<br>Due to the trend of more and more SoC and SiP projects, the complication in chip, package and board designs, and signal interactions thereof is increasing very rapidly. Typical peripheral wire-bond design will be inappropriate for most modern designs; therefore flip-chip package becomes an inevitable choice. However, engineers usually designate the key interfaces including I/Os, bumps and package pin-out (ballplan) by hands in conventional flip-chip designs. The chip-package-board co-planning process is indeed time-consuming and always postpones the time-to-market (TTM) of products. In response to the aforementioned issues, this dissertation proposes methodologies in planning those interfaces with concurrent codesign paradigm, thus speeding up the developing time dramatically.
The dissertation contains three parts. First, we propose a novel and very efficient approach to automating pin-out designation in flip-chip BGA packaging for package-board codesign. The manual time-consuming codesign works can be replaced by proposed methodologies. Through considering signal integrity, power delivery, and routability in pin-block design, our frameworks provide trade-offs in signal performance and package cost while achieving the minimum package size. Second, we present a planning algorithm to optimize pin-block locations by using a new representation for pin-block placement, and defining range constraints in stochastic framework. The experimental results show that our algorithm optimizes the system interconnects during package pin-out planning. In addition to the package-board codesign, we develop a concurrent design flow for chip-package codesign in the third part. Comparing with the previous works, the methods in this part preliminarily provide the optimization study of net crossing and length deviation which are very critical requirements in chip-package codesign. By designing specific I/O-bump tiles and proposing an innovative I/O-row based scheme, two heuristic methods and one assignment algorithm are provided for package-aware I/O-bump planning. As a result, a chip-package-board co-planning automation attempt is accomplished for optimizing performance and design cost simultaneously.
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Yang, Chiu-Chung, and 楊秋忠. "Wafer Level Chip Sized Package LED." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/57788441211425337330.
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碩士<br>大葉大學<br>電機工程學系碩士在職專班<br>96<br>This treatise offer a simple, fast, reliable, cost-decreasing and less heat-reserving package method of LED – Wafer Level Chip Sized Package [WLCSP LED]. In this method, we made an anti-environment protection layor on LED wafer directly in wafer chip process to protect the grains from oxidation and moisture. And, the lectrode, similar to SMD LED were grown, on the wafer directly. The well-cutted finished WLCSP LED chips are same as the finished package of SMD LED. So the followed packaging processes of LED, i.e. framing, mounting, wire bonding, epoxy encapsulation, are omitted. Omission of epoxy, bonded wire, frame or carrier board can reduce the cost of package and increase the dependability. This finished WLCSP LED chip is a Flip Chip LED, but there is no subtract with it. With bigger electrode as SMD LED, the heat from the contact can conduct out quickly by the shortest distance of bigger area of P, N metal electrode. We had checked the temperature of contact and found it was 20℃~30℃ lower than packaged LED products.
Following hereunder, I list 11 different points of package between WLCSP LED and the encapsulation method used now.
1. Chip manufacture procedure: there are 3 added procedures in WLCSPLED.
2. Encapsulation manufacture process: WLCSP LED omit all theprocedures of chip bonding, wire bonding and encapsulation. It means the package factory is unnecessary for WLCSP LED.
3. Heat sinks Junctions: WLCSP LED reduce the junctions from 5 or more in present encapsulation to only one junction.
4. Natural heat sink: WLCSP LED can sink heart by nature air convection.
5. LED dimension: WLCSP LED decrease the smallest dimension of LED from 100μm*500μm*400μm（0402） to 500μm*250μm*60μm（0201）【It is the smallest size SMD can manage presently.】or even smaller.
6. Heat sink organization: While LED is used in high power, it has to set alot of heat sink organizations. For WLCSP LED, sufficient effect can be got by just putting on MPCB only. The cost of heat sink organization is saved.
7. Processing temperature: At present, the processing temperature of LED in pre-heating can not higher than 100℃, and while passing the solder oven the temperature can not over 280℃*3 seconds. The processingcondition of WLCSP LED is same as which used for resistance or IC.
8. Stability and reliability: WLCSP LED has less processing junction, stand for higher processing temperature. For high power dimension the contacted area of electrodes and PCB increase about 36 times, whilethe surroundings condition change it can stand thermal impact.
9. Living life secured: theoretically, the living life of LED is 100 thousand hours, but poor heat sinks drop the living life. WLCSP LED securedthe working temperature under 77℃ the grain is working at low temperature. It extend the living life of white light LED. (For regular LED, the junction temperature is 100-140℃.)
10. Non-yellowing: Due to no epoxy resin is used in WLCSP LED, there is no yellowing and light attenuation problem.
11. Lowest cost: Since packed process is omitted, there are no encapsulation materials and present packed procedure with WLCSP LED. The cost can reduced to the target of lowest level. At present, the cost of WLCSP LED nearly match the target of NT$ 10/W.
From the above mentioned 11 main different points, this treatise offer a way to improve and overcome these 11 problems. We can see the larger potentiality and market opportunity of WLCSP LED.
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Chiang, Chang-Han, and 江昌翰. "Applications of InGaN base Flip-Chip on Wafer Level Chip Package." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/10263430112863448351.
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碩士<br>國立中興大學<br>光電工程研究所<br>101<br>Abstract
This research aimed at Flip-chip structure study to improve the heat dissipation problem that occurred in traditional wire bonding chip and also compare with chip characteristic and heat dissipation ability between these two different chip structures.
In Flip-chip structure reflector and passivation will influence the light intensity and chip reliability. Using different thickness in ITO and SiO2 with aluminum reflector in reflector experiment, the optimum reflection obtaining is around 82%. In passivation experiment, using silicon oxide, silicon nitride and aluminum oxide, the aluminum oxide revealed the best result in reliability test. Applied the optimum experiments parameters in this research to fabricate Flip-Chip, he obtained output power in Flip-Chip is higher, junction temperature is lower and intensity decay is smaller than transitional wire bonding chip.
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Hsu, Hsin-Wu, and 徐欣吳. "The Algorithms for Chip-Package-Board Interfacing." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/03317974454038795344.
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碩士<br>國立交通大學<br>電子研究所<br>100<br>Chip, package, and board are nowadays designed separately and then combined into one system by their interfaces. The interfaces have become much more complex as the number of input/output (IO) pins increases. Few commercial EDA tools provide effective support. Since the problems caused by interfaces involve many design decisions such as time-to-market (TTM) and productivity, and it is not easy to formulate, some practical and efficient interfacing methods are strongly in need to facilitate chip/package/system designs.
On the other hand, iterative re-works with package houses and RDL trial routing exist in conventional design flow. Accordingly, from design houses' point of view, co-design with package houses and good RDL router must be developed to enable fast implementation of RDL. Our proposed algorithms for chip-package-board interfacing contain two parts.
The first work is RDL routing on pseudo single-layer which targets at congested cases where 100\% routability cannot be achieved within single layer. Our approach can achieve 100\% routability and minimize the area for 2-layer routing on a real industrial case, outperforming a state-of-the-art commercial RDL router. The second work contains the methodologies which can generate package pin-out and wire planning for chip-package-board co-design. It provides wire planning without time-consuming routing process to estimate package size, signal integrity, and routability.
Our approaches can enable fast re-spin between chip, package, and system design houses.
Through these two works, design houses can greatly reduce the design efforts and time-to-market.
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Huang, Che-Hsuan, and 黃哲瑄. "Study on freeform-designed chip scale package." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/hm4846.
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博士<br>國立交通大學<br>光電工程研究所<br>107<br>The white light emitting diode has the advantages of high efficiency, power saving, long life and environmental protection, and has received much attention in recent years, especially in the TV backlight and lighting industry. Nowadays, the blue light emitting diode is used to excite the photoluminescent material to form white light. Among the photoluminescent materials, the characteristics of the phosphor are stable, it becomes the major photoluminescent material when the LED is popularized, Since the white light emitting diode technology is fully developed, the Quantum dots has the characteristic of narrow wavelength bandwidth, whose wavelength can be modulated by the particle size. It has gradually become the mainstream of the new generation of forward-looking semiconductor display technology.
On the other hand, it usually includes a set of secondary optical modules when the light emitting diode has been design from component to the module that can be used. Generally, the secondary optics modules include an internal total reflection lens, a free-form lens, and a Fresnel lens. But in response to the forward-looking display technology and the miniaturization trends required by IoT sensors, introducing the concept of secondary optics into the primary optics of components is a key technology currently under discussion.
In this study, our goal is to design a light emitting diode package with secondary optical characteristics and high light extraction efficiency. The first part, we establish a model for the energy transfer theory in the LED package, and use the concept of down-conversion to estimate the energy transfer model of light emitting diode suitable for real verification. This model is also verified both on phosphor and Quantum dots material. After the model is established, in order to improve the light extraction efficiency of the traditional light-emitting diode package, this study will optimize the wafer-level package light-emitting diode. This concept successfully increased the light extraction efficiency of the traditional SMD type package by 9.4%.
Furthermore, this study introduces the algorithm development process of the body light source correction for the free-form surface design method for the purpose of suitable primary optical components that is used in advanced TV backlight application and completes the "Study on freeform-designed chip scale package" with this algorithm. The structure has two advantages: 1. Bat-wing 140 degrees (bat-type light pattern) 2. Ultra-high light extraction efficiency (about 96%). It is suitable for forward-looking display technology in backlight applications like mini-LED.
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Chou, Chien-Hung, and 周建宏. "Package Warpage and Stress Analysis of Stacked Die and Multi-Chip Package." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/23997449215943207034.
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碩士<br>國立雲林科技大學<br>機械工程系碩士班<br>94<br>The three-dimensional stacked package, vertically stacking more than two chips in a package, meets the demand of more functions and higher capacity. The structure of 3D package is more complicated than the single die package. Thermal expansion mismatch between layer materials causes thermal deformation and stresses in a layered structure during manufacturing process. The chip configuration and material selection have effect on the mechanical performance of 3D package.
The deformation and stresses of a layered structure under thermal loading are calculated by theoretical formula and finite element method. The simulation results are verified by the theoretical results. In this study, the finite element model built by both the sequential processing and linear concept are used to predict the package warpage and stresses during the package manufacturing processes for both stacked die and multi-chip packages. The predicted package warpage after molding is compared with experimental measurements to verify the accuracy of finite element model. The induced component stresses of 3D packages during reflowing process are discussed. Also, the package warpage and stresses during manufacturing processes for three configurations of four-chip package are compared to discuss the chip configuration on package warpage and stresses.
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Chen, Yung-Wei, and 陳詠偉. "Refining The Package Processing and Material Analysis for Wafer Level Chip Scale Package." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/42722700973187991870.
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碩士<br>國立交通大學<br>理學院應用科技學程<br>104<br>Wafer level package is one of the advanced integrated circuit (IC) packages.The packaging processing is carried out directly on the whole wafer after it is produced. Then, the packed wafer is cut into single ICs. Neither wire bonding nor fillers are required in the process. After being packaged and cutt, the chip size is very close to the original crystalline grain of the device. As a consequence, the packaging process is named as wafer level chip scale package(WLCSP), which is currently an important issue for the research and development of major packaging companies.
Here we concentrate on refining the wafer level packaging process and packaging materials analysis. The flow of process for the wafer level packaging and the processing methods are introduced in the beginning.Our experimental
methods are presented and the experimental results are summarized in short. The material analysis was carried out by using scanning electron microscope (SEM) and the sizes of silver particles were investigated. In addition, the stencil and scraper printing parameters were adjusted to improve the silver paste printing.The most importance is that the quality of silver paste printing was maintained for the paste of low concentration of silver particles. The paste printing quality was inspected by a white light interferometer. It is confirmed that the surface of
the circuit board is flat and the roughness is small enough, even though the silver paste with low concentrations (such as 70%) of silver particles is used.Moreover, the using of low concentration silver paste passed all electrical measurements and reliability tests as well.
To increase the durability of the packaging, we used under-filler with glues of different viscosity by spraying instruments for the final stage of packaging process. It is found that the under-filler coating on the surface of the wafer help to protect our ICs. The protection solves many common problems, such as damages due to the transportation of IC wafers and the surface mount device (SMT) processes.
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Shih, Wen-Yu, and 施文郁. "Optimal Pad Assignment for Two-Layer BGA Package Using Chip-Package Co-Design." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/ma5s7e.
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碩士<br>國立中央大學<br>電機工程研究所<br>96<br>When semiconductor technology further scales into nanometer era, I/O-pad counts increase continually due to more and more function in chip. The locations of I/O pads not only affect the package design, but also change the noise inside the core. The traditional approaches solve these problems in package design flow and physical design flow respectively, which may have time-consuming and over-design problems. Using chip-package co-design method in pad assignment stage may be a practical approach to simultaneously solve these problems. A good pad assignment can improve the routing quality in packages and reduce the IR-drop in cores, which may solve the over-design problem and shorter the design cycle, too.
In this thesis, a chip-package co-design approach is proposed to reduce the routing congestion in packages. A pad switching algorithm is also proposed to control the routing congestion in packages and the IR-drop in cores at the same time. The experimental results of this work are encouraging. Compared with different approaches, our methodology reduces the routing congestion in packages and the IR-drop in cores simultaneously in all test circuits.
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Han, Fu-yi, and 韓府義. "Modeling of Flip-Chip and Wire-Bond Chip Scale Packages for RF Chip-Package Co-Simulations." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/71759436123532731933.
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博士<br>國立中山大學<br>電機工程學系研究所<br>97<br>This dissertation aims to evaluate the package effects on the performance of radio frequency integrated circuits (RFICs) for wireless applications. A model-based study is presented to compare the effects between flip-chip and wire-bond packages on a front-end cascode low-noise amplifier (LNA) in a 2.45 GHz CMOS wireless local area network (WLAN) receiver. To construct the package electrical models, specific modeling dies are designed to help extract the equivalent-circuit elements from measured S-parameters for chip-package interconnects. Furthermore, the ground-proximity effect on on-chip spiral inductors in a flip-chip package is first observed and presented in this modeling study. Excellent agreement between modeling and measurement is obtained by up to 20 GHz for a 64-pin flip-chip ball grid array (FC-BGA) package and a 64-pin wire-bond quad flat nonlead (WB-QFN) package. For practical applications, the established package models are used to predict the degradation of the figure of merit for the cascode LNA under packaged condition. Chip-package co-simulations can achieve good agreement with measurements, and thus can persuasively account for the complete effects caused by the two different packages on the cascode LNA.
To simultaneously consider the package and board interconnect effects on RFICs, this dissertation also designs and implements a 1.95 GHz upconverter for the wideband code-division multiple-access (W-CDMA) transmitter. Specific ground wire-bonding and board connection are designed to minimize the linearity degradation due to package and board interconnects. Nonlinear analysis technique is also used to evaluate the nonlinear distortion of the upconverter in the chip-package-board co-design phase. The final measurement results have successfully verified the co-design predictions and simulations for this upconverter.
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Lin, Ya-Wen, and 林雅雯. "New Package Free Technology in White LED chip." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/nuejsn.
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碩士<br>中原大學<br>電子工程研究所<br>102<br>This paper introduces a novel package-free chip (PFC) fabrication technology for white LED. It also reports the characterizations of optical properties and thermal effect for the devices produced. The white LED PFC can increase the heat-dissipation ability and lighting angle for device’s indoor lighting applications. The white LED PFC can also eliminate the failure of wire bonding, simplify the packaging process and achieve high-yield production. The luminous fluxes of the white LED PFC measured were about 104.41 lm at 3000K and 113.74 lm at 4000K, respectively, under the applied power of 1 W. A further investigation showed that the heat steady luminous flux are 90.43 lm at 3000K and 99.48 lm at 4000K, respectively under a continuous burning for 30 minutes.
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LIN, CHEN-HAO, and 林晨浩. "Finite Element Analysis of Embedded Chip Package Structure." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/77627957689001330628.
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碩士<br>中華大學<br>機械工程學系<br>105<br>Now a day, according to the powerful application functions and the higher computing speed are necessary in electronic products, the components and circuits make the circuit board more thicker, but the trend of small, slight and thin are avoidable. Component embedded is a method to reduce the size and improve the reliability but also lower cost.
Because the market of wearable electronic products is booming recent years, the demand of FPC is also increasing, improving the technical capabilities to make the applications more portable and versatile for today's major trend.
By using the finite element analysis ANSYS software to establish the finite element model can effectively reduce the cost time and resources, it can confirm the feasibility of product production before the preliminary and advance design.
In this paper, the structure of a package carrying an embedded chip on an FPC substrate will be discussed, using ANSYS software to build up four finite element models which embedded in a cavity with PCB material is model A-1; embedded in a cavity with FPC material called model A-2; direct embedded with PCB material called model B-1; direct embedded with FPC material called model B-2, and a quarter globally symmetric model of conduct Anand Thermal Cycle Test (TCT) simulation with the thermal load of -55 oC to 125 oC, a cycle of 60 minutes of simulated three times.
Then estimate the fatigue life by the result of the analysis in order to compare the results of two kinds of embedded methods and two types circuit board materials and analyzes the advantages of four different combinations.
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Fang, Jia-Wei, and 方家偉. "Routing Algorithms for Chip-Package-Board Co-Design." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/31233120502420379059.
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博士<br>國立臺灣大學<br>電子工程學研究所<br>97<br>In VLSI deigns, nanometer effects have complicated the designs of chips as well as packages and printed circuit boards. Further, due to higher functionality in modern circuits, the number of I/O’s is also dramatically increased. In order to improve the routability, performance, and convergence of the design, two advanced packaging technologies: ball-grid-array packaging and flip-chip packaging, and chip-package-board co-design are strongly recommended by industry. In this dissertation, we present the first routing algorithms in the literature for chip-package-board co-design based on the two advanced packages. They can not only be applied to complete (1) the routing in the packages and printed circuit boards, but also can consider (2) chip-package co-design, (3) package-board co-design, and (4) chip-package-board co-design.
For the routing in the packages and printed circuit boards, our routing algorithms adopt a two-stage technique of global routing followed by detailed routing. In the global routing, the computational geometry techniques (e.g., the Delaunay triangulation and the Voronoi diagram), minimum-cost maximum-flow network algorithm, and integer and linear programming are used to find an optimal global-routing wirelength for the addressed problems. Since we consider the wire congestion in our global-routing networks, the detailed routing can generate a 100% routable sequence to complete the routing.
For chip-package co-design, an I/O netlist between a chip and a package can be simultaneously generated with the package layout. Therefore, the total wirelength can be reduced. By considering package-board co-design, the routing information from the chip and the printed circuit board can be kept during the package routing. Consequently, the routability can be improved. In chip-package-board co-design, due to the great design flexibility, we can additionally consider the I/O planning of a package except the package routing. Hence, the design cost can further be reduced in the early stage. Further, we can also get much shorter total wirelength and higher routability.
Experimental results based on real industry designs show that our routing algorithms can achieve 100% routability and the optimal global-routing wirelength and satisfy all design constraints, under reasonable CPU times, whereas recent related work results in much inferior solution quality.
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Wang, Yiwei. "Electromigration and chip-package interaction reliability of flip chip packages with Cu pillar bumps." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-12-4474.
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The electromigration (EM) and chip-package interaction (CPI) reliability of flip chip packages with Cu pillar structures was investigated. First the EM-related characteristics of Cu pillars with solder tips were studied and compared with standard controlled collapse chip connection (C4) Pb-free solder joints. The simulation results revealed a significant reduction in the current crowding effect when C4 solder joints was replaced by Cu pillar structures. As a result, the current-induced Joule heating and local temperature gradients were reduced in the Cu pillar structure. This was followed by a study of the impact of the Cu pillar bumps on the mechanical reliability of low-k dielectrics. The CPI-induced crack driving force for delamination in the low-k interconnect structure was evaluated using a 3D sub-modeling technique. The energy release rate was found to increase significantly for packages with Cu pillar bumps compared with those with C4 Pb-free solder joints only. Structural optimization of Cu pillar bumps to improve the mechanical stability of packages with low-k chips was discussed.<br>text
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Zhang, Xuefeng. "Chip package interaction (CPI) and its impact on the reliability of flip-chip packages." 2009. http://hdl.handle.net/2152/7539.
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Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging of Cu/low-k chip with organic substrate. The thermo-mechanical deformation and stress develop inside the package during assembly and subsequent reliability tests due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip and the substrate. The thermal residual stress causes many mechanical reliability issues in the solder joints and the underfill layer between die and substrate, such as solder fatigue failure and underfill delamination. Moreover, the thermo-mechanical deformation of the package can be directly coupled into the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The thermo-mechanical reliability risk is further aggravated with the implementation of ultra low-k dielectric for better electrical performance and the mandatory change from Pb-containing solders to Pb-free solders for environmental safety. These CPI-induced reliability issues in flip-chip packaging of Cu/low-k chips are investigated in this dissertation at both chip level and package level using high-resolution Moiré interferometry and Finite Element Analysis (FEA). Firstly, the thermo-mechanical deformation in flip-chip packages is analyzed using high-resolution Moiré interferometry. The effect of underfill properties on package warpage is studied and followed by a strategy study of proper underfill selection to improve solder fatigue life time and reduce the risk of interfacial delamination in underfill and low-k interconnects under CPI. The chip-package interaction is found to maximize at the die attach step during assembly and becomes most detrimental to low-k chip reliability because of the high thermal load generated by the solder reflow process before underfilling. A three-dimensional (3D) multilevel sub-modeling method combined with modified virtual crack closure (MVCC) technique is employed to investigate the CPI-induced interfacial delamination in Cu/low-k interconnects. It is first focused on the effects of dielectrics and solder materials on low-k interconnect reliability and then extended to the scaling effect where the reduction of the interconnect dimension is accompanied with an increased number of metal levels and the implementation of ultralow-k porous dielectrics. Recent studies on CPI-induced crack propagation in the low-k interconnect and the use of crack-stop structures to improve the chip reliability are also discussed. Finally, 3D integration (3DI) with through silicon vias (TSV) has been proposed as the latest solution to increase the device density without down-scaling. The thermo-mechanical reliability issues facing 3DI are analyzed. Three failure modes are proposed and studied. Design optimization of 3D interconnects to reduce the thermal residual stress and the risks of fracture and delamination are discussed.<br>text
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Chen-JungWong and 翁振榮. "Reliability of Flip Chip-Plastic Ball Grid Array Package." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/54558979279914245759.
Full textAbstract:
碩士<br>國立成功大學<br>機械工程學系碩博士班<br>100<br>We used Mechanic APDL(ANSYS 12.0) to build three types of the leaded(Sn37Pb) and lead-free(Sn3.8Ag0.7Cu) solder of the flip-chip plastic ball grid array. These three types are: Type1 (no heat spreader and no molding compound), Type2 (added molding compound with no heat spreader), Type3 (added heat spreader and molding compound).The model set the chip center as the original point, and both X and Y directions are Geometric symmetry, so that the model is a quarter of the entire model. There are totally 90 minutes to proceed the temperature cycling test(TCT) simulation with 30 minutes for each cycle.
In the simulations, all the solder bumps and the solder balls are modeled as nonlinear visco-plastic, and time and temperature dependent material based on Anand's constitutive equation, and other materials are treated as linear elasticity. This study uses Modified Coffin-Manson To analyze the fatigue life of the solder joint with plastic strain results from finite element simulations, and finds out the maximum and minimum stress-load and thermal strain on the solder joint. Comparing the effect of fatigue life of leaded or non-leaded solder joint with different types was then performed in this thesis.
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Chen, Meng-Ling, and 陳孟伶. "Routability-Driven Bump Assignment for Chip-Package Co-Design." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/61838305486549089439.
Full textAbstract:
碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>101<br>In current chip and package designs, it is a bottleneck to simultaneously optimize both pin assignment and pin routing for different design domains (chip, package, and board). Usually, the whole process costs a huge manual effort and multiple iterations thus reducing profit margin. Therefore, we propose a fast heuristic chip-package co-design algorithm in order to automatically obtain a bump assignment which introduces high routability both in RDL routing and substrate routing (100\% in our real case). Experimental results show that the proposed method (inspired by board escape routing algorithms) automatically finishes bump assignment, RDL routing and substrate routing in a short time, while the traditional co-design flow requires weeks even months.
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Zi-PengWu and 吳子朋. "Investigation of the reliability for the Flip-Chip Package." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/81753194367549513650.
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碩士<br>國立成功大學<br>機械工程學系碩博士班<br>98<br>Abstract
In this study, the finite element analysis using the commercial code ANSYS12.0 has been performed to study the thermal-mechanical and heat-transfer behavior in the FC-PBGA. FC-PBGA model consists of seven parts, including heat spreader, molding compound, underfill, chip, substrate, thermal via, solder ball, solder bump, and PCB board. The model is constructed by different materials and each material has its own function to demonstrate its characteristics. For analysis on thermal-mechanical behavior, the viscoeplastic behavior of solder ball is modeled using Anand model, the viscoeplastic behavior of molding compound is simulated by Maxwell model, and the other parts are using linear elastic model to simulate. As a result, analysis of transformation behavior of FC-PBGA can be carried out under a 125℃~-40℃ heat cycling environment. For heat spreading analysis, the beginning temperature of FC-PBGA and surrounding area is 50℃, and the heat dissipation per volume unit of chip is 0.03W/mm^3.
When it reaches the stable condition, There are two design goals. One is to maximum the heat transfer performance, and the other is change the coefficient of variation(c.o.v) and Young’s Modulus of the molding compound, substrate,underfill and the other width and height of BT layers, both the maximal and minimal deviation of the solder bump equivalent strain affects the fatigue life of the package the most. The fatigue life of the package is determined base on a modified Coffin-Manson equation.
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Hsu, Sheng-hung, and 許勝閎. "Study of enhancement in brightness of Chip Scale Package." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/ntvkyy.
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碩士<br>元智大學<br>光電工程學系<br>105<br>CSP is the latest memory wafer packaging technology. It allows wafer area and packaging area ratio exceeds 1: 1.14 and it is almost close to 1: 1. The absolute size is only 32mm2, which is one-third of ordinary BGA packaging, and one-sixth of TSOP package. Comparing to the BGA package, the storage capacity of CSP package can be three times more than BGA.
The overall luminous efficacy of epi has got close to the physical limits; the room for improvement is limited. In order to improve the efficient of lightening to the chip unit, increasing the size of chip or changing the packaging type are relatively feasible.
The goal of this research is to propose new method of CSP in the perspective of cost down, to develop new efficient CSP with principle of LED and characteristics of the phosphor. By adjustment the proportion of phosphor, let the specification of samples be much similar. Choosing one of the samples to be control group, and silicone is used to add in other experiment group.
This research simulates with TRACEPRO, use silicone as a reflecting surface to make several light paths totally reflected through the phosphor, and eventually achieve the purpose to enhance the brightness.
The result of this research shows that the reflection through the silicone of CSP can increase the efficient of lighting from four to twelve percentages much more than currently. The simulation result shows the lightning can be increase ten percentages if increasing the area of silicone from 1.3mm*1.3mm to 2mm*2mm. Further, the lightening can even increase thirty-two percentages by changing the structure to Dome lens type.
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Li, Yu-Jia, and 李育嘉. "Optimal Design of Fatigue Life for Stacked Chip Package." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/9uv978.
Full textAbstract:
碩士<br>國立成功大學<br>工程科學系碩博士班<br>93<br>In accordance with the requirement of miniature, less weight and high density of electronic products， the traditional single chip package has no longer met the market demand any more. Instead, the scale of package should be reduced. As a result, a stacked chip package with integrated character and multi-functions becomes a favorite trend in the future. For minimizing the volume of the electronic component，the stacked chips with 3 D package can be applied to ensure the advantages of saving space, higher electric performance, higher function integration and less area of printed circuit board so as to reduce production costs. Thus it follows that the package becomes more complicate so that the solder balls are required to endure more thermal stresses existing between the B.T. substrate and the printed circuit board . A complicate deformation may lead to the damage of solder balls easily.
This study applies the ANSYS 7.0 Finite Element Analytical Software to simulate the viscoplastic behavior of the solder ball for the stacked chip package under the thermal cycling loading. Meanwhile the effects of multi-chip’s geometric shape, the thermal expansion coefficient and the Young’s Modules of the Epoxy Molding Compound on the life of solder balls are discussed. Finally the Taguchi Method is applied to obtain an optimal stacked chip package.
Acknowledging the lack of domestic related studies on stacked chips, this study expects to conduct the parameters analysis in details. Hopefully, a more complete design measure for the stacked chips can be proposed so as to improve the reliability of the solder ball and upgrade the products competitiveness.
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Chang, Chun-Ping, and 張鈞評. "Building the Chip Scale Package Model With Fluorescent powder." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/65938952897467800501.
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Chou, Yuan-Lung, and 周遠龍. "Chip Scale Package LED Beam Pattern Measurement and Simulation." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/12274385268271505584.
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碩士<br>國立中興大學<br>精密工程學系所<br>105<br>LED nowadays is usually packed by single-sided small white case. This paper is to discuss and compare the CSP LED which utilizes five sides to light with the small white case package. The volume of CSP LED is smaller and has four additional lateral sides to light that is a more efficient way to utilize the luminous efficiency. However, it is not discussed in details in general research regarding the luminous flux and the optical model distribution of the front side and lateral side. Therefore, the luminous flux and the optical model are measured separately for CSP LED’s front side and lateral side in this paper. And compare the luminous flux and the optical model for the front side and lateral side by experiment. The precise luminous model produced by the five sides of CSP LED is built successfully through this research, it will have positive helpfulness for the building and application of optical model in the future.
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Tseng, Zhi-Hao, and 曾致豪. "Fabrication and Package of Flip Chip Type Micro Gyroscope." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/90943670945242189012.
Full textAbstract:
碩士<br>國立清華大學<br>工程與系統科學系<br>93<br>In terms of the semiconductor and MEMS technology, package is the process that all the devices have to go through before being taking out of the laboratory. In the MEMS field, most of the ways of packaging are adopted from those of the traditional IC packaging, which, however, cannot satisfy the various needs of the modern MEMS devices and also increases the cost of the MEMS devices greatly.
This thesis is mainly about the fabrication of the third generation micro gyroscope that our laboratory have developed, the successful design of the structure of the flip chip type packaging, which is able to both transmit electric signal and function the hermetic sealing. With the structure, the packaging of the micro gyroscope has been successfully completed. Furthermore, by using the test vehicle chip, the electric resistance, ranging from 1.8 to 1.9Ω, has been measured from the flip chip solder bump which transmits electric signals. The helium leak rate of the hermetic sealing chamber is 2.4 to 4.8×10-8 atm．cc/s.
The result of the research shows that the innovative design of the structure of the flip chip type package demonstrated in the thesis can be applied in the signal transmission and the hermetic package of the multiple I.O. micro device. Moreover, the design can effectively minify the size of the packaging devices as well.
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Chen, Chih-Hao, and 陳志浩. "Structural stress simulation of the chip-in-substrate package." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/41536073608904970538.
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碩士<br>國立屏東科技大學<br>材料工程所<br>96<br>In our previous study, the weakest interfacial shear strength is the RCC/Al interface of the chip-in-substrate package. The resin cracking or delamination at the RCC/Al interface possibly occurs under temperature cycling loading mainly due to the thermal expansion coefficient mismatch of chip and resin.
Effects of the thickness of the chip, substrate and RCC resin, and the modulus of RCC on the structural stress of the chip under temperature cycling(TC) loading were investigated. The numerical stress analysis was carried out by the finite element method using ANSYS software with 2D model. The optimum condition of the thickness of the chip, substrate and RCC resin, and the modulus of RCC were taken into consideration to minimize the structural stress of the CiSP during temperature cycling loading.
Key words: Chip in substrate package, Resin coated copper, Interfacial shear strength, Temperature cycling test
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Wang, Ting-Chieh, and 王鼎傑. "Thermal Improvement of High Power LED Chip Scale Package by Using Thin Metal Package Technique." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/7b93n5.
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碩士<br>國立交通大學<br>光電科技學程<br>106<br>In solid state lighting, such as light emitting diode (LED), the light emission efficiency will decrease with the temperature increase. Therefore, the heat dissipation is one of the key factors in thermal management, in particular, for high power LED applications. From the LED package structure, the contact mode is the major heat dissipation path that is from LED chips, LED grain carrier substrate, and solder board to ambient. The thermal substrates, such as MCPCB and Al2O3 ceramic substrate, are frequently used in LED grain carrier substrate for heat dissipation. However, when LED chip scale package (LED CSP) is close to the chip size, the efficiency of the above thermal substrates on heat dissipation is insufficient, and the higher thermal resistance of the insulated metal substrate (IMS) used in thermal substrate will also become the bottleneck of heat dissipation. In order to improve the above issue, thin metal package (TMP) substrate was proposed to replace the conventional LED grain carrier substrate to connect LED electrode to solder board, and quickly dissipate the heat. In thermal system, the thermal resistance is one important index to check the thermal conduction ability of materials. In this study, the thermal resistances of TMP and other substrates were investigated and compared. From the experimental results, the proposed TMP exactly provided better heat dissipation performance and lower thermal resistance than that of conventional thermal substrate to greatly reduce the loss of the relative luminous flux and optical characteristic shift with the increase of LED junction temperature.
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Liu, Qing. "Quilt packaging a novel high speed chip-to-chip communication paradigm for system-in-package /." 2007. http://etd.nd.edu/ETD-db/theses/available/etd-12202007-185646/.
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Thesis (Ph. D.)--University of Notre Dame, 2007.<br>Thesis directed by Gary H. Bernstein for the Department of Electrical Engineering. "December 2007." Includes bibliographical references (leaves 182-194).
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陳柏琦. "Simulation of warpage and reliability assessment of chip size package." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/41790539192924393369.
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碩士<br>中國文化大學<br>材料科學與製造研究所<br>90<br>In this study, the reliability of low coefficient of thermal expansion (CTE) epoxy molding compound based on the flexible substrate chip scale package (CSP) was experimentally investigated. The CSP was attached on the flexible substrate as a test vehicle and the dimension of this test vehicle is 12mm×12mm×1.2mm. The reliability was tested by using the Joint Electron Device Engineering Council (JEDEC) JESD22A113A-level 3 method that included precondition and long tern. As the results, the test vehicle was passed the JEDEC level 3 precondition test and with a low warpage. Furthermore, the test vehicle also passed the pressure cooker test, temperature cycle test and temperature shock test under level C condition
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Yeh, Yao-Ting, and 葉耀庭. "Miniaturization of CMOS Image Sensor Using Glass Cover Chip Package." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/74654676608172353949.
Full textAbstract:
碩士<br>國立彰化師範大學<br>電機工程學系<br>95<br>Abstract
The purpose of this thesis is to reduce the package size of CMOS image sensor by using glass cover chip（GCC）technique in the packaging manufacture process. Traditional packaging technique needs dam to attach optical glass on the chip. However, GCC technique directly uses optical glass to attach chip using adhesive. Therefore the package size of GCC technique is smaller than that of the traditional package. Based on GCC technique and Taguchi method, in this thesis we design a new CMOS image sensor package structure. Experimental results demonstrate that the performance of the proposed design is better than that of the non-optimal design in term of adhesion force, package size and SNR (Signal to Nose Ratio). Further, simulations show that the thermal diffusion of our method is better than that of traditional method in the ratio of 245%. Hence, the proposed technique can meet the real requirements in the packaging process.
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Yao, Nai-Yu, and 姚乃鈺. "The study of direct chip package module of color-mixture." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/55009678198979515728.
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碩士<br>雲林科技大學<br>光學電子工程研究所<br>98<br>In this thesis, the high uniformity of 1W surface mount type hybrid optical modules using optical
software TracePro to simulate the front study, by using four-color mixing with self-developed formula to
avoid the present white light emitting diode patent, and the four-color grains are Red, Green, Blue and
adding Y to modify the overall quality of the mixed light. Series-parallel array of grain arrangement
adopted to achieve the high demand for uniformity, while simplifying the design conditions by a certain
voltage instead of the general mixed light-driven complex driver circuit, the completion of the mixing
module using the aluminum plate heat to work properly, and using integrating sphere, light spectrum on
the spectrophotometer, optical power, color coordinates values, such as mixing uniformity measurements.
The chromaticity coordinates errors after complete results of the mixing module measurement and
simulation can be controlled under (0.01x, 0.01y).
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Shang-Wei, Chen, and 陳祥維. "The Characterization of Flip Chip Package by Michelson Interferometry Analysis." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/41704702183233156568.
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碩士<br>國立海洋大學<br>光電科學研究所<br>90<br>ABSTRACT
The objective of the present research activity is to develop an effective technique using Michelson interferometer to characterize the thermal-induced deformations and stress distribution in flip chip packaging(FCP) , and the chip size packaging (CSP). Compare to other methods; such as laser spots analysis, more analysis technique, and the holographic method, Michelson interferometer approach is more reliable in whole area and fast time measurement. Michelson interferometer is useful for measuring the micro- displacement on the surface of the specimen under thermal testing process during the temperature cycle. Due to the flip chip package have gained popularity in high speed devices and PC industry, due to its advantages of low cost and high mass production. The issue of flip chip packaging is the global deformation on the chip surface. The deformation can cause an open circuit , and reduces the reliability of the device. By measuring the phase difference of a projected laser light across the deformed surface, high resolution surface profile measurement of the flip chip is obtainable. In addition, the development of an effective soft ware to transfer the phase difference information into real space deformation of the chip surface is essential to the success of this study. It is shown that the Michelson interference surface deformation system is useful to the application in Flip Chip packaging industry.
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Teng, Chih-Yung, and 鄧志勇. "The Electrical Characteristics of Flip-Chip Package at Microwave Frequency." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/33507386435883953156.
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碩士<br>國立臺北科技大學<br>機電整合研究所<br>89<br>Recently, Flip-chip(FC) package technology turns into an important package technology. More and more scholars have studied in reliable and heat transferred fields of the FC bump interconnect, however, the research of electrical characteristics of a FC Bump interconnect is not taken more attention.
In this paper a coplanar waveguide（CPW）on substrate connected by a FC bump with the other CPW is analyzed in the frequency range of 1 GHz to 60 GHz. The electrical characteristics of various FC bump dimensions and length of the overlap of the CPW on the substrate caused by inaccurate alignment are presented and analyzed. Base on the simulation with Zeland’s IE3D simulation software, we concluded that various FC bump dimensions and length of overlap by inaccurate alignment play an important role in the electrical characteristics of the FC bump interconnection.
In this thesis, S,Y parameters and equivalent circuit obtained by Zeland’s IE3D simulation software are regarded as the main parameters for analysis. The frequency band was obtained by observing the S parameters, R,L,C values could be obtained by Y parameters and equivalent circuit. From the result above, the relation of FC bump dimensions and alignment accuracy could be obtained.
Finally, we summarize how to achieve minimum signal loss with maximum overlap length by FC dimensions in order to reduce the effect of signal transmission reflection caused by inaccurate alignment.
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Lin, Hsiang-Wei, and 林祥偉. "The study of flip chip package technology for flexible eletronics." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/78309744981246293288.
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碩士<br>萬能科技大學<br>工程科技研究所<br>97<br>Flexible electronics and flexible display are both a new industry after the semiconducter industry and liquid crystal display industry. The flexible electronics has saved peaple’s space and causes the electronic products to be small more and more.
Smart cards have enjoyed a steady growth in global market, with higher penetration and prevalence for everyday use. Asian market for smart cards has developed greatly, in particular with the success of Octopus Card in H.K. In addition, the chain store industries have adopted smart cards for better efficiency of consumer relationship management, with online service to integrate the expanding service market.
Smart cards are beneficial not only because they are a powerful strategic tool for customer relationship managenment, but also duo to their supplementary values based on the high-tech feature that can enhance the characteristics of chain store industries, service and convenience-oriented. This competitive edge of smart cards allow marketers to lower the cost, increase communication efficiency with customers and thus generate more profits.
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Liu, Juei-Sien, and 劉睿賢. "Fatigue Life Analysis for Solder Joints of Flip Chip Package." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/99203075074050538842.
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碩士<br>國立交通大學<br>機械工程系<br>89<br>Flip chip package has become a very attractive solution with increasing demand on low cost, miniaturization, and weight reduction of electronic products. The major reliability issue of flip chip package is solder joint crack due to thermal expansion mismatch between joined materials. The purpose of this research is to study the solder joint reliability of flip chip subjected to temperature cycling. FEM code ABAQUS was applied to investigate the nonlinear behavior of eutectic solder joint (63Sn-37Pb) under temperature load. Fatigue life of solder joint was predicted by Coffin-Manson relationship. Good agreements were obtained between numerical results in this thesis and experimental data in other researches. To complete the study, Taguchi method was performed on the choices of underfill materials and size of the package. The final goal is to establish the methodology in obtaining the optimized combination of these parameters to improve the reliability of flip chip.
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Liu, Zhen nan, and 劉振南. "Design and Reliability Analysis of No-Underfill Flip Chip Package." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/49160493942684254855.
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Lin, Chang-hsien, and 林昌賢. "The Fabrication Process of Solder Bumps in Flip-chip Package." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/84480323746116131022.
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碩士<br>國立臺灣大學<br>材料科學與工程學研究所<br>87<br>The effort of this study is concerned with the research and development of a fabrication process of solder bumps on a silicon wafer. The whole process involves the growth of oxide layer, thermal coating or sputtering of metallic thin films, photolithography, electroplating, photoresist removimg, etching and reflow technologies. In addition, owing to the electromigration and interconnection delay of aluminum interconnectors in high-density integrated circuits with fine pitch, it is the future trend to replace the aluminum interconnectors with copper, which possesses lower resistivity and higher electromigration resistance. As a result, several UBM combinations of metallic thin films with copper pads including the effects of diffusion barriers against copper diffusion are also discussed.
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LI, CHUN-HSIEN, and 李俊弦. "The Study of Warpage of The Single Flip Chip Package." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/fafrdc.
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碩士<br>國立高雄大學<br>電機工程學系-電子構裝整合技術產業碩士專班<br>106<br>Due to the increasing of the complexity in design package of modern chip, the capacity of signals and the signal transmission rate is increasing, the interconnection path is shorter, and the substrate layout density is increasing, etc. As a result, the flip chip package has been developed. The flip chip package product consists of die, solder bump, underfill, substrate and solder ball, and each element has its characteristic properties of thermal expansion and Young's modulus. Therefore, during the temperature changes, each substrate element will be suffered internal mechanical interaction and thermal expansion these factors will result in warpage of package. Warpage related issues will make miss-alignment between solder bump and under fill cracks problem. This thesis is focused to study the effects of substrate warpage that caused by different substrate core material, substrate core thickness and adhesive material between bumps and substrate. In approach, numerical simulation has being used to achieve a prototype Flip-Chip package, then a series of warpage measurement by Shadow moire' has been conducted to study the effects of warpage due to core structures and under fill materials. As a result, an optimized Flip-Chip substrate design was achieved. It shows that the core substrate thickness is the main factor of the warpage of thin Flip-Chip packages, and substrate with lower CTE performed better adhesion property between solder ball and substrate.
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Chang, Ming-Li, and 張銘利. "Design and Development of High Power Multi-chip LED package." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/ha84pp.
Full textAbstract:
碩士<br>國立虎尾科技大學<br>光電與材料科技研究所<br>99<br>In recent years, the development of LED light sources was carried out all over the world. Especially for general illumination, backlighting of the monitor or automotive lighting is by far the most popular themes. This paper is primarily a study on lighting design. The common light sources on the market are mostly designed by high power LED chips. However, the external quantum efficiency of the present high power LED chip was poor. Because the operation power is higher than before, such that the generated heat can be easily accumulated and that the temperature of heat source is also higher than before. For the general LED packaging design, the junction temperature can be well controlled less than 70oC if possible. At the same time, more tasks must be used in the back-end heat sink, and its costs are also high.
This study focused on the LED light source design and verification, using a base substrate and arranged most of an array type LED chips set onto the substrate. By using the small-size LED chips (between 280~500 microns), the substrate thickness and chip spacing are well controlled. It was found that the space between every two LED chips is twice times above the size of the chip. The thermal resistance will have a slowing down rate. The temperature reduction is less obvious when the additional space was given. In addition, the multi-chip LED submount was verified by the experiment. We found the thermal resistance decreased by increasing the thickness of submount. The reduction of thermal resistance is slowing down while the thickness is increasing over 2mm. However, based on cost effective, current copper and aluminum plate was commercially available with a thickness of 1.0~2.0 mm. Finally based on the thermal simulation results, if the temperature of heat sink can be controlled within 60oC, the reliability can be achieved pass through the United-States-Energy-Star requirements, or 25,000 hours, that is, the optical attenuation of life requirement is less than 30%.