Academic literature on the topic 'Chips limit temperature'
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Journal articles on the topic "Chips limit temperature"
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Cheli, Lapo, and Carlo Carcasci. "Modelling and analysis of a liquid-cooled system for thermal management application of an electronic equipment." E3S Web of Conferences 197 (2020): 10008. http://dx.doi.org/10.1051/e3sconf/202019710008.
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The removal of heat from electronic components, increasingly miniaturized with high power dissipation per unit volume, is a significant industrial problem to be resolved, to avoid failures due to excessive temperatures and besides to maintain performance and operating conditions. This article describes the development of a one-dimensional thermodynamic model to simulate the cooling of electronic chips belonging to inverters for stationary PV solar arrays; these are typically located in very different environments, including deserts or very hot areas, so the operating life of theirs inverter units are strongly affected by changes in external environmental conditions. Results have shown that the model allows, with very low calculation times, to quantify the effects of cooling performance and thermal load of electronics both in design and off-design conditions: the working temperature of the components was monitored as the effectiveness of the main heat exchanger vary with the exposure to the external environment over time, in terms of fouling and as the ambient air temperature changes; in this case a simple control system was simulated to limit the maximum temperature of the chips and the air flow rate of the fans. The thermal performances of two types of glycol-based refrigerant fluids have been compared.
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Kayaba, Yasuhisa, Yuzo Nakamura, Jun Kamada, and Kazuo Kohmura. "New Thin Adhesive for High Density 2.5D Heterogeneous Device Integration with Cu-Cu Hybrid Bonding." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000280–83. http://dx.doi.org/10.4071/2380-4505-2019.1.000280.
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Abstract Heterogeneous integration of logic, memory, and sensor chips on interposers (2.5D) has attracted a lot of attention as a candidate for More-than-Moore technology. For the high performance 2.5D devices, high density integration of chips with narrow spacing and high density interconnections with small pitch bonding electrodes are a key technology. In the current bonding technology, solder micro-bumps (>20 μm in diameter) and non-conductive adhesives have been adopted. There may be some limitations for high density device integration with these technologies because of the protrusion of adhesives around the chips, the thermal sliding at the bonding, and the limit of solder micro-bump minimization. Hybrid bonding with a small Cu electrode (<10 μm in diameter) is a strong candidate for improving advanced device integration technology. Our goal is to develop a new adhesive which gives no protrusion, no thermal sliding, no voids, and high electrical reliability. A spin coating thin adhesive was therefore developed. The new adhesive can be cured at 200 °C. The cured adhesive film has no tackiness and has an optically flat surface. The adhesive film can be temporarily bondable to SiO2 at room temperature. After 200 °C baking, a permanent bonding can be achieved, and there is no degradation of bonding strength and no voids even after 400 °C of baking. For the applicability to the chip-on-wafer process, the adhesive film/Si wafer can be cut into chips by blade dicing without any delamination and without any apparent particles. After bonding the adhesive/Si chip to a bare Si wafer at room temperature, the thermal sliding amount after the thermal compression process (250 °C, 10 min, 1 MPa) was less than 1 μm (under the detection limit) according to optical microscopic measurements. In addition, there was no protrusion of adhesive around the chip corner from SEM. A first trial result for hybrid bonding is also reported.
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MICHEL, MATHIAS, JOCHEN GEMMER, and GÜNTER MAHLER. "MICROSCOPIC QUANTUM MECHANICAL FOUNDATION OF FOURIER'S LAW." International Journal of Modern Physics B 20, no. 29 (November 20, 2006): 4855–83. http://dx.doi.org/10.1142/s0217979206035849.
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Besides the growing interest in old concepts such as temperature and entropy at the nanoscale, theories of relaxation and transport have recently regained a lot of attention. With the electronic circuits and computer chips getting smaller and smaller, a fresh look on the equilibrium and nonequilibrium thermodynamics at small length scales far below the thermodynamic limit, i.e. on the theoretical understanding of original macroscopic processes, e.g. transport of energy, heat, charge, mass, magnetization, etc., should be appropriate. Only from the foundations of a theory its limits of applicability may be inferred. This review tries to give an overview on the background and recent developments in the field of nonequilibrium quantum thermodynamics, focusing on the transport of heat in small quantum systems.
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Mjallal, Ibrahim, Hussein Farhat, Mohammad Hammoud, Samer Ali, Ali AL Shaer, and Ali Assi. "Cooling Performance of Heat Sinks Used in Electronic Devices." MATEC Web of Conferences 171 (2018): 02003. http://dx.doi.org/10.1051/matecconf/201817102003.
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Existing passive cooling solutions limit the short-term thermal output of systems, thereby either limiting instantaneous performance or requiring active cooling solutions. As the temperature of the electronic devices increases, their failure rate increases. That’s why electrical devices should be cooled. Conventional electronic cooling systems usually consist of a metal heat sink coupled to a fan. This paper compares the heat distribution on a heat sink relative to different heat fluxes produced by electronic chips. The benefit of adding a fan is also investigated when high levels of heat generation are expected.
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De Leonardis, Francesco, Richard A. Soref, and Vittorio M. N. Passaro. "Design of an on-Chip Room Temperature Group-IV Quantum Photonic Chem/Bio Interferometric Sensor Based on Parity Detection." Nanomaterials 10, no. 10 (October 7, 2020): 1984. http://dx.doi.org/10.3390/nano10101984.
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We propose and analyze three Si-based room-temperature strip-guided “manufacturable” integrated quantum photonic chem/bio sensor chips operating at wavelengths of 1550 nm, 1330 nm, and 640 nm, respectively. We propose design rules that will achieve super-sensitivity (above the classical limit) by means of mixing between states of coherent light and single-mode squeezed-light. The silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon nitride-on-SiO2-on Si (SiN) platforms have been investigated. Each chip is comprised of photonic building blocks: a race-track resonator, a pump filter, an integrated Mach-Zehnder interferometric chem/bio sensor, and a photonic circuit to perform parity measurements, where our homodyne measurement circuit avoids the use of single-photon-counting detectors and utilizes instead conventional photodetectors. A combination of super-sensitivity with super-resolution is predicted for all three platforms to be used for chem/bio sensing applications.
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Jia, Xiaoning, Joris Roels, Roel Baets, and Gunther Roelkens. "A Miniaturised, Fully Integrated NDIR CO2 Sensor On-Chip." Sensors 21, no. 16 (August 8, 2021): 5347. http://dx.doi.org/10.3390/s21165347.
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In this paper, we present a fully integrated Non-dispersive Infrared (NDIR) CO2 sensor implemented on a silicon chip. The sensor is based on an integrating cylinder with access waveguides. A mid-IR LED is used as the optical source, and two mid-IR photodiodes are used as detectors. The fully integrated sensor is formed by wafer bonding of two silicon substrates. The fabricated sensor was evaluated by performing a CO2 concentration measurement, showing a limit of detection of ∼750 ppm. The cross-sensitivity of the sensor to water vapor was studied both experimentally and numerically. No notable water interference was observed in the experimental characterizations. Numerical simulations showed that the transmission change induced by water vapor absorption is much smaller than the detection limit of the sensor. A qualitative analysis on the long term stability of the sensor revealed that the long term stability of the sensor is subject to the temperature fluctuations in the laboratory. The use of relatively cheap LED and photodiodes bare chips, together with the wafer-level fabrication process of the sensor provides the potential for a low cost, highly miniaturized NDIR CO2 sensor.
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KOTTAPALLI, BALASUBRAHMANYAM, STEPHANIE P. V. NGUYEN, TIM PEREZ, and ASHLEY CUNNINGHAM. "Thermal Inactivation of Salmonella and Listeria monocytogenes in Peanut Butter–Filled Pretzels and Whole Wheat Pita Chips." Journal of Food Protection 82, no. 2 (January 24, 2019): 238–46. http://dx.doi.org/10.4315/0362-028x.jfp-18-231.
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ABSTRACT Recent recalls and outbreaks due to foodborne pathogens in thermally processed low-moisture foods highlight the need for the food industry to validate their thermal process. The purpose of this study was to validate baking as an adequate lethality step in controlling Salmonella and Listeria monocytogenes during the production of peanut butter (PB)–filled pretzels and whole wheat (WW) pita chips. Two dough types, PB-filled pretzel and WW pita chip with varying water activities (0.96 to 0.98), were inoculated (target level, ∼108 to 109 CFU/g) with a multistrain cocktail of Salmonella and L. monocytogenes in separate trials and were baked at 300°F (148.9°C) and 350°F (176.6°C) for 0, 5, 10, 17, 25, and 30 min. Following baking, samples were rapidly cooled and analyzed for Salmonella and L. monocytogenes by the pour plate method. Uninoculated samples were analyzed for total viable aerobic plate count (APC) and Enterobacteriaceae counts. Water activity analysis was also performed. The experiment was replicated three times. Nonlinear regression was used to estimate the baking times required to achieve a minimum of 4- and 5-log reduction in APC, Salmonella, and L. monocytogenes. A 4- and 5-log reduction in APC was predicted following a treatment at 350°F for 3.3 and 5.6 min in WW pita chip product, respectively. Following a treatment of 350°F for 10 and 25 min, Enterobacteriaceae and APC counts were below the detection limit (<1 log CFU/g), respectively, in all of the PB-filled pretzel samples. Salmonella and L. monocytogenes counts decreased with increasing baking time regardless of the temperature used. Significant reductions (≥5-log reduction) were estimated in Salmonella and L. monocytogenes in product baked at 350°F for 15.5 and 17.5 min in WW pita chip dough and PB-filled pretzel dough, respectively. Both pathogens were below the detection limit (<1 log CFU/g) in PB-filled pretzel and WW pita chip products under baking conditions of 350°F for 25 and 30 min, respectively. This study demonstrates that PB-filled pretzel and WW pita chip products, when baked to saleable quality, will not present a public health risk from the standpoint of Salmonella or L. monocytogenes.
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Iemmolo, Rosario, Valentina La Cognata, Giovanna Morello, Maria Guarnaccia, Mariamena Arbitrio, Enrico Alessi, and Sebastiano Cavallaro. "Development of a Pharmacogenetic Lab-on-Chip Assay Based on the In-Check Technology to Screen for Genetic Variations Associated to Adverse Drug Reactions to Common Chemotherapeutic Agents." Biosensors 10, no. 12 (December 9, 2020): 202. http://dx.doi.org/10.3390/bios10120202.
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Background: Antineoplastic agents represent the most common class of drugs causing Adverse Drug Reactions (ADRs). Mutant alleles of genes coding for drug-metabolizing enzymes are the best studied individual risk factors for these ADRs. Although the correlation between genetic polymorphisms and ADRs is well-known, pharmacogenetic tests are limited to centralized laboratories with expensive or dedicated instrumentation used by specialized personnel. Nowadays, DNA chips have overcome the major limitations in terms of sensibility, specificity or small molecular detection, allowing the simultaneous detection of several genetic polymorphisms with time and costs-effective advantages. In this work, we describe the design of a novel silicon-based lab-on-chip assay able to perform low-density and high-resolution multi-assay analysis (amplification and hybridization reactions) on the In-Check platform. Methods: The novel lab-on-chip was used to screen 17 allelic variants of three genes associated with adverse reactions to common chemotherapeutic agents: DPYD (Dihydropyrimidine dehydrogenase), MTHFR (5,10-Methylenetetrahydrofolate reductase) and TPMT (Thiopurine S-methyltransferase). Results: Inter- and intra assay variability were performed to assess the specificity and sensibility of the chip. Linear regression was used to assess the optimal hybridization temperature set at 52 °C (R2 ≈ 0.97). Limit of detection was 50 nM. Conclusions: The high performance in terms of sensibility and specificity of this lab-on-chip supports its further translation to clinical diagnostics, where it may effectively promote precision medicine.
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Nguyen Thi, Huong, Bich Phuong Vu Thi, Long Nguyen Van, Thanh Diu Dao Thi, Linh Chu Manh, and Hung Dang The. "Determination of acrylamide content in processed starchy foods in Hanoi." Heavy metals and arsenic concentrations in water, agricultural soil, and rice in Ngan Son district, Bac Kan province, Vietnam 1, no. 2 (August 8, 2018): 34–39. http://dx.doi.org/10.47866/2615-9252/vjfc.50.
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Acrylamide is a toxic chemical formed in high temperature-processed foods (e.g., Potato snacks, instant noodle, etc.). Previous studied showed that acrylamide is a carcinogenic agent in human and animals. Evaluation of acrylamide contents in some processed starchy foods has been performed in order to investigate the presence of acrylamide in foods in Hanoi. This study is to validate a LC-MS/MS method for determination of acrylamide in food and to determine the acrylamide content in some processed starchy foods available in Hanoi, Vietnam. Samples of potato chips collected from food shops in Hanoi were tested. The acrylamide content was determined by high performance liquid chromatography-mass spectrometry. The method was validated for accuracy, precision, linearity, and recovery. The assay was linear over the entire range of calibration standards i.e., a concentration range from 1 ng/mL to 2500 ng/mL (r2 >0.996). The precision and recoveries were obtained based on the AOAC guidelines. The lower limit of quantification of the analytical method of acrylamide was 24,82 ng/mL. The validated method was successfully applied to determine acrylamide in 28 samples of potato snacks. The content of acrylamide ranged from 58.0 to 1829.6 mg/kg. Acrylamide was detected in all samples, nevertheless, the acrylamide content was lower than that from other studies published in 2009 in Europe.
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Xie, X. L., W. Q. Tao, and Y. L. He. "Numerical Study of Turbulent Heat Transfer and Pressure Drop Characteristics in a Water-Cooled Minichannel Heat Sink." Journal of Electronic Packaging 129, no. 3 (December 13, 2006): 247–55. http://dx.doi.org/10.1115/1.2753887.
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With the rapid development of the Information Technology (IT) industry, the heat flux in integrated circuit (IC) chips cooled by air has almost reached its limit at about 100W∕cm2. Some applications in high technology industries require heat fluxes well beyond such a limitation. Therefore, the search for a more efficient cooling technology becomes one of the bottleneck problems of the further development of the IT industry. The microchannel flow geometry offers a large surface area of heat transfer and a high convective heat transfer coefficient. However, it has been hard to implement because of its very high pressure head required to pump the coolant fluid through the channels. A normal channel size could not give high heat flux, although the pressure drop is very small. A minichannel can be used in a heat sink with quite a high heat flux and a mild pressure loss. A minichannel heat sink with bottom size of 20mm×20mm is analyzed numerically for the single-phase turbulent flow of water as a coolant through small hydraulic diameters. A constant heat flux boundary condition is assumed. The effect of channel dimensions, channel wall thickness, bottom thickness, and inlet velocity on the pressure drop, temperature difference, and maximum allowable heat flux are presented. The results indicate that a narrow and deep channel with thin bottom thickness and relatively thin channel wall thickness results in improved heat transfer performance with a relatively high but acceptable pressure drop. A nearly optimized structure of heat sink is found that can cool a chip with heat flux of 350W∕cm2 at a pumping power of 0.314W.
Dissertations / Theses on the topic "Chips limit temperature"
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Gdhaidh, Farouq A. S. "Heat Transfer Characteristics of Natural Convection within an Enclosure Using Liquid Cooling System." Thesis, University of Bradford, 2015. http://hdl.handle.net/10454/7824.
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In this investigation, a single phase fluid is used to study the coupling between natural convection heat transfer within an enclosure and forced convection through computer covering case to cool the electronic chip. Two working fluids are used (water and air) within a rectangular enclosure and the air flow through the computer case is created by an exhaust fan installed at the back of the computer case. The optimum enclosure size configuration that keeps a maximum temperature of the heat source at a safe temperature level (85℃) is determined. The cooling system is tested for varying values of applied power in the range of 15−40𝑊.
The study is based on both numerical models and experimental observations. The numerical work was developed using the commercial software (ANSYS-Icepak) to simulate the flow and temperature fields for the desktop computer and the cooling system. The numerical simulation has the same physical geometry as those used in the experimental investigations. The experimental work was aimed to gather the details for temperature field and use them in the validation of the numerical prediction.
The results showed that, the cavity size variations influence both the heat transfer process and the maximum temperature. Furthermore, the experimental results
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compared favourably with those obtained numerically, where the maximum deviation in terms of the maximum system temperature, is within 3.5%. Moreover, it is seen that using water as the working fluid within the enclosure is capable of keeping the maximum temperature under 77℃ for a heat source of 40𝑊, which is below the recommended electronic chips temperature of not exceeding 85℃. As a result, the noise and vibration level is reduced. In addition, the proposed cooling system saved about 65% of the CPU fan power.
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Gdhaidh, Farouq Ali S. "Heat transfer characteristics of natural convection within an enclosure using liquid cooling system." Thesis, University of Bradford, 2015. http://hdl.handle.net/10454/7824.
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In this investigation, a single phase fluid is used to study the coupling between natural convection heat transfer within an enclosure and forced convection through computer covering case to cool the electronic chip. Two working fluids are used (water and air) within a rectangular enclosure and the air flow through the computer case is created by an exhaust fan installed at the back of the computer case. The optimum enclosure size configuration that keeps a maximum temperature of the heat source at a safe temperature level (85°C) is determined. The cooling system is tested for varying values of applied power in the range of 15-40W. The study is based on both numerical models and experimental observations. The numerical work was developed using the commercial software (ANSYS-Icepak) to simulate the flow and temperature fields for the desktop computer and the cooling system. The numerical simulation has the same physical geometry as those used in the experimental investigations. The experimental work was aimed to gather the details for temperature field and use them in the validation of the numerical prediction. The results showed that, the cavity size variations influence both the heat transfer process and the maximum temperature. Furthermore, the experimental results ii compared favourably with those obtained numerically, where the maximum deviation in terms of the maximum system temperature, is within 3.5%. Moreover, it is seen that using water as the working fluid within the enclosure is capable of keeping the maximum temperature under 77°C for a heat source of 40W, which is below the recommended electronic chips temperature of not exceeding 85°C. As a result, the noise and vibration level is reduced. In addition, the proposed cooling system saved about 65% of the CPU fan power.
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Gdhaidh, Farouq A. S., Khalid Hussain, and Hong Sheng Qi. "Enhancement of Natural Convection Heat Transfer within Closed Enclosure Using Parallel Fins." 2015. http://hdl.handle.net/10454/7920.
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yesA numerical study of natural convection heat transfer in water filled cavity has been examined in 3-D for single phase liquid cooling system by using an array of parallel plate fins mounted to one wall of a cavity. The heat generated by a heat source represents a computer CPU with dimensions of 37.5∗37.5mm mounted on substrate. A cold plate is used as a heat sink installed on the opposite vertical end of the enclosure. The air flow inside the computer case is created by an exhaust fan. A turbulent air flow is assumed and k-ε model is applied. The fins are installed on the substrate to enhance the heat transfer. The applied power energy range used is between 15 - 40W. In order to determine the thermal behaviour of the cooling system, the effect of the heat input and the number of the parallel plate fins are investigated. The results illustrate that as the fin number increases the maximum heat source temperature decreases. However, when the fin number increases to critical value the temperature start to increase due to the fins are too closely spaced and that cause the obstruction of water flow. The introduction of parallel plate fins reduces the maximum heat source temperature by 10% compared to the case without fins. The cooling system maintains the maximum chip temperature at 64.68°C when the heat input was at 40W that is much lower than the recommended computer chips limit temperature of no more than 85°C and hence the performance of the CPU is enhanced.
Conference papers on the topic "Chips limit temperature"
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Reddy, Sohail R., and George S. Dulikravich. "Inverse Design of Cooling of Electronic Chips Subject to Specified Hot Spot Temperature and Coolant Inlet Temperature." In ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. American Society of Mechanical Engineers, 2015. http://dx.doi.org/10.1115/ipack2015-48346.
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Most methods for designing electronics cooling schemes do not offer the information on what levels of heat fluxes are maximally possible to achieve with the given material, boundary and operating conditions. Here, we offer an answer to this inverse problem posed by the question below. Given a micro pin-fin array cooling with these constraints: - given maximum allowable temperature of the material, - given inlet cooling fluid temperature, - given total pressure loss (pumping power affordable), and - given overall thickness of the entire electronic component, find out the maximum possible average heat flux on the hot surface and find the maximum possible heat flux at the hot spot under the condition that the entire amount of the inputted heat is completely removed by the cooling fluid. This problem was solved using multi-objective constrained optimization and metamodeling for an array of micro pin-fins with circular, airfoil and symmetric convex cross sections that is removing all the heat inputted via uniform background heat flux and by a hot spot. The goal of this effort was to identify a cooling pin-fin shape and scheme that is able to push the maximum allowable heat flux as high as possible without the maximum temperature exceeding the specified limit for the given material. Conjugate heat transfer analysis was performed on each of the randomly created candidate configurations. Response surfaces based on Radial Basis Functions were coupled with a genetic algorithm to arrive at a Pareto frontier of best trade-off solutions. The Pareto optimized configuration indicates the maximum physically possible heat fluxes for specified material and constraints.
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Wang, Peng, F. Patrick McCluskey, and Avram Bar-Cohen. "Isothermalization of an IGBT Power Electronic Chip." In ASME 2010 International Mechanical Engineering Congress and Exposition. ASMEDC, 2010. http://dx.doi.org/10.1115/imece2010-41019.
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Rapid increases in the power ratings and continued miniaturization of power electronic semiconductor devices have pushed chip heat fluxes well beyond the range of conventional thermal management techniques. The heat flux of power electronic chips for hybrid electric vehicles is now at the level of 100 to 150W/cm2 and is projected to increase to 500 W/cm2 in next generation vehicles. Such heat fluxes lead to higher and less uniform IGBT chip temperature, significantly degrading the device performance and system reliability. Maintaining the maximum temperature below a specified limit, while isothermalizing the surface of the chip, have become critical issues for thermal management of power electronics. In this work, a hybrid cooling system design, which combines microchannel liquid cooling and thermoelectric solid-state cooling, is proposed for thermal management of a 10mm × 10mm IGBT chip. The microchannel heat sink is used for global cooling of the chip while the embedded thermo-electric cooler is employed for isothermalization of the chip. A detailed package level 3D thermal model is developed to explore the potential application of this concept, with an attention focused on isothermalization and temperature reduction of IGBT chip associated with variations in thermoelectric cooler sizes, thermoelectric materials, cooling system designs, and trench structures in the DBC substrate. It is found that a thin-film superlattice TEC can deliver a superior cooling performance by eliminating more than 90% of the temperature non-uniformity on 100∼200 W/cm2 IGBT chips.
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Schmidt, Erik Ravn, Jens Christian Clausen, and Fritz Luxhøi. "Large-Scale Handling and Use of Solid Biofuels." In ASME 1998 International Gas Turbine and Aeroengine Congress and Exhibition. American Society of Mechanical Engineers, 1998. http://dx.doi.org/10.1115/98-gt-327.
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Utilising biomass in the CHP production is not without difficulties: the chemical and physical characteristics of the biofuels; corrosion, slagging and fouling; and working environment. An in-situ high-temperature corrosion monitoring test system was successfully developed. Furthermore, activities have been launched to develop a straw pre-processing method separating the aggressive substances from straw. As a result of the gasification projects (straw, coal-straw, wood chips) it was concluded that it is possible to gasify straw — probably for 100% straw and definitely for 50/50 blends, although with some difficulties — and for wood chips deposit formation was a major obstacle. Further R&D is definitely needed, but with the limited international interest the gasification technology seems to have reached a dead end in Denmark. Another focal point is the working environment, where care must be taken to limit any potential health hazards resulting from the handling of long-term stored biofuels.
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Cortez, Margarita L., and Amir Jokar. "Development and Testing of a Prototype Heat Sink Within a Wind Tunnel for Use in an Engineering Course." In ASME 2009 International Mechanical Engineering Congress and Exposition. ASMEDC, 2009. http://dx.doi.org/10.1115/imece2009-12084.
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The purpose of this undergraduate research project was to develop a test section and prototype heat sinks that will be used in an existing electronics cooling wind tunnel for a project in a future Advanced Thermal Systems course. During the course, students will design and manufacture their own prototype heat sinks. Heat sinks are made of highly conductive materials with various geometries and are attached to computer chips to dissipate heat from them to the surroundings. The prototype heat sinks will be manufactured in the school’s facilities which will limit the complexity of the geometry. The purpose is not to design a commercial heat sink. The students will experimentally analyze and simulate the heat transfer that takes place between a computer chip and a heat sink. During the course project the students will also analyze the heat sinks using CFD and compare the results to the experimental data. In this study, an electronics cooling wind tunnel was used to simulate the flow conditions that normally exist in a personal computer. A test section was designed and built in order to measure temperatures at different locations on a prototype heat sink using 18 type-T thermocouples. A data acquisition unit was set up and a Labview program was developed to collect the temperature data as well as the air velocity of the wind tunnel. The recorded data were then transferred to an excel file for further analysis. The objectives of this summer internship project were achieved through testing and analyzing different prototype heat sinks.
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Marbut, Cody J., Mahsa Montazeri, and David Huitink. "Interconnect Fatigue Failure Parameter Isolation for Power Device Reliability Prediction." In ASME 2018 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2018. http://dx.doi.org/10.1115/ipack2018-8275.
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Flip chip (FC) packaging techniques in modern power electronics have enabled increased power density in module performance, but mechanical stresses induced by thermal expansion during inherent operating conditions in the power devices and packages create a need for understanding thermomechanical fatigue mechanisms that lead to reliability concerns. Moreover, in actual use, these mechanical stresses impact the reliable lifetime alongside thermal factors (such as diffusion and microstructural transformation) and other process history effects. This amalgam of damage inducing phenomena make development of a concise association between damage, fatigue, and stress factors difficult to determine. For reliability demonstration under fatigue loading, accelerated life testing (ALT), such as Thermal Cycling (TC), are commonly used in industry; however, long duration and expensive equipment required for TC limit its utility, especially when considering the high cost of wide-bandgap devices and modules, and the limitation of high temperature (> 150°C) testing standards. As a result, alternative test methodologies are needed to provide faster, cheaper, and design integrable reliability determination. In this work, an accelerated test methodology is introduced and designed to simulate these mechanical stresses at isothermal conditions, which is demonstrated using test chips that are analogous to power devices. By stressing these devices in a controlled environment, mechanical stresses become de-coupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device-relevant, flip-chip solder interconnects while monitoring cycles-to-failure (CTF). Also, Finite Element Analysis (FEA) is used to extract various damage metrics of different solder materials (including PbSn37/63, SAC305 and Nano-silver) in both thermal operation and the introduced alternative mechanical testing conditions. In doing so, test protocol translations to common qualification tests (or use condition thermal profiles) can be determined and are validated using the mechanical shear stress testing method. Plastic work density and maximum shear were calculated in the critical solder interconnects for different isothermal mechanical testing temperatures (22°C, 75°C, 100°C and 125°C) and the results are compared with the simulation results of different TC test conditions. This reliability determination with failure parameter isolation allows for improved integration with FEA modeling for a priori reliability prediction during the design process.
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Liu, Jing, Yi-Xin Zhou, Yong-Gang Lv, and Teng Li. "Liquid Metal Based Miniaturized Chip-Cooling Device Driven by Electromagnetic Pump." In ASME 2005 International Mechanical Engineering Congress and Exposition. ASMEDC, 2005. http://dx.doi.org/10.1115/imece2005-80188.
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Conventional methods for thermal management of computer chips are approaching their practical application limit for recently emerging high integrity and high power processors. There is a strong demand to develop alternative approaches to accommodate to the trend of increasing industrial need. In this paper, a prototype of the newly proposed liquid metal based chip cooling device using electromagnetic pump as the flow driving force was fabricated and demonstrated. The technical routes to build up the new miniaturized system were illustrated. Being flowing based, completely electricity-controllable, and almost entirely made of metal, the new cooling device has a rather strong heat dissipation capability compared with that of the conventional forced liquid or air cooling approaches. A series of experiments successfully showed that the EM pump designed and fabricated in this paper is very flexible in driving the circulation flow of the liquid gallium, and the cooling device thus built up can significantly reduce the temperature of a simulating heating module. Further, promising strategies to optimize the present device were suggested and discussed. A series of new issues concerning the heat and fluid transport, and electromagnetic field effect of liquid metal in developing the micro/nano scale cooling devices were raised by interpreting the theoretical models established for characterizing the running behaviors of the present system. The liquid metal based cooling device would find exciting applications in the heat dissipation area where extremely high heat flux and very small geometry were seriously requested.
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Zhang, Xiaokun, Xiao-Dong Xiang, and Yong Xiang. "Approaches Towards the Ultimate Luminous Output Power of Light-Emitting Diodes: Bottlenecks and Remedies." In ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels collocated with the ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2015. http://dx.doi.org/10.1115/icnmm2015-48835.
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Although light-emitting diodes (LEDs) hold great promises for high-efficiency lighting applications, the cost per lumen still poses a challenge for LEDs to fast penetrate into the markets. Increasing the output power per LED chip reduces the number of chips required for a specific luminous flux, thus reducing the cost of LED luminaires. However, it is well known that the luminous output power of LEDs (Pout) cannot be enhanced simply by increasing the injection current density (Jinj) due to efficiency droop. Extensive efforts have been made towards avoiding efficiency droop at high injection current densities (e.g., Jinj > 50 A/cm2). Gardner et al. reported a double-heterostructure LED with an external quantum efficiency (EQE) of 40% at 200 A/cm2. Xie et al. introduced an electron-blocking layer into the LED devices and the EQE peak occurred at 900 A/cm2 approximately. Nevertheless, the EQE is always lower than 100%, excessive heat will accumulate in LEDs at high current densities and increase the junction temperatures, which will damage the device and limit its luminous output power and lifetime. In this paper, the recombination mechanism in the LED active area is analyzed and an analytic relationship between Pout and Jinj is proposed. The calculated results show that the best Pout currently achieved is far lower than its potential value. The temperature dependence of the Pout-Jinj relationship is also calculated and the thermal state of LEDs at high injection current densities predicted. The results demonstrate that LED luminaires with thermal management based on conventional fin-shaped heat sinks suffer from thermal runaway due to excessive heat accumulation before reaching their ultimate output power. The gap between the existing and predicted Pout is mainly due to thermal runaway of LED devices at high injection current densities, instead of efficiency droop. Therefore, the short-term solution of LED luminous output power enhancement should be better cooling of LED modules, such as jet/spray cooling, heat pipe cooling, or 3D embedded two-phase cooling. Long-term solutions continue to focus on reducing the efficiency droop with improved LED device structures and advanced materials.
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Qian, Zhengfang, Xiaohua Wu, and Joe Tomase. "Deterministic and Statistical Reliability of Surface Mount Components." In ASME 2002 International Mechanical Engineering Congress and Exposition. ASMEDC, 2002. http://dx.doi.org/10.1115/imece2002-39633.
Full textAbstract:
This paper is to investigate both deterministic and statistical aspects of thermal reliability of solder joints of surface mount leadless components (SMLCs). The emphasis is on bridging deterministic with statistical reliability prediction. A reliable methodology has been established to predict the failure rate at accelerated life tests (ALTs) and field failed rate in terms of key statistical parameters of design, environmental condition, and material selection due to the uncertainty from the component manufacturing/assembly, temperature profile of ALTs and field environmental conditions, and material property. Analytical equations and solutions of inelastic strain range and fatigue life for simplified joint geometry have been developed from deterministic approach. They are furthermore utilized to obtain the failure functions of thermal fatigue caused by both crack initiation and crack propagation from multivariable distributions. First Order Reliability Model (FORM) has been extended by combining Taylor series in technique with central limit theorem (CLT). An important outcome is that the statistical fatigue life is a lognormal distribution in which its parameters can be analytically evaluated by the approximate method with satisfactory accuracy for small COVs (COV=mean/deviation) of random variables (RVs). Specifically, SMLCs have been investigated on inelastic strain distribution, fatigue life distribution, failure and reliability functions, and failure rate prediction based on the statistical distributions of the solder joint height, solder paste size, temperature profile, and the experimental property of the eutectic solder alloy. Moreover, the component failure under two failure modes, i.e., both crack initiation and crack propagation, has been performed to illustrate the significance of failure criteria selection and address the data collection in field. Additionally, the simulation of realistic solder joint geometry and damage-based failure processes will be also presented. The developed methodology can be directly used for the board-level reliability prediction of advanced electronic packages such as BGAs, CSPs, QFPs, and Flip-chips.
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Zhang, Conan, and Carlos H. Hidrovo. "Investigation of Nanopillar Wicking Capabilities for Heat Pipes Applications." In ASME 2009 Second International Conference on Micro/Nanoscale Heat and Mass Transfer. ASMEDC, 2009. http://dx.doi.org/10.1115/mnhmt2009-18484.
Full textAbstract:
Since Moore’s prediction in 1965, transistor count density on computer chips has grown exponentially and roadmaps for future industry growth still project exponential development for the next decade. With higher transistor densities, greater heat flux dissipation is required in order for performance to keep par with chip development. However, it is theorized that current cooling systems would not be able to cope with heat fluxes of future computer chips. Microchip heat management systems can be either active or passive. Active systems require an external driving component that increases the system’s complexity and ultimately power consumption. Heat pipes are passive fluidic systems, which are more robust and easier to implement than their active counterparts. Recirculation of the coolant in a heat pipe is done passively by means of a wicking structure that induces capillary flow from the condenser to the evaporator. However, there are many limiting factors associated with heat pipes based on the wick dimensions, fluid selection and orientation. At CPU chip operating temperatures the most significant limitation is the capillary limit. This limitation must be addressed in order to meet future computer chip heat dissipation requirements. In order to find an optimal geometry that would maximize the capillary flow, a theoretical model was developed using a rectangular pillar array. Surface tension forces induce a capillary flow that is opposed by viscous stresses from the pillars. Due to the regular and well-defined geometry of the pillar array, an ab initio approach can be used to model this flow, rather than resorting to Darcy’s flow and empirical permeability correlations. Predicted values of maximum flow rate were obtained from this theoretical model. This model and its results are directly applicable to carbon nanotube (CNT) and nanowire (NW) based wick structures. To validate the merit of nanostructure wicks for use in heat pipes, experimental data was collected to show the capillary limits of various nanowicks. The capillary limit of a wick was associated with the heat flux at which the wick cannot sustain the fluid flow necessary for heat removal and burnout occurs. When a baseline wick was experimentally compared to a nanowick, it was found that due to the difference in thickness of the wicks, the baseline wick provided higher flow rates. However, when the data were normalized to produce velocity values, the nanowick was found to have a higher velocity than the baseline wicks.
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Gurrum, Siva, Shivesh Suman, Yogendra Joshi, and Andrei Fedorov. "Thermal Issues in Next Generation Integrated Circuits." In ASME 2003 International Electronic Packaging Technical Conference and Exhibition. ASMEDC, 2003. http://dx.doi.org/10.1115/ipack2003-35309.
Full textAbstract:
Effective cooling of electronic chips is crucial for reliability and performance of electronic devices. Steadily increasing power dissipation in both devices and interconnects motivate the investigation of chip-centric thermal management as opposed to traditional package-centric solutions. In this work, we explore the fundamental limits for heat removal from a model chip for various configurations. Temperature rise when the chip is embedded in an infinite solid is computed for different thermal conductivities of the medium to pin down the best that can be achieved with conduction based thermal management. Next, a chip attached to a spreader plate with convection boundary condition on top was considered. A brief review of interface thermal resistances and partitioning of overall thermal resistance is presented for current generation microprocessors. Based upon the analysis it is concluded that far-term cooling solutions might necessitate integration with chip/interconnect-stack to meet the challenges. In addition, this would require concurrent thermal and electrical design/fabrication of future high-performance microprocessors.