Relevant bibliographies by topics / ChipScope

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'ChipScope'

Author: Grafiati
Published: 4 June 2021
Last updated: 4 February 2022

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Journal articles on the topic "ChipScope"

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G.Shanthi, G. Shanthi. "CHIPSCOPE Implementation of CRC circuit architecture." IOSR journal of VLSI and Signal Processing 2, no. 1 (2013): 07–14. http://dx.doi.org/10.9790/4200-0210714.

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Diéguez, Angel, Steffen Bornemann, Katarzyna Kluczyk-Korch, Kateryna Trofymchuk, Viktorija Glembockyte, and Stefan Schrittwieser. "ChipScope Symposium: Novel Approaches for a Chip-Sized Optical Microscope." Proceedings 56, no. 1 (December 9, 2020): 5. http://dx.doi.org/10.3390/proceedings2020056005.

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In the Chipscope project funded by the EU, a completely new strategy towards optical microscopy is explored by a team of researchers from different European institutions. In this workshop, the different researchers of the project will explain the last advances obtained in the project, presenting the microscopes, how light emission is produced, and the detection principles and simulations.
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Divakaran, Ruckmani, Srinivas Babu N, Shashi Kiran S, and Byrareddy H.C. "IMPLEMENTATION AND VERIFICATION OF RISC PROCESSOR ON FPGA USING CHIPSCOPE PRO TOOL." International Journal of Current Engineering and Scientific Research 6, no. 6 (June 2019): 59–65. http://dx.doi.org/10.21276/ijcesr.2019.6.6.12.

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Leander, Kevin M. "ChipScope: Actually, That Funny Way of Looking at it Works Pretty Well." E-Learning and Digital Media 11, no. 5 (January 2014): 471–74. http://dx.doi.org/10.2304/elea.2014.11.5.471.

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Qin, Peng, Hao Lu, Zhi Ye Jiang, Jin Liang Bai, Lu Gao, and Gang Meng. "Design and Test of High Speed Digitization Sampling Circuit Based on FPGA." Applied Mechanics and Materials 482 (December 2013): 386–89. http://dx.doi.org/10.4028/www.scientific.net/amm.482.386.

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To sample wideband IF signal with large amounts of data, a high-speed data acquisition program is presented. The program focus on circuit design, issues that need attention, and high-speed sampling signal deceleration strategy. The 2.4GHz rate sampling data acquisition, reception and demux are completed with ADC083000 and Field-Programmable Gate Array (FPGA). At last, a result of sampling with the converter is offered by chipscope software. The result verified ADC083000 has an excellent performance with more than 6.5 bit ENOB and good phase coherence. In engineering practice, the design has been used and has good performance.
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AV, Shruthi, Electa Alice, and Mohammed Bilal. "Low Power VLSI Design and Implementation of Area-Optimized 256-bit AEStandard for Real Time Images on Vertex 5." International Journal of Reconfigurable and Embedded Systems (IJRES) 2, no. 2 (July 1, 2013): 83. http://dx.doi.org/10.11591/ijres.v2.i2.pp83-88.

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A new Vertex6-chipscope based implementation scheme of the AES-256 (Advanced Encryption Standard, with 256-bit key) encryption and decryption algorithm is proposed in this paper. For maintaining the speed of encryption and decryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 256-bit plaintext and the 256- bit initial key, as well as the 256-bit output of cipher-text, are all divided into four 32-bit consecutive units respectively controlled by the clock. In this novel work, substantial improvement in performance in terms of area, power and dynamic speed has been obtained.
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Wang, Jiang Wei, Mu Yan Ma, and Jun Min Leng. "Design of Real-Time Image Collecting Module Based on FPGA." Advanced Materials Research 532-533 (June 2012): 1095–99. http://dx.doi.org/10.4028/www.scientific.net/amr.532-533.1095.

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A new pixel collecting interface board based on FPGA is designed, it is a part of conveyer belt’s fault detection device. The previous system’s controller chip CPLD is replaced by FPGA, the memory FIFO chips are replaced by SRAM, the chip CY7C68013 is chosen as the USB 2.0 controller and works in Slave FIFO transmission mode. The firmware program and application program are compiled to transmit data. The Chipscope Pro Tools are used in the system to debug online, and the correctness of data transmission can be analyzed and verified. The experimental results demonstrate that the new pixel collecting interface board has the advantage of high-speed data acquisition, and can transmit data in real time and correctly. It also has a good scalability and can be used into other high-speed acquisition systems.
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Muhammad, A. B., Denny Darlis, and Arfianto Fahmi. "Design and Realization of Digital Modulator BPSK, QPSK and 16-QAM on FPGA." Journal of Measurements, Electronics, Communications, and Systems 2, no. 1 (December 31, 2016): 1. http://dx.doi.org/10.25124/jmecs.v2i1.1482.

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Innovations in the field of wireless communication are growing very rapidly in line with the behavior of modern societies that have high mobility, need of the flexible services, easy access, and high speed data transfer to facilitate any activities of its users. The needs of every user of any variety are more than just voice, video, data transfer, up to a demanding streaming multimedia capabilities and reliability of the communication system used. One of the factors that affect the quality and speed of data transfer in wireless communications is modulation. The development of technological modulation allows data transfer rate to become faster, more resistant to noise, and have high security (encryption) in order to secure data sent over the lead. The implementation of digital modulator PSK (Phase Shift Keying Modulation) and QAM (Quadrature Amplitude Modulation) on FPGA is designed to simplify the design of a hardware by representing the input which is prepared by using the VHDL programming language. The input will be programmed by logic gates contained in the FPGA into a circuit that functions as a digital modulator. This device can map the input bits into a modulator output that has been mapped in accordance with the coordinates of the constellation. The expected results of the implementation are three types of digital modulator, namely: BPSK, QPSK and 16-QAM to be implemented on FPGA Xilinx Spartan-6 XC6SLX45 CSG324C; modulation type to be used can be selected by entering input on the programs implemented in the FPGA. In the design used input from laptop devices with UART interface and data types for input is ASCII 8 bit for later analysis simulation results modulation of the input to each modulator using Modelsim for simulation design and Chipscope for simulation system design implemented in the FPGA.
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Murthy, C. Srinivasa, and K. Sridevi. "Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications." Circuit World 47, no. 3 (June 8, 2021): 252–61. http://dx.doi.org/10.1108/cw-11-2020-0332.

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Purpose In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters. Design/methodology/approach The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer. Findings Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively. Originality/value The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.
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Castro, Jasmine O., Shwathy Ramesan, Amgad R. Rezk, and Leslie Y. Yeo. "Continuous tuneable droplet ejection via pulsed surface acoustic wave jetting." Soft Matter 14, no. 28 (2018): 5721–27. http://dx.doi.org/10.1039/c7sm02534c.

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Dissertations / Theses on the topic "ChipScope"

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Bernspång, Johan. "Interfacing an external Ethernet MAC/PHY to a MicroBlaze system on a Virtex-II FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2412.

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Due to the development towards more dense programmable devices (FPGAs) it is today possible to fit a complete embedded system including microprocessor, bus architecture, memory, and custom peripherals onto one single reprogrammable chip, it is called a System-on-Chip (SoC). The custom peripherals can be of literally any nature from I/O interfaces to Ethernet Media Access Controllers. The latter core, however, usually consumes a big part of a good sized FPGA. The purpose of this thesis is to explore the possibilities of interfacing an FPGA based Microblaze system to an off-chip Ethernet MAC/PHY. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price. This work includes evaluation of different available Ethernet devices, decision of interface technology, implementation of the interface, testing and verification. Since the ISA interface still is a common interface to Ethernet MAC devices a bus bridge is implemented linking the internal On-Chip Peripheral Bus (OPB) with the ISA bus. Due to delivery delays of the selected Ethernet chip a small on-chip ISA peripheral was constructed to provide a tool for the testing and verification of the bus bridge. The main result of this work is an OPB to ISA bus bridge core. The bridge was determined to work according to specification, and with this report at hand the connection of the Ethernet chip to the system should be quite straightforward.

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Ljungberg, Jan. "SYSTEM ON CHIP : Fördelar i konstruktion med system on chip i förhållande till fristående FPGA och processor." Thesis, Tekniska Högskolan, Högskolan i Jönköping, JTH, Data- och elektroteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-28263.

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In this exam project the investigation has been done to determine, which profits that can be made by switching an internal bus between two chips, one FPGA and a processor, to an internal bus implemented on only one chip, System on Chip. The work is based on measurements made in real time in Xilinx’s development tools on different buses, AXI4 and AXI4-Light connected to AXI3. The port that is used is FPGA’s own GP-port. Besides measuring the time of transactions also physical aspects have been investigated in this project: space, costs and time. Based on those criteria a comparison to the original construction was made to determine which benefits that can be achieved. The work has shown a number of results that are in comparison with the original construction. The System on Chip has turned out to be a better solution in most cases. When using the AXI4-Light-bus the benefits were not as obvious. Cosmic radiation, temperature or humidity are beyond the scope of this investigation. In the work the hypothetic deductive method has been used to prove that the System on Chip is faster than the original design. In this method three statements must be set up against each other; one statement that ought to be true, one statement that is a contradiction and a conclusion of what is proved. The pre-study pointed out that the System on Chip is a faster solution than the original construction. The method is useful since it proves that the pre-study is comparable to the measured results.
I detta examensarbete har undersökningar gjorts för att fastställa vilka vinster som går att göra genom att byta en internbuss mellan två chip, en FPGA och en processor, mot en intern buss implementerat på ett enda chip, System on Chip. Arbetet bygger på mätningar gjorda i realtid i Xilinx utvecklingsverktyg på olika bussar, AXI4 och AXI4‑Lite som är kopplade internt mot AXI3. Den port som används är FPGAs egen GP‑port. Förutom att mäta överföringshastigheterna, har även fysiska aspekter som utrymme, kostnader och utvecklingstid undersökts. Utifrån dessa kriterier har en jämförelse gjorts med den befintliga konstruktionen för att fastställa vilka vinster som går att uppnå. Arbetet har resulterat i ett antal resultat som är ställda mot de förutsättningar som fanns i den ursprungliga lösningen. I de flesta fall visar resultatet att ett System on Chip är en bättre lösning. De fall som var tveksamma var vid viss typ av överföring med AXI4‑Lite bussen. I arbetet har inte undersökning av kosmisk strålning, temperatur eller luftfuktighet betraktas. I arbetet med att försöka att bevisa att ett System on Chip är snabbare än den ursprungliga uppsättningen har utvecklingsmetoden hypotetisk deduktiv använts. Denna metod bygger på att man från början sätter upp ett påstående, som man förutsätter är sant, följt av en konjunktion, som inte får inträffa, för att slutligen dra en slutsats, som konstaterar fakta. Eftersom fakta som lästes in i början av arbetet pekade på att ett System on Chip var en snabbare och billigare lösning kändes metoden användbar. Under arbetets gång har det visat sig vara en bra metod som också ger ett resultat där sannolikheten för att det är en snabbare lösning ökar. Däremot säger inte metoden att det är helt säkert att den i alla situationer är bättre, vilket kan ändras om man använder andra förutsättningar eller tar med andra aspekter.
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Books on the topic "ChipScope"

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McAlpine, Kenneth B. Netlabels and Real-World Festivals. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780190496098.003.0009.

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This chapter explores how the infrastructure of the established music industry—the routes to market and, just as significantly, the gatekeepers who control them—emerged spontaneously as part of the chipscene, albeit with a noncommercial ethos, giving rise to an economy built on community esteem and authenticity. The chapter begins by exploring how diskmags and archives provided a way for fans to collect and share the music that they loved. Gathering together a complete collection of the video game music that fans loved—a common feature of fandom—and providing software players and emulators that allowed the music to be played on modern computer platforms enabled 8-bit music to be collected and shared. From these archives grew netlabels, online record labels that publish and distribute new music, and festivals, most significantly the Blip festival, which has grown into a major international event, with shows in North America, Europe, Japan, and Australia.
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McAlpine, Kenneth B. Fakebit, Fans, and 8-Bit Covers. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780190496098.003.0010.

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Musicians have for centuries reinterpreted and recontextualized the music of other songwriters, composers and performers, and this chapter explores how this musical reinvention has manifested itself as part of the contemporary chipscene. The chapter explores how in the early days of 8-bit gaming, game soundtracks often borrowed heavily from the popular electronic music of the time, often featuring arrangements of Jarre, Vangelis, and Yellow Magic Orchestra. The chapter also explores how, today, there are bands who take those classic video game themes and perform them as live five- or six-piece rock bands. It discusses how social media has provided a platform for the performance and distribution of video game covers and examines how, as musicians have demanded simple, self-contained production environments to develop chip music, new hardware and software synthesizers have been developed to meet that need, an approach that is known as fakebit and that highlights the value that different participants in the scene place on authenticity.
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Book chapters on the topic "ChipScope"

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Shirol, Suhas B., S. Ramakrishna, and Rajashekar B. Shettar. "Design and Implementation of Adders and Multiplier in FPGA Using ChipScope: A Performance Improvement." In Information and Communication Technology for Competitive Strategies, 11–19. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-0586-3_2.

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Conference papers on the topic "ChipScope"

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Arshak, Khalil, Essa Jafer, and Christian Ibala. "Testing FPGA based digital system using XILINX ChipScope logic analyzer." In 2006 29th International Spring Seminar on Electronics Technology. IEEE, 2006. http://dx.doi.org/10.1109/isse.2006.365129.

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Kippenberg, Tobias J. "Chipscale soliton microcombs." In CLEO: Science and Innovations. Washington, D.C.: OSA, 2019. http://dx.doi.org/10.1364/cleo_si.2019.sm2n.1.

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Boles, T., J. Brogle, and J. Goodrich. "Chipscale mmW Switches." In 2007 Asia-Pacific Microwave Conference - (APMC 2007). IEEE, 2007. http://dx.doi.org/10.1109/apmc.2007.4555128.

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Shih, Ta-Ming, Chris H. Sarantos, Susan M. Haynes, and John E. Heebner. "Ultrafast, Chipscale, Optically-Gated Optical Sampler." In Conference on Lasers and Electro-Optics. Washington, D.C.: OSA, 2010. http://dx.doi.org/10.1364/cleo.2010.cwh1.

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Brongersma, Mark L., Rashid Zia, Jon Schuler, and Anu Chandran. "Plasmonics – The New Wave of Chipscale Technologies!?" In Nanophotonics. Washington, D.C.: OSA, 2006. http://dx.doi.org/10.1364/nano.2006.nfa1.

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Boles, T., J. Brogle, and A. Rozbicki. "HMIC 3-D chipscale, surface mount devices." In 2011 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS). IEEE, 2011. http://dx.doi.org/10.1109/comcas.2011.6105782.

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Hoople, J., J. Kuo, Mohamed Abdel-moneum, and A. Lal. "Chipscale GHz ultrasonic channels for fingerprint scanning." In 2015 IEEE International Ultrasonics Symposium (IUS). IEEE, 2015. http://dx.doi.org/10.1109/ultsym.2015.0027.

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Hoople, J., J. Kuo, J. Soon Bo Woon, N. Singh, and A. Lal. "Optimized response of AlN stack for chipscale GHz ultrasonics." In 2015 IEEE International Ultrasonics Symposium (IUS). IEEE, 2015. http://dx.doi.org/10.1109/ultsym.2015.0357.

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Hu, Juejun, J. David Musgraves, Nathan Carlie, Bogdan Zdyrko, Igor Luzinov, Anu Agarwal, Kathleen Richardson, and Lionel Kimerling. "Development of chipscale chalcogenide glass based infrared chemical sensors." In SPIE OPTO, edited by Manijeh Razeghi, Rengarajan Sudharsanan, and Gail J. Brown. SPIE, 2011. http://dx.doi.org/10.1117/12.871399.

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Kippenberg, T. J., and V. Brasch. "Chipscale Microresonator-based Frequency Combs using Soliton Cherenkov Radiation." In Mid-Infrared Coherent Sources. Washington, D.C.: OSA, 2016. http://dx.doi.org/10.1364/mics.2016.mm1c.1.

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