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Whittaker, Philip. "On board signal analysis using novel analogue/digital signal processing techniques on low earth orbit mini/microsatellites." Thesis, University of Surrey, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.343484.
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Fabris, Eric Ericson. "A Modular and digitally programmable interface based on band-pass sigma-delta modulator for mixed-signal systems-on-chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/6226.
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O foco desta tese é a descrição e validação de uma arquitetura de interface para processamento de sinais analógicos para SOC de sinais mistos. A abordagem proposta apresenta a possibilidade de cobertura de uma larga faixa de freqüências com performance praticamente constante associada a uma estrutura digital de programação. A premissa é usar uma célula analógica fixa e promover a configuração da aplicação no domínio digital, levando a uma arquitetura de interface de sinais mistos. O emprego de um bloco analógico fixo busca eliminar a perda inerente de performance decorrente da própria estrutura de programação em circuitos reconfiguráveis analógicos. A emprego da programação no domínio digital abre espaço para usos da vasta gama de ferramentas disponíveis para o projeto em alto nível de abstração, simulação e síntese automática para implementar a aplicação alvo com excelente predição do desempenho final. A abordagem proposta baseia-se no conceito de translação em freqüência (mixagem) do sinal de entrada seguida pela sua conversão para o domínio ΣΔ. A estrutura de processamento possibilita o emprego de um bloco analógico constante, e também, um processamento uniforme de sinais de entrada indo de DC até altas freqüências. A aplicação é configurada no domínio ΣΔ onde a performance pode ser predita de acordo com as especificações alvo. Objetivando a exploração do espaço de projeto foi desenvolvido o modelo de performance teórico e de simulação. Os modelos desenvolvidos auxiliam no também no projeto físico da interface proposta. Objetivando, tanto a validação dos modelos propostos, bem como o desenvolvimento de aplicações, foram construídos dois protótipos. São apresentados os usos da interface como um ADC paramétrico multi-banda e como um multiplicador e um somador de sinais analógicos. É proposta também uma arquitetura para uma interface analógica multi-canal. Os resultados experimentais empregados para a caracterização da interface proposta suportam as vantagens da mesma.<br>The focus of this thesis is to discuss the development and modeling of an interface architecture to be employed for interfacing analog signals in mixed-signal SOC. We claim that the approach that is going to be presented is able to achieve wide frequency range, and covers a large range of applications with constant performance, allied to digital configuration compatibility. Our primary assumptions are to use a fixed analog block and to promote application configurability in the digital domain, which leads to a mixed-signal interface. The use of a fixed analog block avoids the performance loss common to configurable analog blocks. The usage of configurability on the digital domain makes possible the use of all existing tools for high level design, simulation and synthesis to implement the target application, with very good performance prediction. The proposed approach utilizes the concept of frequency translation (mixing) of the input signal followed by its conversion to the ΣΔ domain, which makes possible the use of a fairly constant analog block, and also, a uniform treatment of input signal from DC to high frequencies. The programmability is performed in the ΣΔ digital domain where performance can be closely achieved according to application specification. The interface performance theoretical and simulation model are developed for design space exploration and for physical design support. Two prototypes are built and characterized to validate the proposed model and to implement some application examples. The usage of this interface as a multi-band parametric ADC and as a two channels analog multiplier and adder are shown. The multi-channel analog interface architecture is also presented. The characterization measurements support the main advantages of the approach proposed.
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Rahman, M. S. "An investigation into spectral analysis using a chirp signal matched filter." Thesis, University of Manchester, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.312219.
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Kashyap, Aditya. "Computationally Efficient Methods for Detection and Localization of a Chirp Signal." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/87586.
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In this thesis, a computationally efficient method for detecting a whistle and capturing it using a 4 microphone array is proposed. Furthermore, methods are developed to efficiently process the data captured from all the microphones to estimate the direction of the sound source. The accuracy, the shortcoming and the constraints of the method proposed are also discussed. There is an emphasis placed on being computationally efficient so that the methods may be implemented on a low cost microcontroller and be used to provide a heading to an Unmanned Ground Vehicle.<br>MS<br>As humans, we rely on our sense of hearing to help us interact with the outside world. It helps us to listen not just to other people but also for sounds that maybe a warning for us. It can often be the first warning we get of an impending danger as we might hear a predator before we see it or we might hear a car brake and slip before we turn to look at it. However, it is not merely the ability to hear a sound that makes hearing so useful. It is the fact that we can tell which direction the sound is coming from that makes it so important. That is what allows us to know which direction to turn towards to respond to someone or from which direction the sound warning us of danger is coming. We may not be able to pinpoint the location of the source with complete accuracy but we can discern the general heading. It was this idea that inspired this research work. We wanted to be capable of estimating where a sound is coming from while being computationally efficient so that it may be implemented in real time with the help of a low cost microcontroller. This would then be used to provide a heading to an Unmanned Ground Vehicle while keeping the costs down.
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Shi, Rui. "Off-chip wire distribution and signal analysis." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2008. http://wwwlib.umi.com/cr/ucsd/fullcit?p3336647.
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Thesis (Ph. D.)--University of California, San Diego, 2008.<br>Title from first page of PDF file (viewed Jan. 6, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 91-93).
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Hollis, Timothy M. "Circuit and modeling solutions for high-speed chip-to-chip communication /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd1721.pdf.
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Zoh, Brice. "An Underwater Channel Model and Chirp Slope Keying Modulation Scheme Performance." ScholarWorks@UNO, 2010. http://scholarworks.uno.edu/td/1263.
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Chirp-Slope Keying (CSK) is a new and innovative digital modulation scheme for underwater data transmission. The underwater environment brings up several challenges to the manufacturing and operation of communication systems. This thesis shows through analysis and simulations the effectiveness of Chirp-Slope Keying (CSK) in providing a satisfying performance in underwater communication. The experiment consists of modulating a chirp slope by binary numbers (representing our data). '0' is represented by a linear- down chirp and '1' is represented by a linear-up chirp. The received data is first processed by a correlator receiver. Then, the detection of either binary symbol is obtained by the comparison to a threshold. Simulation results for numerous signal-to-noise ratios show that CSK provides satisfying performance for underwater data transmission. The Mississippi gulf coast shallow water Data collected from the National Oceanic and Atmospheric Administration (NOAA), (see appendix), allow us to accurately generate a laboratory model for the channel of interest.
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Xia, Tian. "On-chip timing measurement /." View online ; access limited to URI, 2003. http://0-wwwlib.umi.com.helin.uri.edu/dissertations/dlnow/3112132.
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El, Sayed Atika. "Echographie ultrasonore à émission de type "Chirp" et traitement par analyse spectrale numérique." Lyon 1, 1987. http://www.theses.fr/1987LYO19018.
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Karasu, Mücahit. "AR parameter estimation using TMS320C30 digital signal processor chip /." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA305733.
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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1995.<br>Thesis advisor(s): M.K. Shields, Murali Tummala. "December 1995." Includes bibliographical references. Also available online.
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Ahmad, Shakeel. "Stimuli Generation Techniques for On-Chip Mixed-Signal Test." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-61712.
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With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer. Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author. Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques. A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.
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Li, Qing. "Densely integrated photonic structures for on-chip signal processing." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/49035.
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Microelectronics has enjoyed great success in the past century. As the technology node progresses, the complementary metal-oxide-semiconductor scaling has already reached a wall, and serious challenges in high-bandwidth interconnects and fast-speed signal processing arise. The incorporation of photonics to microelectronics provides potential solutions. The theme of this thesis is focused on the novel applications of travelling-wave microresonators such as microdisks and microrings for the on-chip optical interconnects and signal processing. Challenges arising from these applications including theoretical and experimental ones are addressed. On the theoretical aspect, a modified version of coupled mode theory is offered for the TM-polarization in high index contrast material systems. Through numerical comparisons, it is shown that our modified coupled mode theory is more accurate than all the existing ones. The coupling-induced phase responses are also studied, which is of critical importance to coupled-resonator structures. Different coupling structures are studied by a customized numerical code, revealing that the phase response of symmetric couplers with the symmetry about the wave propagating direction can be simply estimated while the one of asymmetric couplers is more complicated. Mode splitting and scattering loss, which are two important features commonly observed in the spectrum of high-Q microresonators, are also investigated. Our review of the existing analytical approaches shows that they have only achieved partial success. Especially, different models have been proposed for several distinct regimes and cannot be reconciled. In this thesis, a unified approach is developed for the general case to achieve a complete understanding of these two effects. On the experimental aspect, we first develop a new fabrication recipe with a focus on the accurate dimensional control and low-loss performance. HSQ is employed as the electron-beam resist, and the lithography and plasma etching steps are both optimized to achieve vertical and smooth sidewalls. A third-order temperature-insensitive coupled-resonator filter is designed and demonstrated in the silicon-on-insulator (SOI) platform, which serves as a critical building block element in terabit/s on-chip networks. Two design challenges, i.e., a broadband flat-band response and a temperature-insensitive design, are coherently addressed by employing the redundant bandwidth of the filter channel caused by the dispersion as thermal guard band. As a result, the filter can accommodate 21 WDM channels with a data rate up to 100 gigabit/s per wavelength channel, while providing a sufficient thermal guard band to tolerate more than ±15°C temperature fluctuations in the on-chip environment. In this thesis, high-Q microdisk resonators are also proposed to be used as low-loss delay lines for narrowband filters. Pulley coupling scheme is used to selectively couple to one of the radial modes of the microdisk and also to achieve a strong coupling. A first-order tunable narrowband filter based on the microdisk-based delay line is experimentally demonstrated in an SOI platform, which shows a tunable bandwidth from 4.1 GHz to 0.47 GHz with an overall size of 0.05 mm². Finally, to address the challenges for the resonator-based delay lines encountered in the SOI platform, we propose to vertically integrate silicon nitride to the SOI platform, which can potentially have significantly lower propagation loss and higher power handling capability. High-Q silicon nitride microresonators are demonstrated; especially, microresonators with a 16 million intrinsic Q and a moderate size of 240 µm radius are realized, which is one order of magnitude improvement compared to what can be achieved in the SOI platform using the same fabrication technology. We have also successfully grown silicon nitride on top of SOI and a good coupling has been achieved between the silicon nitride and the silicon layers.
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Karasu, Mucahit. "AR parameter estimation using TMS320C30 digital signal processor chip." Thesis, Monterey, California. Naval Postgraduate School, 1995. http://hdl.handle.net/10945/31332.
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Autoregressive analysis is used in modern signal processing applications for modeling and estimation of random signals. High speed digital signal processors with advanced architecture and special digital signal processing instructions, mostly compiled in C language, can be used in these applications to achieve realtime performance. A commercially available digital signal processor has been used in this work to estimate the AR parameters and power spectral density from the given input data by using the Levinson, Burg and Schur algorithms. This work produced a library file that contains the object files of the AR parameter estimation algorithms. The time required in terms of the cycle counts to execute each algorithm is listed for different data lengths and model orders.
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Ravuru, Anusha. "Characterization of Ecg Signal Using Programmable System on Chip." Thesis, University of North Texas, 2012. https://digital.library.unt.edu/ark:/67531/metadc177242/.
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Electrocardiography (ECG) monitor is a medical device for recording the electrical activities of the heart using electrodes placed on the body. There are many ECG monitors in the market but it is essential to find the accuracy with which they generate results. Accuracy depends on the processing of the ECG signal which contains several noises and the algorithms used for detecting peaks. Based on these peaks the abnormality in the functioning of the heart can be estimated. Hence this thesis characterizes the ECG signal which helps to detect the abnormalities and determine the accuracy of the system.
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Balasubramanian, Karthikeyan. "Reconfigurable System-on-Chip Architecture for Neural Signal Processing." Diss., Temple University Libraries, 2011. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/144255.
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Electrical Engineering<br>Ph.D.<br>Analyzing the brain's behavior in terms of its neuronal activity is the fundamental purpose of Brain-Machine Interfaces (BMIs). Neuronal activity is often assumed to be encoded in the rate of neuronal action potential spikes. Successful performance of a BMI system is tied to the efficiency of its individual processing elements such as spike detection, sorting and decoding. To achieve reliable operation, BMIs are equipped with hundreds of electrodes at the neural interface. While a single electrode/tetrode communicates with up to four neurons at a given instant of time, a typical interface communicates with an ensemble of hundreds or even thousands of neurons. However, translation of these signals (data) into usable information for real-time BMIs is bottlenecked due to the lack of efficient real-time algorithms and real-time hardware that can handle massively parallel channels of neural data. The research presented here addresses this issue by developing real-time neural processing algorithms that can be implemented in reconfigurable hardware and thus, can be scaled to handle thousands of channels in parallel. The developed reconfigurable system serves as an evaluation platform for investigating the fundamental design tradeoffs in allocating finite hardware resources for a reliable BMI. In this work, the generic architectural layout needed to process neural signals in a massive scale is discussed. A System-on-Chip design with embedded system architecture is presented for FPGA hardware realization that features (a) scalability (b) reconfigurability, and (c) real-time operability. A prototype design incorporating a dual processor system and essential neural signal processing routines such as real-time spike detection and sorting is presented. Two kinds of spike detectors, a simple threshold-based and non-linear energy operator-based, were implemented. To achieve real-time spike sorting, a fuzzy logic-based spike sorter was developed and synthesized in the hardware. Furthermore, a real-time kernel to monitor the high-level interactions of the system was implemented. The entire system was realized in a platform FPGA (Xilinx Virtex-5 LX110T). The system was tested using extracellular neural recordings from three different animals, a owl monkey, a macaque and a rat. Operational performance of the system is demonstrated for a 300 channel neural interface. Scaling the system to 900 channels is trivial.<br>Temple University--Theses
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Roh, Jeongjin. "Mixed-signal signature analysis for systems-on-a-chip." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3035971.
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Pagani, Mattia. "Microwave Photonic Signal Processing Using On-Chip Nonlinear Optics." Thesis, The University of Sydney, 2016. http://hdl.handle.net/2123/14450.
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The field of microwave photonics (MWP) emerged as a solution to the challenges faced by electronic systems when dealing with high-bandwidth RF and microwave signals. Photonic devices are capable of handling immense bandwidths thanks to the properties of light. MWP therefore employs such devices to process and distribute the information carried by RF and microwave signals, enabling significantly higher capacity compared to conventional electronics. The photonic devices traditionally used in MWP circuits have mainly comprised bulky components, such as spools of fibre and benchtop optical amplifiers. While achieving impressive performance, these systems were not capable of competing with electronics in terms of size and portability. More recently, research has focused on the application of photonic chip technology to the field of MWP in order to reap the benefits of integration, such as reductions in size, weight, cost, and power consumption. Integrated MWP however is still in its infancy, and ongoing research efforts are exploring new ways to match integrated photonic devices to the unique requirements of MWP circuits. This work investigates the application of on-chip nonlinear optical interactions to MWP. Nonlinear optics enables light-on-light interactions (not normally possible in a linear regime) which open a vast array of powerful functionalities. In particular, this thesis focuses on stimulated Brillouin scattering, resulting from the interaction of light with hypersonic sound waves, and four-wave mixing, where photons exchange energies. These two nonlinear effects are applied to implement MWP ultra-high suppression notch filters, wideband phase shifters, and ultra-fast instantaneous frequency measurement systems. Experimental demonstrations using integrated optical waveguides confirm record results.
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Al, irkhis Luay A. "Wideband DoA and Parameter Estimation of Chirp Sources using DCFT and Compressive Sensing." Wright State University / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=wright1547548984021509.
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Chen, Tsai Yuan. "Network Electrophysiology Sensor-On-A- Chip." Digital WPI, 2011. https://digitalcommons.wpi.edu/etd-dissertations/389.
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Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) bio-potential signals are commonly recorded in clinical practice. Typically, patients are connected to a bulky and mains-powered instrument, which reduces their mobility and creates discomfort. This limits the acquisition time, prevents the continuous monitoring of patients, and can affect the diagnosis of illness. Therefore, there is a great demand for low-power, small-size, and ambulatory bio-potential signal acquisition systems.
Recent work on instrumentation amplifier design for bio-potential signals can be broadly classified as using one or both of two popular techniques: In the first, an AC-coupled signal path with a MOS-Bipolar pseudo resistor is used to obtain a low-frequency cutoff that passes the signal of interest while rejecting large dc offsets. In the second, a chopper stabilization technique is designed to reduce 1/f noise at low frequencies. However, both of these existing techniques lack control of low-frequency cutoff.
This thesis presents the design of a mixed- signal integrated circuit (IC) prototype to provide complete, programmable analog signal conditioning and analog-to-digital conversion of an electrophysiologic signal. A front-end amplifier is designed with low input referred noise of 1 uVrms, and common mode rejection ratio 102 dB. A novel second order sigma-delta analog- to-digital converter (ADC) with a feedback integrator from the sigma-delta output is presented to program the low-frequency cutoff, and to enable wide input common mode range of ¡Ãƒâ€œ0.3 V. The overall system is implemented in Jazz Semiconductor 0.18 um CMOS technology with power consumption 5.8 mW from ¡Ãƒâ€œ0.9V power supplies. "
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Abaskharoun, Nazmy. "Circuits for on-chip sub-nanosecond signal capture and characterization." Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=31041.
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On-chip signal extraction and characterization structures are slowly becoming a necessary component of any complex integrated circuit design. The increased integration of the modern System On a Chip has necessitated the development of these alternate test strategies to address the issue of device node access and signal integrity. The process of extracting a signal in an analog form across a chip boundary can often compromise its true nature, as these new systems stretch performance limits.<br>The aim of this thesis is to introduce two circuits for on-chip sub-nanosecond signal capture. The emphasis is placed on providing gigahertz rate effective sampling resolutions to provide a progressive characterization solution for the ever increasing operating speed of integrated circuits.<br>The first circuit presented is a hardware implementation of an undersampling algorithm that extends the operation of a pre-existing mixed-signal test-core to the capture of periodic signals with a bandwidth much greater than the sample rate of the system. This hardware unit comprises of a specialized timing module based on a Delay Locked Loop with tap selection circuitry. The effective sampling resolution of the system is limited by the intrinsic gate delay of the technology the timing module is implemented in.<br>The second circuit presented is a specialized jitter measurement device. This device is based on a Vernier Delay Line Time-to-Digital converter, and can provide resolutions well below a gate delay. Special emphasis was given to jitter measurement, since it is an issue that is often difficult to address adequately in the testing of many complex circuits. Both the aforementioned circuits were implemented in a 0.35 mum CMOS process, and results demonstrating their successful operation are presented.
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Omeni, Okundu Chukwuemeke. "Advanced mixed signal strategies for micropower CMOS system on chip." Thesis, Imperial College London, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.420136.
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Dick, Chris. "FPGAs: RE-INVENTING THE SIGNAL PROCESSOR." International Foundation for Telemetering, 2002. http://hdl.handle.net/10150/606348.
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International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California<br>FPGAs are increasingly being employed for building real-time signal processing systems.
They have been used extensively for implementing the PHY in software radio
architectures. This paper provides a technology and market perspective on the use FPGAs
for signal processing and demonstrates FPGA DSP using an adaptive channel equalizer
case study.
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Shen, Meigen. "Concurrent chip and package design for radio and mixed-signal systems." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-476.
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Sundaresan, Krishnan. "Activity-aware modeling and design optimization of on-chip signal interconnects." Diss., Connect to online resource - MSU authorized users, 2006.
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Thesis (Ph. D.)--Michigan State University. Dept. of Electrical and Computer Engineering, 2006.<br>Title from PDF t.p. (viewed on Nov. 17, 2008) Includes bibliographical references (p. 183-195). Also issued in print.
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Farolfi, Andrea. "Elaborazione di segnali elettromagnetici mediante metasuperfici." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/24026/.
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La crescita esponenziale del traffico dati e le future applicazioni che dovranno essere supportate imporranno requisiti di bit-rate e latenza che non potranno essere soddisfatte dall'odierno standard di quinta generazione, ma richiederanno una larga banda, presumibilmente individuabile nella banda dei TeraHertz. Si prospetta che nel prossimo futuro, con l'avvento dello standard di sesta generazione (6G), le tecniche di Digital Signal Processing (DSP) correntemente utilizzate possano non essere sufficienti a soddisfare i requisiti richiesti. Le cause delle limitazioni del DSP sono da ricercare nelle elevate frequenze dei segnali, i quali, per il teorema di Shannon, richiedono convertitori analogico-digitali (ADC) e convertitori digitali-analogico (DAC) operanti a frequenze molto alte. Inoltre, l'elevata quantità di dati binari prodotta dagli ADC, non potrebbe essere processata dagli odierni circuiti digitali garantendo piccole latenze e bassi consumi. Alla luce di ciò, a livello accademico si stanno investigando metodi alternativi per eseguire il Signal Processing direttamente sull'onda elettromagnetica veicolo dell'informazione, allo scopo di semplificare l'elaborazione eseguita in digitale, con vantaggi in termini di piccole latenze, bassi consumi e modesti ingombri. In tal senso la tecnologia delle metasuperfici, dispositivi in grado di interagire con le onde elettromagnetiche effettuando funzioni non presenti o difficili da ottenere in natura, potrebbe rivestire un importante ruolo. Nel presente elaborato vengono illustrate le metasuperfici sviluppate negli ultimi anni, analizzandone le caratteristiche e le peculiarità elettromagnetiche al fine di ricavare un modello ingresso-uscita della funzione implementata. Successivamente, sfruttando alcune delle metasuperfici proposte, viene presentata una possibile applicazione delle stesse per la modulazione e demodulazione a livello elettromagnetico di segnali chirp, che rappresentano uno dei candidati per i sistemi 6G.
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Thornicroft, Keith. "Ultrasonic guided wave testing of pipelines using a broadband excitation." Thesis, Brunel University, 2015. http://bura.brunel.ac.uk/handle/2438/14001.
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Guided Wave Testing (GWT) is a relatively new development in non-destructive testing. Conventional Ultrasonic Testing (UT) methods are operated at high frequencies (MHz) and are capable of detecting very small (down to micrometre-scale) flaws within a range of millimetres from a transducer. GWT, however, is carried out at lower frequencies (kHz) and is capable of highlighting the position of volumetric structural detail and discontinuities, such as gross corrosion at a minimum of 9% of the cross-sectional area, tens of metres from a test location. Conventional ultrasonic testing relies on the transmission of bulk waves whereas GWT employs so-called ultrasonic guided waves (UGW). To simplify UGW inspections, several tests are conducted sequentially at a range of different excitation frequencies. The frequency bandwidth of each of these tests needs to be controlled to avoid complexities caused by the frequency dependent nature of the propagation of guided waves. This gives rise to the current GWT inspection procedure, where a number of different narrowband tests are conducted at several distinct frequencies. It is also found that different test circumstances (such as pipe coating or defect type) are inspected more easily with certain excitation frequencies than with others - and the optimum frequency can not always be predicted ahead of time. Thus, where time allows it is often beneficial to carry out a frequency sweep, whereby a large range of excitation frequencies are incrementally generated - for example, from 20 to 80kHz in 1kHz steps. This research proposes a novel approach to the existing pipeline inspection procedure by utilising the information contained within a broadband response. The overarching proposition given by this research is that the current collection procedure be entirely rewritten. This thesis will present ideas related to every area of the inspection procedure beginning with the tuning of excitation signals and concluding with recommendations on how tooling and excitation configuration can be modified to further optimise the technique for broadband excitation.
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Sherazi, Syed Muhammad Yasser, and Shahzad Asif. "Reduction of Simultaneous Switching Noise in Analog Signal Band on a Chip." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12249.
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<p>In the era of VLSI the technological advancements have lead us to integrate not only digital circuits of high device density but both digital and analog circuits on to the same chip. In recent years the number of devices on a chip has spectacularly increased, all</p><p>because of the downward scaling in sizes of the devices. But because of this dramatic scaling the devices have become more sensitive to the power-ground noise. Now in designing a mix signal system within single silicon die that has high speed digital circuits</p><p>along with high performance analog circuits the digital switching noise becomes a foremost concern for the correct functioning of the system.</p><p>The purpose of the thesis is to evaluate the reduction of Simultaneous Switching Noise in analog signal band with in the chip. The experiment is done by the use of DCVSL circuits combined with a novel method of implementation, instead of the common static circuits in the core design. These DCVSL circuits have the property to draw periodic currents from the power supply. So if the circuit draws equal amount of current at each clock cycle independent of the input fed to it, the generated noise’s frequency content, produced due to current spikes will then be shifted above the input clock frequency.</p><p>The idea is to reduce Simultaneous Switching Noise (SSN) by half of the clock frequency in the frequency band. This frequency band often contains to the analog signal band of a digital-to-analog converter. To evaluate the method two pipelined adders have been implemented in 0.13 μm CMOS technology. The proposed method (test circuit) is</p><p>implemented using DCVSL techniques and the reference circuit using static CMOS logic. For testing of the design we generated the input data on-chip. The pseudo-random data is generated by implementing two different length PRBS. We have also implemented a ROM containing specific test patterns. In the end, we have achieved a 10 dB decrease of noise level at the substrate node on the chip.</p>
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Omar, Omar Jaber. "An On-Chip Memory for Testing of High-Speed Mixed-Signal Circuits." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103800.
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Mixed-signal processing systems especially data converters can be reliably tested at high frequencies using on-chip testing schemes based on memory. In this thesis, an on-chip testing strategy based on shift registers/memory (2 k bits) has been proposed for digital-to-analog converters (DACs) operating at 5 GHz. The proposed design uses word length of 8 bits in order to test DAC at high speed of 5 GHz. The proposed testing strategy has been designed in standard 65 nm CMOS technology with additional requirement of 1-V supply. This design has been implemented using Cadence IC design environment. The additional advantage of the proposed testing strategy is that it requires lower number of I/O pins and avoids the large number of high speed I/O pads. It therefore also solves the problem of the bandwidth limitation that is associated with I/O transmission paths. The design of the on-chip tester based on memory contains no analog block and is implemented entirely in digital domain. In the proposed design, low frequency of 1 MHz has been used outside the chip to load the data into the memory during the write mode. During the read mode, the frequency of 625 MHz is used to read the data from the memory. A multiplexing system is used to reuse the stored data during read mode to test the intended functionality and performance. In order to convert the parallel data into serial data at high frequency at the memory output, serializer has been used. By using the frequencies of 1.25 GHz and 2.5 GHz, the serializer speeds up the data from the lower frequency of 625 MHz to the highest frequency of 5 GHz in order to test DAC at 5 GHz.
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Hafed, Mohamed M. "Analog and mixed-signal test methods using on-chip embedded test cores." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=38487.
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A robust method has been developed for the test and characterization of analog and mixed-signal integrated circuits. The method relies on a compact, robust, and easily synthesized integrated test core capable of emulating the function of external automatic test equipment. The core consists of a 2 x N memory whose contents are periodically circulated, a coarse analog filter, and a voltage comparator. One half of the circular memory is used to generate analog signals without the need for multi-bit digital-to-analog converters. The second half is used to generate extremely accurate DC levels, the latter being programmed using a clever software encoding technique that relies on some form of sigma-delta modulation. The DC levels, in combination with the comparator, enable multi-bit digitization using a progressive multiple conversion pass procedure. In order to accommodate broadband circuit phenomena, a delayed-clock sub-sampling mechanism is also employed, in which the digitizer sample clock is consistently delayed over multiple runs of the periodic test signal. One method of delaying the clock is to use a voltage-controlled delay line tuned by a delay-locked loop. The timing resolution of this approach is determined by the value of the consistent clock delay and not its period.<br>A divide-and-conquer approach to the test of deeply embedded analog integrated circuits using the proposed test core is described. Multiple test configurations are presented that can span a wide range of phenomena to be tested both internally to the integrated circuit and externally through I/O interfaces. The applicability of these configurations to increasing test parallelism both at the core and die levels is investigated. Performance limits of the proposed test core are also derived by drawing a comparison to conventional circuits used for data-conversion applications. The same fundamental limitations on integrated circuit performance are shown to affect the test core electronics, although test-specific requirements, such as forcing periodicity and the reliance on software signal processing, help further enhance on-chip measurement accuracy and repeatability. Finally, several successful experimental prototypes that demonstrate the viability of the proposed approach are presented. The prototypes range from concept proving test core integrated circuits to ones containing multiple simultaneously operated test cores and completely embedded circuits under test. In total, several hundred different test cores have been demonstrated, which is further testimony to the practicality of the proposed techniques.
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George, Suma. "Can my chip behave like my brain?" Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54905.
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Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.
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Liu, Yang. "High-Performance On-Chip Microwave Photonic Signal Processing Using Linear and Nonlinear Optics." Thesis, The University of Sydney, 2019. http://hdl.handle.net/2123/20568.
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Manipulating and processing radio-frequency (RF) signals using integrated photonic devices has recently emerged as a paradigm-shifting technology for future microwave applications. This emerging technique is referred to as integrated microwave photonics (IMWP) which enables the high-frequency processing and unprecedentedly wideband tunability in compact photonic circuits, with significantly enhanced stability and robustness. However, to find widespread applications, the performance of IMWP devices must meet or exceed the achievable performance of conventional electronic counterparts. The work presented in this thesis investigates high-performance IMWP signal processing from two aspects: the optimized IMWP processing schemes and the photonic integration. Firstly, we explore novel schemes to improve the performance of chip-based microwave photonic subsystems, such as RF delay lines and RF filters which are basic building blocks of RF systems. A phase amplification technique is demonstrated to achieve a Si3N4 chip-based RF time delay with a delay tuning speed at gigahertz level. A new scheme to achieve an all-optimized RF photonic notch filter is demonstrated, producing a record-high RF link performance and complete functionalities. To unlock the potential of RF signal processing, we investigate a new filter concept of pairing linear and nonlinear optics for a high-performance RF photonic filter. To reduce the footprint of the novel IMWP filter, the photonic integration of both the ring resonators and Brillouin-active circuits on the same photonic chip is achieved. To eliminate the use of integrated optical circulators for on-chip SBS, on-chip backward inter-modal stimulated Brillouin scattering is predicted and experimentally demonstrated in a Si-Chalcogenide hybrid integrated photonic platform. The study and demonstrations presented in this thesis make the first viable step towards high-performance IMWP signal processing for real-world RF applications.
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Blais, Sébastien R. "Superstructured Fiber Bragg Gratings and Applications in Microwave Signal Processing." Thèse, Université d'Ottawa / University of Ottawa, 2013. http://hdl.handle.net/10393/30358.
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Since their discovery in 1978 by Hill et al. and the development of the transverse holographic technique for their fabrication by Meltz et al. in 1989, fiber Bragg gratings (FBG) have become an important device for applications in optical communications, optical signal processing and fiber-optical sensors.
A superstructured fiber Bragg grating (SFBG), also called a sampled fiber Bragg grating, is a special FBG that consists of a several small FBGs placed in close proximity to one another. SFBGs have attracted much attention in recent years with the discovery of techniques allowing the creation of equivalent chirp or equivalent phase shifts. The biggest advantage of an SFBG with equivalent chirp or equivalent phase shifts is the possibility to design and fabricate gratings with greatly varying phase and amplitude responses by adjusting the spatial profile of the superstructure. The realization of SFBGs with equivalent chirp or equivalent phase shifts requires only sub-millimeter precision. This is a relief from the sub-micron precision required by traditional approaches.
In this thesis, the mathematical modeling of FBGs and SFBGs is reviewed. The use of SFBGs for various applications in photonic microwave signal processing is considered.
Four main topics are presented in this thesis. The first topic is the use of SFBG as a photonic true-time delay (TTD) beamformer for phased array antennas (PAAs).
The second topic addresses non-linearities in the group delay response of an SFBG with equivalent chirp in its sampling period. An SFBG with an equivalent chirp using only a linear chirp coefficient may yield a group delay response that deviates from the linear response required by a TTD beamformer. In the thesis, a technique to improve the linearity of the group delay response is proposed and an adaptive algorithm to find the optimal linear and non-linear chirp coefficients to produce the best linear group delay response is described. Since no closed-form solution exists to represent the amplitude and phase responses of an SFBG, we rely on a Fourier transform analogy under a weak grating approximation as a starting point in the design of an SFBG. Simulations are then used to refine the response of the SFBG. The algorithm proposed provides an optimal set of chirp coefficients that minimizes the error in the group delay response. Four gratings are fabricated using the optimized chirp coefficients and their application in a TTD PAA system is discussed.
The third topic discusses the use of an SFBG with equivalent phase shifts in its sampling period as a means to realize optical single sideband (SSB) modulation. SSB modulation eliminates the power penalty caused by chromatic dispersion experienced by an optical signal traveling through a long length of optical fiber. By introducing two π phase shifts through equivalent sampling to the SFBG, two ultra-narrow transmission bands are created in the grating stop band of the +/- 1st spectral orders. In the proposed system, a double-sideband plus carrier (DSB+C) modulated optical signal is sent to the input of an optical SSB filter based on the equivalent phase-shift SFBG in order to select the optical carrier and a single sideband, effectively blocking one sideband from propagating.
Finally, the fourth topic focuses on the implementation of a photonic microwave bandpass filter based on an SFBG with equivalent chirp. Photonic microwave filters are used to process microwave signals in the optical domain. By using a technique called phase-modulation to intensity-modulation (PM-IM) conversion, a two-tap delay line filter is created with one negative tap. A single SFBG with a chirp in its sampling period is used as a means to achieve the PM-IM conversion for the two taps. Two phase modulated optical carriers are used to generate the two taps, each entering a different port of the SFBG and thus experiencing an opposite dispersion value. The two optical signals are then recombined before being sent to a photodetector (PD) where the filtered microwave signal is recovered.
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Kim, Daeik D. "Design of Robust and Flexible On-chip Analog-to-Digital Conversion Architecture." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4773.
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This dissertation presents a comprehensive design and analysis framework for system-on-a-chip analog-to-digital conversion design. The design encompasses a broad class of systems, which take advantage of system-on-a-chip complexity. This class is exemplified by an interferometric photodetector array based bio-optoelectronic sensor that is built and tested as part of the reported work.
While there have been many discussions of the technical details of individual analog-to-digital converter (ADC) schemes in the literature, the importance of the analog front-end as a pre-processor for a data converter and the generalized analysis including converter encoding and decoding functions have not previously been investigated thoroughly, and these are key elements in the choice of converter designs for low-noise systems such as bio-optoelectronic sensors.
Frequency domain analog front-end models of ADCs are developed to enable the architectural modeling of ADCs. The proposed models can be used for ADC statistically worst-case performance estimation, with stationary random process assumptions on input signals. These models prove able to reveal the architectural advantages of a specific analog-to-digital converter schemes quantitatively, allowing meaningful comparisons between converter designs.
The modeling of analog-to-digital converters as communication channels and the ADC functional analysis as encoders and decoders are developed. This work shows that analog-to-digital converters can be categorized as either a decoder-centered design or an encoder-centered design. This perspective helps to show the advantages of nonlinear decoding schemes for oversampling noise-shaping data converters, and a new nonlinear decoding algorithm is suggested to explore the optimum solution of the decoding problem.
A case study of decoder-centered and encoder-centered data converter designs is presented by applying the proposed theoretical framework. The robustness and flexibility of the resulting analog-to-digital converters are demonstrated and compared. The electrical and optical sensitivity measurements of a fabricated oversampling noise shaping analog-to-digital converter circuit are provided, and a sensor system-on-a-chip using these ADCs with integrated interferometric waveguides for bio-optoelectronic sensing is demonstrated.
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Garate, Inaki. "Entirely digital permanent magnet synchronous machine controller by a single digital signal processor chip." Thesis, Staffordshire University, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.237841.
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Poling, Brian. "On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In-Self-Test." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1190050023.
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Taillefer, Chris. "Reducing measurement uncertainty in a DSP-based mixed-signal test environment." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=84104.
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FFT-based tests (e.g. gain, distortion, SNR, etc.) from a device-under-test (DUT) exhibit normal distributions when the measurement is repeated many times. Hence, a statistical approach to evaluate the accuracy of these measurements is traditionally applied. The noise in a DSP-based mixed-signal test system severely limits its measurement accuracy. Moreover, in high-speed sampled-channel applications the jitter-induced noise from the DUT and test equipment can severely impede accurate measurements.<br>A new digitizer architecture and post-processing methodology is proposed to increase the measurement accuracy of the DUT and the test equipment. An optimal digitizer design is presented which removes any measurement bias due to noise and greatly improves measurement repeatability. Most importantly, the presented system improves accuracy in the same test time as any conventional test.<br>An integrated mixed-signal test core was implemented in TSMC's 0.18 mum mixed-signal process. Experimental results obtained from the mixed-signal integrated test core validate the proposed digitizer architecture and post processing technique. Bias errors were successfully removed and measurement variance was improved by a factor of 5.
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Schlottmann, Craig Richard. "A coordinated approach to reconfigurable analog signal processing." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/49021.
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The purpose of this research is to create a solid framework for embedded system design with field-programmable analog arrays (FPAAs). To achieve this goal, we've created a unified approach to the three phases of FPAA system design: (1) the hardware architecture; (2) the circuit design and modeling; and (3) the high-level software tools. First, we describe innovations to the reconfigurable analog hardware that enable advanced signal processing and integration into embedded systems. We introduce the multiple-input translinear element (MITE) FPAA and the dynamically-reconfigurable RASP 2.9v FPAA, which was designed explicitly for interfacing with external digital systems. This compatibility creates a streamlined workflow for dropping the FPAA hardware into mixed-signal embedded systems. The second phase, algorithm analysis and modeling, is important to create a useful and reliable library of components for the system designer. We discuss the concept and procedure of analog abstraction that empowers non-circuit design engineers to take full advantage of analog techniques. We use the analog vector-matrix multiplier as an example for a detailed discussion on computational analog analysis and system mapping to the FPAA. Lastly, we describe high-level software tools, which are an absolute necessity for the design of large systems due to the size and complexity of modern FPAAs. We describe the Sim2Spice tool, which allows system designers to develop signal processing systems in the Simulink environment. The tool then compiles the system to the FPAA hardware. By coordinating the development of these three phases, we've created a solid unified framework that empowers engineers to utilize FPAAs.
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Carter, Scott Edward. "Development and saw device implementation of a new weighted stepped chirp code signal for direct sequence spread spectrum communications systems." Doctoral diss., University of Central Florida, 1998. http://digital.library.ucf.edu/cdm/ref/collection/RTD/id/15108.
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University of Central Florida College of Engineering Thesis<br>This work introduces the new weighted stepped chirp code signal for direct dequence spread spectrum (DS/SS) communications systems. This code signal uses the truncated cosine series functions as the chip functions. This code signal is the result of discretizing a continuous wave (CW) chirp which results in enhanced performance versus a pseudonoise (PN) cose and equivalent performance and easier implementation than a CW chirp. This code signal will be shown to possess improved compression ratio (CR), peak sidelobe level (PSL), integrated sidelobe level (ISL), and bit error rate (BER) when compared to a PN code of identical code length and chip length. It also will be shown to have a similar CR, PSL, ISL, and loss in processing gain (LPG) when compared to a CW chirp with identical pulse length and frequency deviation. The code signal is implemented on surface acoustic wave (SAW) devices which can be used as the code signal generator at the transmitter and the correlator at the receiver in a DS/SS communication system. SAW design considerations for the weighted stepped chirp signal are discussed. Experimental data is presented and compared to the predicted CR, PSL, ISL, LPG, and BER.<br>Ph.D.;<br>Electrical and Computer Engineering<br>Engineering;<br>Engineering;<br>105 p.<br>xiv, 105 leaves, bound : ill. ; 28 cm.
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Simakov, Dmitry [Verfasser]. "Dynamical tuning of a signal recycled gravitational wave detector : dynamical effects and sensitivity gain of dynamical tuning during detection of a chirp signal from compact binary coalescences / Dmitry Simakov." Hannover : Technische Informationsbibliothek und Universitätsbibliothek Hannover (TIB), 2014. http://d-nb.info/1051038081/34.
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Curtis, Bryce Allen. "A special instruction set multiple chip computer for DSP : architecture and compiler design." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15736.
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Razzaghi, Elyas, and Hoek Arno Van. "Micro-Shivering Detection : Detection of human micro-shivering using a 77 GHz radar." Thesis, Högskolan i Halmstad, Akademin för informationsteknologi, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-39807.
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Radars have been under steady development to track, identify, image, and classify targets. Modern radar systems, with the help of embedded systems, have additional comprehensive signal processing capabilities. They can extract useful information from very noisy data, e.g. interference from the environment and unwanted echoes which is collectively known as clutter in radar terms. Concerning the healthcare industry, radar applications for detection of vital signs, i.e. breathing and heart rate, have been extensively developed during the last few decades. Modern radar systems are expected to be a large part of non-intrusive monitoring in the coming smart home industry, where vital signs need to be monitored in the currently aging population. The research presented here is to break new ground in the radar-based healthcare technology, enabling detection of cold-induced shivering to such level that the micro-shivering can be clearly identified. To simplify the radar software optimization, a commercially available radar kit with demo application and a muscle model system using a vibration generator is used. The model is quantified through precise measurements. A simulated human body vital sign plus shivering is applied. By optimizing the radar software, the shivering amplitude and frequency are measured.
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Merklein, Moritz. "Controlling, storing and manipulating light using on-chip Brillouin scattering." Thesis, The University of Sydney, 2018. http://hdl.handle.net/2123/18147.
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The importance of optical signal processing techniques is growing rapidly in recent years due to the exponentially increasing demand for bandwidth, capacity and power efficiency in communications and computing. However, due to their bosonic nature photons do not interact with each other, unless there is a nonlinear medium mediating the interaction. One of the strongest nonlinear effects is the interaction of light waves, photons, with sound-waves, acoustic phonons, which is known as stimulated Brillouin scattering (SBS). This thesis experimentally investigates SBS in photonic chips. It is shown in this thesis that the fundamental interaction strength between light and sound waves can be tailored by using one-dimensional photonic bandgap structures, completely suppressing the effect or alternatively enhancing the interaction to form phase-locked Brillouin frequency combs. It was shown furthermore that efficiently generating SBS on-chip enables the generation of stable RF signals that are widely tunable in frequency. Finally, it is shown in this thesis that SBS enables the storage of light signals on a chip, one of the holy grails of all-optical signal processing. Delaying optical signals is of key importance in optical networks to enable synchronization, buffering, and rerouting. SBS enables large delays by resonantly transferring an optical signal to an acoustic wave, that travels five orders of magnitude slower and retrieving it after a certain storage time. It is demonstrated in this thesis that a Brillouin-based memory (BBM) technique allows storing amplitude and phase of optical data pulses and operate at multiple wavelengths with minimal cross-talk. Replenishing of the acoustic wave to overcome storage time limitations imposed by the lifetime of the acoustic wave as well as non-reciprocal light storage is also shown.
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Srinivasan, Venkatesh. "Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11588.
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In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.
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Weber, John Baltzer. "Spread spectrum signal characteristic estimation using exponential averaging and an ad-hoc chip rate estimator." Monterey, Calif. : Naval Postgraduate School, 2007. http://bosun.nps.edu/uhtbin/hyperion.exe/07Mar%5FWeber%5FPhD.pdf.
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Dissertation (Ph.D. in Electrical Engineering)--Naval Postgraduate School, March 2007.<br>Dissertation Advisor(s): Clark Robertson. "March 2007." Includes bibliographical references (p. 125-130). Also available in print.
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Bichan, Mike. "Signal Processing Techniques for High-speed Chip-to-chip Links." Thesis, 2012. http://hdl.handle.net/1807/32666.
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This thesis tackles the problem of high-speed data communication over wireline channels. Particular attention is paid to backplane channels which have impedance discontinuities and high-frequency loss. These channels require extra equalization effort in order to produce an open eye diagram at the receiver. Three signal processing techniques were investigated in the pursuit of higher data rates over backplane channels: transmit-side FIR filter equalization with variable tap spacing, bidirectional communication using frequency-division multiplexing, and an ADC-based receiver to provide a capability for non-linear equalization. The ADC presented here is a 5-bit flash ADC intended to be time-interleaved to attain a sufficient data rate. This ADC uses redundant comparators to obtain sufficient resolution without an explicit threshold tuning circuit. A resonant clocking line is used to reduce power and increase the maximum clock frequency.
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Lin, Ding-Zhi, and 林鼎智. "Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/q4ebx7.
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碩士<br>國立中山大學<br>電機工程學系研究所<br>106<br>With the advance of mobile healthcare and the Internet-of-things increasing numbers of applications incorporate low-power miniature sensing devices for various types of input signal. In the health and fitness market, devices monitor rehabilitation progress, quantify personal body condition, map activity, and often provide means for data integration within the front-end or via a network. This thesis focuses on the microelectronic biomedical chip for real-time measurement in the target application of a wearable monitoring system for athletes or rehabilitation.
The circuit is divided into three main parts: the temperature readout, the piezoelectric vibration readout circuit, and the variable gain amplifier circuit system to sense the electrocardiograms or muscle activity.
The vibration readout uses an external piezoelectric transducer foil which converts strain to voltage that is then conditioned and acquired by the integrated amplifier. The variable gain amplifier circuit connect to external gel electrode patches. It incorporates digitally controlled offset compensation which enables tracking and compensating for varying electrode offset in real-time. Also the amplifier gain is variable during operation to provide a good match for the amplitude of the signal input.
The system is designed and implemented in TSMC 0.18um CMOS process technology in a small active circuit area of 321.2um * 383.2um. Measured results are reported which confirm the intended operation.
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Cheng, Yi-Ren, and 鄭貽仁. "Analog signal measurement with on-chip ADC." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/52018237602013553279.
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Lin, Shi-her, and 林士赫. "Performance of Signal Identification of Chirp radar and Barker Coded Radar Signals." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/28338649996633002139.
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碩士<br>國立中央大學<br>電機工程研究所<br>88<br>A radar is an apparatus which provides positions, velocities, and some other
specific informations about the objectives of concern. It collects information by
comparing the differences between transmit signals and receiver signals. There are many types of radar signals, some of which hold similar forms. Sometimes the radar
is not able to distinguish signals which are emitted by itself from those which are interferences. This work is to study signal identification based on the method of
Maximum Likelihood.
The objective of this study is to evaluate the performance of radar signal identification, mainly focusing on chirp radar and barker coded radar. Three types of radar signals are simulated. Different sets of parameters are used to evalute their influences on the performance of signal identufucation. These parameters include, different numbers of signals, different functions, pulse repetition interval, and pulse duration time.
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Huan-Chieh, Lo, and 羅煥傑. "A digital signal processor system for PIC16F87X chip." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/74692914116038320363.
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Lin, Ｙｕ-chih, and 林育志. "Joint Time and Frequency Offset Estimation Assisted from Chirp Signal forWireless OFDM Communications." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/9tve7t.
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碩士<br>國立中央大學<br>通訊工程研究所<br>96<br>This paper describes two novel structures for reception of dual-chirp
waveforms. The approaches provide mechanisms for synchronization in
various communications environments. Both detection performance, and time
and frequency estimation accuracy are analyzed and simulated. One receiver
utilizes a dual time-domain correlator to initially estimate two peak times after
detection. Time and frequency estimates are obtained by linearly combining the
peak time estimates. The second receiver uses paired frequency-domain
correlators to initially estimate two peak frequencies and then linearly convert
them to the time and frequency estimates.