Relevant bibliographies by topics / Circuit aging

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Circuit aging'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Circuit aging"

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Jin, Song, and Yi Ran Huang. "Analysis and Evaluation on NBTI-Induced Circuit Aging." Applied Mechanics and Materials 513-517 (February 2014): 3976–82. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.3976.

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Aging effects degrade circuit performance with time, inducing reliability problem. Accurate prediction of circuit aging can help designer determine the reasonable design margin, avoiding the over-design of the circuit. Based on the physical understanding of aging mechanism, an analysis framework is proposed to predict NBTI-induced circuit aging. The analysis framework starts at the worst case prediction, which assumes the extremely operational conditions. Then, the impacts of different workloads and logic topology of the circuit on the aging-induced degradation are incorporated into the analysis framework to make the predicted result be closer to the practical scenario. Experimental results demonstrate that the effectiveness of the proposed analysis framework.
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Ahnaou, A., D. Rodriguez-Manrique, S. Embrechts, R. Biermans, N. V. Manyakov, S. A. Youssef, and W. H. I. M. Drinkenburg. "Aging Alters Olfactory Bulb Network Oscillations and Connectivity: Relevance for Aging-Related Neurodegeneration Studies." Neural Plasticity 2020 (May 2, 2020): 1–17. http://dx.doi.org/10.1155/2020/1703969.

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The aging process eventually cause a breakdown in critical synaptic plasticity and connectivity leading to deficits in memory function. The olfactory bulb (OB) and the hippocampus, both regions of the brain considered critical for the processing of odors and spatial memory, are commonly affected by aging. Using an aged wild-type C57B/6 mouse model, we sought to define the effects of aging on hippocampal plasticity and the integrity of cortical circuits. Specifically, we measured the long-term potentiation of high-frequency stimulation (HFS-LTP) at the Shaffer-Collateral CA1 pyramidal synapses. Next, local field potential (LFP) spectra, phase-amplitude theta-gamma coupling (PAC), and connectivity through coherence were assessed in the olfactory bulb, frontal and entorhinal cortices, CA1, and amygdala circuits. The OB of aged mice showed a significant increase in the number of histone H2AX-positive neurons, a marker of DNA damage. While the input-output relationship measure of basal synaptic activity was found not to differ between young and aged mice, a pronounced decline in the slope of field excitatory postsynaptic potential (fEPSP) and the population spike amplitude (PSA) were found in aged mice. Furthermore, aging was accompanied by deficits in gamma network oscillations, a shift to slow oscillations, reduced coherence and theta-gamma PAC in the OB circuit. Thus, while the basal synaptic activity was unaltered in older mice, impairment in hippocampal synaptic transmission was observed only in response to HFS. However, age-dependent alterations in neural network appeared spontaneously in the OB circuit, suggesting the neurophysiological basis of synaptic deficits underlying olfactory processing. Taken together, the results highlight the sensitivity and therefore potential use of LFP quantitative network oscillations and connectivity at the OB level as objective electrophysiological markers that will help reveal specific dysfunctional circuits in aging-related neurodegeneration studies.
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Danka Mohammed, Chand Parvez. "Differential Circuit Mechanisms of Young and Aged Visual Cortex in the Mammalian Brain." NeuroSci 2, no. 1 (January 4, 2021): 1–26. http://dx.doi.org/10.3390/neurosci2010001.

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The main goal of this review is to summarize and discuss (1) age-dependent structural reorganization of mammalian visual cortical circuits underlying complex visual behavior functions in primary visual cortex (V1) and multiple extrastriate visual areas, and (2) current evidence supporting the notion of compensatory mechanisms in aged visual circuits as well as the use of rehabilitative therapy for the recovery of neural plasticity in normal and diseased aging visual circuit mechanisms in different species. It is well known that aging significantly modulates both the structural and physiological properties of visual cortical neurons in V1 and other visual cortical areas in various species. Compensatory aged neural mechanisms correlate with the complexity of visual functions; however, they do not always result in major circuit alterations resulting in age-dependent decline in performance of a visual task or neurodegenerative disorders. Computational load and neural processing gradually increase with age, and the complexity of compensatory mechanisms correlates with the intricacy of higher form visual perceptions that are more evident in higher-order visual areas. It is particularly interesting to note that the visual perceptual processing of certain visual behavior functions does not change with age. This review aims to comprehensively discuss the effect of normal aging on neuroanatomical alterations that underlie critical visual functions and more importantly to highlight differences between compensatory mechanisms in aged neural circuits and neural processes related to visual disorders. This type of approach will further enhance our understanding of inter-areal and cortico-cortical connectivity of visual circuits in normal aging and identify major circuit alterations that occur in different visual deficits, thus facilitating the design and evaluation of potential rehabilitation therapies as well as the assessment of the extent of their rejuvenation.
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Thirunavukkarasu, A., Hussam Amrouch, Jerin Joe, Nilesh Goel, Narendra Parihar, Subrat Mishra, Chetan K. Dabhi, Yogesh S. Chauhan, Jorg Henkel, and Souvik Mahapatra. "Device to Circuit Framework for Activity-Dependent NBTI Aging in Digital Circuits." IEEE Transactions on Electron Devices 66, no. 1 (January 2019): 316–23. http://dx.doi.org/10.1109/ted.2018.2882229.

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More, S., M. Fulde, F. Chouard, and D. Schmitt-Landsiedel. "Reliability analysis of buffer stage in mixed signal application." Advances in Radio Science 9 (August 1, 2011): 225–30. http://dx.doi.org/10.5194/ars-9-225-2011.

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Abstract. This paper discusses reliability analysis of a buffer circuit targeted for an analog to digital converter application. The circuit designed in a 32 nm high-κ metal gate CMOS technology was investigated by circuit simulation and sensitivity analysis. This analysis was conducted for realistic time varying (AC) stress. As aging effects, negative and positive bias temperature instability, conducting and non-conducting hot carrier injection are taken into consideration. The aging contributions of these effects on the different transistors in the buffer circuit and on different buffer performance figures are evaluated. Using these results, the impact of an aged buffer circuit on the performance of a successive approximation ADC circuit is evaluated. The most severely affected performance due to aging is amplifier offset, which leads to time varying gain error in the ADC circuit.
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Song, Shihao, Jui Hanamshet, Adarsha Balaji, Anup Das, Jeffrey L. Krichmar, Nikil D. Dutt, Nagarajan Kandasamy, and Francky Catthoor. "Dynamic Reliability Management in Neuromorphic Computing." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (July 19, 2021): 1–27. http://dx.doi.org/10.1145/3462330.

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Neuromorphic computing systems execute machine learning tasks designed with spiking neural networks. These systems are embracing non-volatile memory to implement high-density and low-energy synaptic storage. Elevated voltages and currents needed to operate non-volatile memories cause aging of CMOS-based transistors in each neuron and synapse circuit in the hardware, drifting the transistor’s parameters from their nominal values. If these circuits are used continuously for too long, the parameter drifts cannot be reversed, resulting in permanent degradation of circuit performance over time, eventually leading to hardware faults. Aggressive device scaling increases power density and temperature, which further accelerates the aging, challenging the reliable operation of neuromorphic systems. Existing reliability-oriented techniques periodically de-stress all neuron and synapse circuits in the hardware at fixed intervals, assuming worst-case operating conditions, without actually tracking their aging at run-time. To de-stress these circuits, normal operation must be interrupted, which introduces latency in spike generation and propagation, impacting the inter-spike interval and hence, performance (e.g., accuracy). We observe that in contrast to long-term aging, which permanently damages the hardware, short-term aging in scaled CMOS transistors is mostly due to bias temperature instability. The latter is heavily workload-dependent and, more importantly, partially reversible. We propose a new architectural technique to mitigate the aging-related reliability problems in neuromorphic systems by designing an intelligent run-time manager (NCRTM), which dynamically de-stresses neuron and synapse circuits in response to the short-term aging in their CMOS transistors during the execution of machine learning workloads, with the objective of meeting a reliability target. NCRTM de-stresses these circuits only when it is absolutely necessary to do so, otherwise reducing the performance impact by scheduling de-stress operations off the critical path. We evaluate NCRTM with state-of-the-art machine learning workloads on a neuromorphic hardware. Our results demonstrate that NCRTM significantly improves the reliability of neuromorphic hardware, with marginal impact on performance.
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Surabhi, Virinchi Roy, Prashanth Krishnamurthy, Hussam Amrouch, Kanad Basu, Jorg Henkel, Ramesh Karri, and Farshad Khorrami. "Hardware Trojan Detection Using Controlled Circuit Aging." IEEE Access 8 (2020): 77415–34. http://dx.doi.org/10.1109/access.2020.2989735.

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Hernandez, Yoanlys, Bernhard Stampfer, Tibor Grasser, and Michael Waltl. "Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies." Crystals 11, no. 9 (September 21, 2021): 1150. http://dx.doi.org/10.3390/cryst11091150.

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All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.
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Barajas, Enrique, Xavier Aragones, Diego Mateo, and Josep Altet. "Differential Temperature Sensors: Review of Applications in the Test and Characterization of Circuits, Usage and Design Methodology." Sensors 19, no. 21 (November 5, 2019): 4815. http://dx.doi.org/10.3390/s19214815.

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Differential temperature sensors can be placed in integrated circuits to extract a signature of the power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper first discusses the singularity that differential temperature sensors provide with respect to other sensor topologies, with circuit monitoring being their main application. The paper focuses on the monitoring of radio-frequency analog circuits. The strategies to extract the power signature of the monitored circuit are reviewed, and a list of application examples in the domain of test and characterization is provided. As a practical example, we elaborate the design methodology to conceive, step by step, a differential temperature sensor to monitor the aging degradation in a class-A linear power amplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how, for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamic range is required. A circuit solution for this objective is proposed, as well as recommendations for the dimensions and location of the devices that form the temperature sensor. The paper concludes with a description of a simple procedure to monitor time variability.
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Fodor, István, Réka Svigruha, György Kemenes, Ildikó Kemenes, and Zsolt Pirger. "The Great Pond Snail (Lymnaea stagnalis) as a Model of Aging and Age-Related Memory Impairment: An Overview." Journals of Gerontology: Series A 76, no. 6 (January 16, 2021): 975–82. http://dx.doi.org/10.1093/gerona/glab014.

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Abstract With the increase of life span, normal aging and age-related memory decline are affecting an increasing number of people; however, many aspects of these processes are still not fully understood. Although vertebrate models have provided considerable insights into the molecular and electrophysiological changes associated with brain aging, invertebrates, including the widely recognized molluscan model organism, the great pond snail (Lymnaea stagnalis), have proven to be extremely useful for studying mechanisms of aging at the level of identified individual neurons and well-defined circuits. Its numerically simpler nervous system, well-characterized life cycle, and relatively long life span make it an ideal organism to study age-related changes in the nervous system. Here, we provide an overview of age-related studies on L. stagnalis and showcase this species as a contemporary choice for modeling the molecular, cellular, circuit, and behavioral mechanisms of aging and age-related memory impairment.
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Dissertations / Theses on the topic "Circuit aging"

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Shah, Nimay Shamik. "Built-in proactive tuning for circuit aging and process variation resilience." [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2891.

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Moudgil, Rashmi. "A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs." Thesis, Virginia Tech, 2013. http://hdl.handle.net/10919/23177.

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Counterfeit Integrated Circuits (ICs) are previously used ICs that are resold as new. They have become a serious problem in modern electronic devices. They cause lower performance, reduced life span and even catastrophic failure of systems and platforms. To prevent counterfeiting and the associated revenue loss, there is need for non-invasive and inexpensive techniques to establish the authenticity of devices. We describe a technique to detect a counterfeit IC that does not have any special anti-counterfeiting mechanisms built-in prior to deployment. Our detection criterion is based on measuring path delays. The experiments show that a single path delay cannot directly reveal the age, as it is also greatly influenced by process variation and this could result in large error in classifying ICs as authentic or counterfeit. �Instead, we establish that the relationship between the delays of two or more paths is a great indicator for the age of device. The idea is to project ICs from different age groups onto the space of the path delays and train a trusted reference hyper-surface for each age group. Ideally, the hyper-surfaces do not overlap. In this way, an IC under test can be assigned to one hyper-surface based on the distance of its footprint with respect to these hyper-surfaces, thus predicting its age. In our simulations, we observe over 97% correct prediction of identifying an aged IC from a new IC.
Master of Science
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Alladi, Phaninder. "VALIDATION OF CIRCUIT TIMING BEHAVIOR IN THE PRESENCE OF DELAY DEFECTS AND NBTI AGING." OpenSIUC, 2016. https://opensiuc.lib.siu.edu/dissertations/1292.

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In deep sub-micron, the decrease in feature size of the transistor has led to increasing challenge in testing an integrated circuit for delay defects. Small Delay Defects (SDD) have become predominant with aggressive scaling of the transistors. SDDs occur within gates, and interconnect. The traditional stuck-at, and transition fault model are not appropriate to model such defects. They must be tested appropriately by targeting critical paths in the circuit. Furthermore, reliability issues such as Negative Bias Temperature Instability (NBTI) and Hot carrier injection impact the threshold voltage of a transistor which, in turn, affect path delays. This necessitates selecting critical paths and formulating test methods that consider the above factors. An efficient method to select critical paths in the presence of small delay defects is presented. Due to the limitations in test application time, only a limited number of test patterns are applied that only sensitize a small subset of the critical paths. The paths are selected such that the defect probability density function of any node n in the circuit is maximized. The method uses the established linear parameterized model to encapsulate variations in process parameters. Experimental results on ISCAS ’85’, ’89’ and ITC ’99’ benchmarks demonstrate the scalability of the approach. In the presence of NBTI effects, the set of critical paths obtained at manufacturing time may change at a later time because paths age differently. An approach that generates a test set TL that target a set of paths PL (|TL|<|PL|) that become critical over the product life span L is presented. The critical paths in PL characterize timing behavior of the circuit considering process related variations. In addition, a pin-to-pin aging degradation model is introduced that accurately computes path delays. Experimental results on ISCAS ’85’,’89’ and ITC ’99’ benchmarks demonstrate the scalability of the approach. Finally, a BIST mechanism to detect counterfeit circuits which experience aging delays is presented. The approach is based on the NBTI aging factor. HSPICE simulations on 45nm and 65nm technologies using a predictive NBTI degradation model are presented. The results indicate that counterfeit circuits undergone minimal stress are detected consistently in the presence of process variations.
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Butzen, Paulo Francisco. "Aging aware design techniques and CMOS gate degradation estimative." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/61868.

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O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa miniaturização permitiu a construção de dispositivos menores, mais rápidos e que consomem menos frequência. O outro fator é a utilização da metodologia baseada em biblioteca de células. Esta metodologia permite o projeto de um circuito eficiente em um curto espaço de tempo. Com a redução dos dispositivos, novos fatores que eram desconsiderados no fluxo automático passaram a ter importância. Dentre eles podemos citar o consumo estático, a variabilidade, a manufaturabilidade e o envelhecimento. Alguns desses fatores, como o consumo estático e a variabilidade, já estão integrados à metodologia baseada em biblioteca de células. Os efeitos de envelhecimento tem sua degradação aumentada a cada novo processo tecnológico, assim como tem aumentado também a sua importância em relação à confiabilidade do circuito ao longo da sua vida útil. Este trabalho irá explorar estes efeitos de envelhecimento no projeto de circuitos integrados digitais. Dentre as principais contribuições pode-se destacar a definição de um custo de envelhecimento na definição de portas lógicas, que pode ser explorado pelos algoritmos de síntese lógica para obterem um circuito mais confiável. Este custo também pode ser utilizado pelas ferramentas de análise a fim de obter uma estimativa da degradação que o circuito proposto irá sofrer ao longo da sua vida útil. Além disso, é apresentada uma proposta de reordenamento estrutural do arranjo de transistores em portas lógicas, a fim de tratar os efeitos de envelhecimento nos níveis mais iniciais do fluxo. Por fim, uma análise simplificada de características a serem exploradas ao nível de circuito é discutida utilizando o auxílio do projeto de portas lógicas complexas. Os resultados apresentam uma boa e rápida estimativa da degradação das portas lógicas. A reestruturação do arranjo dos transistores tem se apresentado como uma boa alternativa ao projeto de circuitos mais confiáveis. Além disso, a utilização de arranjos mais complexos também é uma excelente alternativa que explora a robustez intrínseca da associação de transistores em série. Além disso, as alternativas propostas podem ser utilizadas em conjunto com técnicas já existentes na literatura.
The increased presence of integrated circuit (IC) in the people’s life has occurred for main two reasons. The first is the aggressive scaling of integrated device dimensions. This miniaturization enabled the construction of smaller, faster and lower power consumption devices. The other factor is the use of a cell based methodology in IC design. This methodology is able to provide efficient circuits in a short time. With the devices scaling, new factors that were usually ignored in micrometer technologies have become relevant in nanometer designs. Among them, it can be mentioned the static consumption, process parameters variability, manufacturability and aging effects. Some of these factors, such as static consumption and variability, are already taken into account by the standard cell design methodology. On the other hand, the degradation caused by aging effects has increased at each new technology node, as well as the importance in relation to the circuit reliability throughout its entire lifetime has also increased. This thesis explores such aging effects in the design of digital IC. The main contributions can be highlighted as the definition of a cost of aging that can be exploited by logic synthesis algorithms to produce a more reliable circuit. This cost can be also used by the analysis tools in order to obtain an estimative of the degradation that specific circuit experiences throughout their lifetime. In addition, a proposal to reorder the transistor structural arrangement of logic gates is presented in order to treat the effects of aging on initial steps in the design flow. Finally, a simplified analysis of the characteristics to be exploited at circuit level is performed exploring details of the design of complex logic gates. The aging cost results have given a good and fast prediction of logic gates degradation. The transistor arrangement restructuring approach is a good alternative to design more reliable circuits. Furthermore, the use of complex arrangements is also an excellent alternative which exploits the intrinsic robustness of series transistors association. Moreover, the discussed approaches can be easily used together with existing techniques in the literature to achieve better results.
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Dal, Bem Vinícius. "CMOS digital integrated circuit design faced to NBTI and other nanometric effects." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/37180.

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Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuitos, este efeito de envelhecimento recebe destaque também neste texto, sendo explorado mais detalhadamente. Diversas técnicas de avaliação de redução do NBTI são demonstradas, sendo apresentados, em cada um destes tópicos, trabalhos desenvolvidos no âmbito desta dissertação e seus resultados. O circuito proposto como técnica de avaliação de NBTI permite uso de simulações elétricas para análise de degradação de circuitos. A análise da influência do rearranjo da estrutura de transistores para reduzir a degradação quanto ao NBTI apresenta bons resultados e não impede o uso de outras técnicas combinadas.
This thesis explores the challenges worsened by the technology miniaturization in fabrication and design of digital integrated circuits. The physical effects of nanometric regime reduce the production yield and shorten the devices lifetime, restricting the usefulness of standard design flows and threatening the evolution of CMOS technologies. This thesis exposes a consistent bibliographic review about the main aggressive physical effects of nanometric regime. NBTI has received special attention in reliability literature, so this text follows the same strategy, deeply exploring this aging effect. A broad set of NBTI evaluation and mitigation techniques are explained, including developed works in each one of these categories. The proposed circuit as NBTI evaluation technique allows the use of electrical simulation for circuit degradation analysis. The analysis of the transistors arrangement restructuring as a technique for NBTI degradation reduction shows satisfactory results, while does not restrict the use of other combined techniques.
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Sienkiewicz, Lukasz Krzysztof. "Concept, implementation and analysis of the piezoelectric resonant sensor / Actuator for measuring the aging process of human skin." Thesis, Toulouse, INPT, 2016. http://www.theses.fr/2016INPT0047/document.

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L’objectif de cet projet est la conception, réalisation et caractérisation d’un actionneur / capteur piézoélectrique piézorésonant destiné à la mesure du vieillissement de la peau humaine. L’étude présentée est le fruit d’une collaboration entre le groupe de recherche de l'Electrodynamique du INP-ENSEEIHT (Toulouse), LAPLACE Laboratoire de Recherche et l'École Polytechnique de Gdask, Département Génie Electrique et Automatique. Un concept d’actionneur / capteur pour la caractérisation des propriétés mécaniques des tissus mous a été présenté. Un actionneur piézoélectrique résonant, appelé "unimorphe" a été choisi parmi les différentes structures piézoélectriques fondées sur le cahier des charges. L'innovation du projet réside dans l'intégration de la méthode d'indentation dynamique en utilisant un unimorphe comme dispositif d'indentation. Ceci permet l'utilisation d'un certain nombre de propriétés électromécaniques favorables des transducteurs piézo-électriques. Ce mémoire est divisé en 7 chapitres. Le chapitre 1 présente la thèse et ses objectifs. Le chapitre 2 présente le phénomène piézoélectrique et les applications piézoélectriques dans les domaines de la médecine et de la bio ingénierie. Le chapitre 3 décrit le cahier des charges pour le transducteur développé. Le choix du transducteur unimorphe est ainsi justifié. Le chapitre 4 présente une description analytique du transducteur unimorphe, y compris les calculs de déformations statiques, la description du circuit équivalent de Mason, et la description des conditions de contact entre la sonde d'indentation et les matériaux testés. Le chapitre 5 contient l'analyse numérique du transducteur unimorphe en utilisant le modèle virtuel MEF. Les résultats de simulations statiques et modales sont décrits par deux géométries considérées du transducteur. Le chapitre 6 décrit le processus de vérification expérimentale des modèles analytiques et numériques développés pour le transducteur unimorphe. Enfin, le dernier chapitre comprend des conclusions générales concernant les résultats de recherche obtenus, ainsi que les travaux futurs possibles. Afin de vérifier la thèse d'un cycle complet de recherche a été effectuée, qui a couvert: étude analytique, l'analyse numérique (simulations MEF), réalisation de prototype, et la vérification expérimentale des actionneurs / capteurs piézoélectriques considérés
The main goal of the dissertation was following: preparation of a new concept, implementation and analysis of the piezoelectric resonant sensor/actuator for measuring the aging process of human skin. The research work has been carried out in the framework of cooperation between the INP-ENSEEIHT-LAPLACE, Toulouse, France, and at the Gdansk University of Technology, Faculty of Electrical and Control Engineering, Research Group of Power Electronics and Electrical Machines, Gdask, Poland. A concept of transducer for the characterization of mechanical properties of soft tissues was presented. The piezoelectric resonant, bending transducer, referred to as “unimorph transducer” was chosen from different topologies of piezoelectric benders based on the fulfillment of the stated requirements. The innovation of the project lies in the integration of the dynamic indentation method by using a unimorph as an indentation device. This allows the use of a number of attractive electromechanical properties of piezoelectric transducers. The thesis is divided into seven chapters. Chapter 1 states the thesis and goals of the dissertation. Chapter 2 presents piezoelectric phenomenon and piezoelectric applications in the fields of medicine and bioengineering. Chapter 3 describes the requirements for the developed transducer. The choice of unimorph transducer is justified. Chapter 4 presents an analytical description of the unimorph transducer, including the calculations of static deformations, equivalent circuit description, and description of the contact conditions between the transducer and the tested materials. Chapter 5 contains the numerical analysis of the unimorph transducer using FEM virtual model. Results of static and modal simulations are described for two considered geometries of the transducer. Chapter 6 describes the experimental verification process of analytic and numerical models developed for unimorph transducer. The final chapter includes general conclusions concerning obtained research results and achievements, as well as possible future works. In order to verify the proposition of the thesis a full research cycle was carried out, that covered: analytical study, numerical analysis (FEM simulations), prototype realization, and experimental verification of the considered (developed) piezoelectric sensor/actuator structures
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Tsujikawa, Hiroshi. "Klotho, a gene related to a syndrome resembling human premature aging, functions in a negative regulatory circuit of vitamin D endocrine system." Kyoto University, 2004. http://hdl.handle.net/2433/145275.

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Cordoba, Arenas Andrea Carolina. "Aging Propagation Modeling and State-of-Health Assessment in Advanced Battery Systems." The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1385967836.

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Fu, Jian zhi. "Mise en oeuvre de moyens de vieillissement accéléré et d'analyses dédiés aux composants de puissance grand gap." Thesis, Normandie, 2018. http://www.theses.fr/2018NORMR075/document.

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Cette thèse constitue un des éléments du projet de recherche EMOCAVI (Evolution des Modèles des Composants de puissance grand gAp au cours du VIeillissement). Elle porte sur l’étude de la fiabilité des transistors de puissance en Nitrure de Gallium (GaN) récemment apparus sur le marché. Ces travaux se focalisent sur la réalisation d’une méthodologie pour paramétrer le modèle du composant GaN GIT (Gate Injection Transistor) en fonction du vieillissement auquel il a été soumis. Pour atteindre cet objectif, nous sommes passés par plusieurs étapes. La première a été consacrée à la définition, la mise en place et la validation d’un banc de vieillissement et à la caractérisation de ces composants avant et en cours de vieillissement. Un banc de test de vieillissement en court-circuit répétitif à faible puissance a été conçu et mis en oeuvre. Ce banc a permis de valider l’hypothèse du vieillissement lié à l’énergie, d’identifier son niveau déterminant d’un point de vue fiabilité du composant et enfin mettre en évidence la dégradation progressive du composant afin d’identifier les paramètres du transistor les plus sensibles au vieillissement. La deuxième étape de nos travaux a été consacrée à l’établissement d’une méthodologie de création de modèle de vieillissement du composant GaN-GIT. En reproduisant le modèle COBRA présenté dans la littérature, nous avons réussi dans nos travaux à proposer une approche novatrice permettant d’intégrer les dépendances en température et en énergie subie par le composant pendant le stress (la durée d’impulsion Tsc et le nombre de pulse subi Nsc). La dernière étape de nos travaux a été dédiée à l’analyse physique de défaillance afin de confirmer les hypothèses faites sur les mécanismes de dégradation obtenus après vieillissement du composant. Pour réaliser ces analyses, nous avons commencé par la décapsulation du composant en combinant l’ouverture laser aux attaques chimiques de la résine constituant le packaging. Une fois le défaut localisé par photoluminescence, une analyse approfondie par des vues au microscope électronique à balayage MEB puis par découpe PFIB (Plasma Fouced Ion Beam) a été réalisée afin de déterminer le mécanisme de défaillance. Il s’agissait principalement de fissures situées dans le métal d’Al au niveau du drain ainsi que la présence de cavités dans la couche métallique qui sert à réaliser le contact ohmique au niveau de la source, ce qui explique l’augmentation de la résistance RDSON
This thesis constitute one of the elements of the EMOCAVI research project (Evolution of the Large gAp Power Component Models during the VIeillissement). It deals with the study of the reliability of Gallium Nitride (GaN) power transistors which are recently appeared on the market. This work focuses on the realization of a methodology to parameterize the model of GaN GIT component (Gate Injection Transistor) according to the aging to which it has been subjected. To achieve this goal, it will be necessary to go through several steps. The first step was dedicated to the definition, implementation and validation of an aging bench for the component and the characterization of these components before and during aging. A low power repetitive short-circuit aging test bench was designed and implemented. This bench is used to validate the energy-related aging hypothesis, to identify its determining level from a point of view of the reliability of the component and finally to highlight the progressive degradation of the component in order to identify the parameters of the transistor which are the most sensitive to aging. The second step of our work was devoted to the establishment of a methodology to create the aging model for the GaN-GIT component. By reproducing the COBRA model presented in the literature, we have succeeded in our work in proposing an innovative approach to integrate the dependencies in temperature and energy suffered by the component during stress (the Tsc pulse duration and the number of pulse suffered Nsc). The last step of our work was dedicated to the physical failure analysis in order to confirm the hypothesis made on the degradation mechanisms obtained after aging of the component. To carry out these analyzes, we started with the de-capsulation of the component by combining the laser cutting with the chemical attacks of the resin constituting the packaging. Once the defect was localized by photoluminescence, an in-depth analysis by SEM scanning and then PFIB (Plasma Focused Ion Beam) scans was performed to determine the mechanism of failure. These were mainly cracks in the Al metal at the drain and the presence of cavities in the metal layer which is used to make the Ohmic contact at the source, which explains the increase in resistance RDSON
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Altieri, scarpato Mauricio. "Estimation de la performance des circuits numériques sous variations PVT et vieillissement." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT093/document.

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La réduction des dimensions des transistors a augmenté la sensibilité des circuits numériques aux variations PVT et, plus récemment, aux effets de vieillissement, notamment BTI et HCI. De larges marges de sécurité sont donc nécessaires pour assurer un fonctionnement correct du circuit, ce qui entraîne une perte d'énergie importante. Les solutions actuelles pour améliorer l'efficacité énergétique sont principalement basées sur des solutions de type «Adaptive Voltage and Frequency Scaling (AVFS)». Cependant, ce type de solution ne peut anticiper les variations avant qu'elles ne se produisent. Cette approche doit donc être amélioré pour traiter les problèmes de fiabilité liés au vieillissement. Cette thèse propose une nouvelle méthodologie pour générer des modèles simplifiés pour estimer la fréquence maximale du circuit Fmax. Un premier modèle est créé pour estimer le délai de propagation du (des) chemin(s) critique(s) en fonction des variations PVT. Les effets BTI et HCI sont ensuite modélisés via une modification des paramètres du premier modèle. Construit à partir des modèles au niveau transistor, le modèle de vieillissement obtenu prend en compte tous les facteurs qui influent sur le vieillissement, à savoir, la topologie des circuits, l'application, la tension et la température. La méthodologie proposée est validée sur deux architectures en technologie 28nm FD-SOI. Les modèles peuvent être alimentés par des moniteurs de température et de tension, ce qui permet une évaluation précise de l'évolution de Fmax. Toutefois, ces moniteurs sont sensibles au vieillissement. Aussi, une méthode de recalibrage pour compenser les effets du vieillissement a été développée pour un moniteur numérique de température et de tension. Des exemples d'applications en ligne sont donnés. Les modèles sont également utilisés pour simuler des circuits complexes sous des variations de vieillissement, par exemple un circuit multi-cœur et un système AVFS. Cela permet d'évaluer différentes stratégies concernant la performance, l'énergie et la fiabilité
The continuous scaling of transistor dimensions has increased the sensitivity of digital circuits to PVT variations and, more recently, to aging effects such as BTI and HCI. Large voltage guard bands, corresponding to worst-case operation, are thus necessary and leads to a considerable energy loss. Current solutions to increase energy efficiency are mainly based on Adaptive Voltage and Frequency Scaling (AVFS). However, as a reactive solution, it cannot anticipate the variation before it occurs. It has, thus, to be improved for handling long-term reliability issues. This thesis proposes a new methodology to generate simplified but nevertheless accurate models to estimate the circuit maximum operating frequency Fmax. A first model is created for the modelling of the propagation delay of the critical path(s) as a function of PVT variations. Both BTI/HCI effects are then modelled as a shift in the parameters of the first model. Built on the top of device-level models, it takes into account all factors that impact global aging, namely, circuit topology, workload, voltage and temperature variations. The proposed modelling approach is evaluated on two architectures implemented in 28nm FD-SOI technology. The models can be fed by temperature and voltage monitors. This allows an accurate assessment of the circuit Fmax evolution during its operation. However, these monitors are prone to aging. Therefore, an aging-aware recalibration method has been developed for a particular V T monitor. Examples of on-line applications are given. Finally, the models are used to simulate complex circuits under aging variations such a multi-core circuit and an AVFS system. This allows the evaluation of different strategies regarding performance, energy and reliability
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Books on the topic "Circuit aging"

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Halak, Basel, ed. Ageing of Integrated Circuits. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-23781-3.

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Gleason, J. F. Comprehensive aging assessment of circuit breakers and relays. Supt. of Docs., U.S. G.P.O. [distributor], 1992.

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Bai, Lijun, Tuo Zhang, Xi-Nian Zuo, and Mingzhou Ding, eds. Balancing Act: Structural-Functional Circuit Disruptions and Compensations in Developing and Aging Brain Disorders. Frontiers Media SA, 2020. http://dx.doi.org/10.3389/978-2-88963-486-6.

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Halak, Basel. Ageing of Integrated Circuits: Causes, Effects and Mitigation Techniques. Springer, 2019.

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Kandler, Karl, ed. The Oxford Handbook of the Auditory Brainstem. Oxford University Press, 2018. http://dx.doi.org/10.1093/oxfordhb/9780190849061.001.0001.

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The Oxford Handbook of the Auditory Brainstem provides an in-depth reference to the organization and function of ascending and descending auditory pathways in the mammalian brainstem. Individual chapters are organized along the auditory pathway, beginning with the cochlea and ending with the auditory midbrain. Each chapter provides an introduction to the respective area and summarizes our current knowledge before discussing the disputes and challenges that the field currently faces.The handbook emphasizes the numerous forms of plasticity that are increasingly observed in many areas of the auditory brainstem. Several chapters focus on neuronal modulation of function and plasticity on the synaptic, neuronal, and circuit level, especially during development, aging, and following peripheral hearing loss. In addition, the book addresses the role of trauma-induced maladaptive plasticity with respect to its contribution in generating central hearing dysfunction, such as hyperacusis and tinnitus.The book is intended for students and postdoctoral fellows starting in the auditory field and for researchers of related fields who wish to get an authoritative and up-to-date summary of the current state of auditory brainstem research. For clinical practitioners in audiology, otolaryngology, and neurology, the book is a valuable resource of information about the neuronal mechanisms that are currently discussed as major candidates for the generation of central hearing dysfunction.
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Davidson, James D. Capacitance-voltage analysis, SPICE modeling, and aging studies of AC thin-film electroluminescent devices. 1991.

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Davidson, James D. Capacitance-voltage analysis, SPICE modeling, and aging studies of AC thin-film electroluminescent devices. 1991.

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Book chapters on the topic "Circuit aging"

1

Golanbari, Mohammad Saber, Mojtaba Ebrahimi, Saman Kiamehr, and Mehdi B. Tahoori. "Selective Flip-Flop Optimization for Circuit Reliability." In Dependable Embedded Systems, 337–64. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_14.

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AbstractThis chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timing-critical components under severe impact of runtime variations. As flip-flops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the overall system lifetime. In the proposed method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe Bias Temperature Instability (BTI) impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop critical flip-flops of the circuit with optimized versions to improve the timing and reliability of the entire circuit in a cost-effective way. Simulation results show that incorporating the optimized flip-flops in a processor can prolong the circuit lifetime by 36.9%, which translates into better reliability.This chapter is organized as follows. Section 1 introduces wide-voltage operation reliability issues and motivates the proposed selective flip-flop optimization approach. The impacts of runtime variations on flip-flops are explained in Sect. 2. Consequently, Sect. 3 presents cell-level optimization of the flip-flops. The proposed selective flip-flop optimization methodology is described in Sect. 4, and optimization results are discussed in Sect. 5. Finally, Sect. 7 concludes the chapter.
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Islam, Mahfuzul, and Hidetoshi Onodera. "Monitor Circuits for Cross-Layer Resiliency." In Dependable Embedded Systems, 385–407. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_16.

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AbstractCross-layer resiliency has become a critical deciding factor for any successful product. This chapter focuses on monitor circuits that are essential in realizing the cross-layer resiliency. The role of monitor circuits is to establish a bridge between the hardware and other layers by providing information about the devices and the operating environment in run-time. This chapter explores delay-based monitor circuits for design automation with the existing cell-based design methodology. The chapter discusses several design techniques to monitor parameters of threshold voltage, temperature, leakage current, critical delay, and aging. The chapter then demonstrates a reconfigurable architecture to monitor multiple parameters with small area footprint. Finally, an extraction methodology of physical parameters is discussed for model-hardware correlation. Utilizing the cell-based design flow, delay-based monitors can be placed inside the target digital circuit and thus a better correlation between monitor and target circuit behavior can be realized.
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Keane, John, Xiaofei Wang, Pulkit Jain, and Chris H. Kim. "On-Chip Silicon Odometers for Circuit Aging Characterization." In Bias Temperature Instability for Devices and Circuits, 679–717. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-7909-3_27.

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Gebregiorgis, Anteneh, Rajendra Bishnoi, and Mehdi B. Tahoori. "Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches." In Dependable Embedded Systems, 303–34. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_13.

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AbstractNear-threshold computing (NTC) has significant role in reducing the energy consumption of modern very large-scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This chapter presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near-threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this chapter, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture-level analysis.
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Chen, Ning, Bing Li, and Ulf Schlichtmann. "Timing Modeling of Flipflops Considering Aging Effects." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 63–72. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_7.

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Knoth, Christoph, Carsten Uphoff, Sebastian Kiesel, and Ulf Schlichtmann. "SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 193–203. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_20.

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Graeb, Helmut. "How to Include Pareto Front Computation, Discrete Parameter Values and Aging into Analog Circuit Sizing." In Mathematics in Industry, 411–17. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-23413-7_56.

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Diekmann, S., R. Nitsch, and T. G. Ohm. "The organotypic entorhinal-hippocampal complex slice culture of adolescent rats. A model to study transcellular changes in a circuit particularly vulnerable in neurodegenerative disorders." In Cell and Animal Models in Aging and Dementia Research, 61–71. Vienna: Springer Vienna, 1994. http://dx.doi.org/10.1007/978-3-7091-9350-1_5.

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Abbas, Haider Muhi, Mark Zwolinski, and Basel Halak. "Aging Mitigation Techniques for Microprocessors Using Anti-aging Software." In Ageing of Integrated Circuits, 67–89. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23781-3_3.

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Helms, Domenik. "Understanding Ageing Mechanisms." In Ageing of Integrated Circuits, 3–34. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23781-3_1.

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Conference papers on the topic "Circuit aging"

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Byunghyun Jang, Jin Kyung Lee, Minsu Choi, and Kyung Ki Kim. "On-chip aging prediction circuit in nanometer digital circuits." In 2014 International SoC Design Conference (ISOCC). IEEE, 2014. http://dx.doi.org/10.1109/isocc.2014.7087599.

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Simevski, Aleksandar, Rolf Kraemer, and Milos Krstic. "Low-complexity integrated circuit aging monitor." In Systems (DDECS). IEEE, 2011. http://dx.doi.org/10.1109/ddecs.2011.5783060.

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Sengupta, Deepashree, and Sachin S. Sapatnekar. "Predicting circuit aging using ring oscillators." In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2014. http://dx.doi.org/10.1109/aspdac.2014.6742929.

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Mintarno, Evelyn, Joelle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen Boyd, Robert W. Dutton, and Subhasish Mitra. "Optimized self-tuning for circuit aging." In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010. http://dx.doi.org/10.1109/date.2010.5457140.

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Rosenbaum, E., J. Xiong, A. Yang, Z. Chen, and M. Raginsky. "Machine Learning for Circuit Aging Simulation." In 2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 2020. http://dx.doi.org/10.1109/iedm13553.2020.9371931.

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Wang, Wenping, Varsha Balakrishnan, Bo Yang, and Yu Cao. "Statistical prediction of NBTI-induced circuit aging." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734563.

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Firouzi, Farshad, Fangming Ye, Arunkumar Vijayan, Abhishek Koneru, Krishnendu Chakrabarty, and Mehdi B. Tahoori. "Re-using BIST for circuit aging monitoring." In 2015 20th IEEE European Test Symposium (ETS). IEEE, 2015. http://dx.doi.org/10.1109/ets.2015.7138768.

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Zheng, Rui, Jyothi Velamala, Vijay Reddy, Varsha Balakrishnan, Evelyn Mintarno, Subhasish Mitra, Srikanth Krishnan, and Yu Cao. "Circuit aging prediction for low-power operation." In 2009 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2009. http://dx.doi.org/10.1109/cicc.2009.5280814.

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Haoyuan Jiang, Chenyue Ma, Lining Zhang, and Mansun Chan. "Concurrent device/circuit aging for general reliability simulations." In 2016 International Symposium on Integrated Circuits (ISIC). IEEE, 2016. http://dx.doi.org/10.1109/isicir.2016.7829708.

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Sutaria, Ketul, Athul Ramkumar, Rongjun Zhu, and Yu Cao. "Where is the Achilles Heel under Circuit Aging." In 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2014. http://dx.doi.org/10.1109/isvlsi.2014.106.

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Reports on the topic "Circuit aging"

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G. William Hannaman and C. Dan Wilkinson. Evaluating the Effects of Aging on Electronic Instrument and Control Circuit Boards and Components in Nuclear Power Plants. Office of Scientific and Technical Information (OSTI), May 2005. http://dx.doi.org/10.2172/841248.

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