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Journal articles on the topic 'Circuit aging'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Jin, Song, and Yi Ran Huang. "Analysis and Evaluation on NBTI-Induced Circuit Aging." Applied Mechanics and Materials 513-517 (February 2014): 3976–82. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.3976.

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Aging effects degrade circuit performance with time, inducing reliability problem. Accurate prediction of circuit aging can help designer determine the reasonable design margin, avoiding the over-design of the circuit. Based on the physical understanding of aging mechanism, an analysis framework is proposed to predict NBTI-induced circuit aging. The analysis framework starts at the worst case prediction, which assumes the extremely operational conditions. Then, the impacts of different workloads and logic topology of the circuit on the aging-induced degradation are incorporated into the analysis framework to make the predicted result be closer to the practical scenario. Experimental results demonstrate that the effectiveness of the proposed analysis framework.

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2

Ahnaou, A., D. Rodriguez-Manrique, S. Embrechts, R. Biermans, N. V. Manyakov, S. A. Youssef, and W. H. I. M. Drinkenburg. "Aging Alters Olfactory Bulb Network Oscillations and Connectivity: Relevance for Aging-Related Neurodegeneration Studies." Neural Plasticity 2020 (May 2, 2020): 1–17. http://dx.doi.org/10.1155/2020/1703969.

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The aging process eventually cause a breakdown in critical synaptic plasticity and connectivity leading to deficits in memory function. The olfactory bulb (OB) and the hippocampus, both regions of the brain considered critical for the processing of odors and spatial memory, are commonly affected by aging. Using an aged wild-type C57B/6 mouse model, we sought to define the effects of aging on hippocampal plasticity and the integrity of cortical circuits. Specifically, we measured the long-term potentiation of high-frequency stimulation (HFS-LTP) at the Shaffer-Collateral CA1 pyramidal synapses. Next, local field potential (LFP) spectra, phase-amplitude theta-gamma coupling (PAC), and connectivity through coherence were assessed in the olfactory bulb, frontal and entorhinal cortices, CA1, and amygdala circuits. The OB of aged mice showed a significant increase in the number of histone H2AX-positive neurons, a marker of DNA damage. While the input-output relationship measure of basal synaptic activity was found not to differ between young and aged mice, a pronounced decline in the slope of field excitatory postsynaptic potential (fEPSP) and the population spike amplitude (PSA) were found in aged mice. Furthermore, aging was accompanied by deficits in gamma network oscillations, a shift to slow oscillations, reduced coherence and theta-gamma PAC in the OB circuit. Thus, while the basal synaptic activity was unaltered in older mice, impairment in hippocampal synaptic transmission was observed only in response to HFS. However, age-dependent alterations in neural network appeared spontaneously in the OB circuit, suggesting the neurophysiological basis of synaptic deficits underlying olfactory processing. Taken together, the results highlight the sensitivity and therefore potential use of LFP quantitative network oscillations and connectivity at the OB level as objective electrophysiological markers that will help reveal specific dysfunctional circuits in aging-related neurodegeneration studies.

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3

Danka Mohammed, Chand Parvez. "Differential Circuit Mechanisms of Young and Aged Visual Cortex in the Mammalian Brain." NeuroSci 2, no. 1 (January 4, 2021): 1–26. http://dx.doi.org/10.3390/neurosci2010001.

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The main goal of this review is to summarize and discuss (1) age-dependent structural reorganization of mammalian visual cortical circuits underlying complex visual behavior functions in primary visual cortex (V1) and multiple extrastriate visual areas, and (2) current evidence supporting the notion of compensatory mechanisms in aged visual circuits as well as the use of rehabilitative therapy for the recovery of neural plasticity in normal and diseased aging visual circuit mechanisms in different species. It is well known that aging significantly modulates both the structural and physiological properties of visual cortical neurons in V1 and other visual cortical areas in various species. Compensatory aged neural mechanisms correlate with the complexity of visual functions; however, they do not always result in major circuit alterations resulting in age-dependent decline in performance of a visual task or neurodegenerative disorders. Computational load and neural processing gradually increase with age, and the complexity of compensatory mechanisms correlates with the intricacy of higher form visual perceptions that are more evident in higher-order visual areas. It is particularly interesting to note that the visual perceptual processing of certain visual behavior functions does not change with age. This review aims to comprehensively discuss the effect of normal aging on neuroanatomical alterations that underlie critical visual functions and more importantly to highlight differences between compensatory mechanisms in aged neural circuits and neural processes related to visual disorders. This type of approach will further enhance our understanding of inter-areal and cortico-cortical connectivity of visual circuits in normal aging and identify major circuit alterations that occur in different visual deficits, thus facilitating the design and evaluation of potential rehabilitation therapies as well as the assessment of the extent of their rejuvenation.

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Thirunavukkarasu, A., Hussam Amrouch, Jerin Joe, Nilesh Goel, Narendra Parihar, Subrat Mishra, Chetan K. Dabhi, Yogesh S. Chauhan, Jorg Henkel, and Souvik Mahapatra. "Device to Circuit Framework for Activity-Dependent NBTI Aging in Digital Circuits." IEEE Transactions on Electron Devices 66, no. 1 (January 2019): 316–23. http://dx.doi.org/10.1109/ted.2018.2882229.

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5

More, S., M. Fulde, F. Chouard, and D. Schmitt-Landsiedel. "Reliability analysis of buffer stage in mixed signal application." Advances in Radio Science 9 (August 1, 2011): 225–30. http://dx.doi.org/10.5194/ars-9-225-2011.

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Abstract. This paper discusses reliability analysis of a buffer circuit targeted for an analog to digital converter application. The circuit designed in a 32 nm high-κ metal gate CMOS technology was investigated by circuit simulation and sensitivity analysis. This analysis was conducted for realistic time varying (AC) stress. As aging effects, negative and positive bias temperature instability, conducting and non-conducting hot carrier injection are taken into consideration. The aging contributions of these effects on the different transistors in the buffer circuit and on different buffer performance figures are evaluated. Using these results, the impact of an aged buffer circuit on the performance of a successive approximation ADC circuit is evaluated. The most severely affected performance due to aging is amplifier offset, which leads to time varying gain error in the ADC circuit.

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6

Song, Shihao, Jui Hanamshet, Adarsha Balaji, Anup Das, Jeffrey L. Krichmar, Nikil D. Dutt, Nagarajan Kandasamy, and Francky Catthoor. "Dynamic Reliability Management in Neuromorphic Computing." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (July 19, 2021): 1–27. http://dx.doi.org/10.1145/3462330.

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Neuromorphic computing systems execute machine learning tasks designed with spiking neural networks. These systems are embracing non-volatile memory to implement high-density and low-energy synaptic storage. Elevated voltages and currents needed to operate non-volatile memories cause aging of CMOS-based transistors in each neuron and synapse circuit in the hardware, drifting the transistor’s parameters from their nominal values. If these circuits are used continuously for too long, the parameter drifts cannot be reversed, resulting in permanent degradation of circuit performance over time, eventually leading to hardware faults. Aggressive device scaling increases power density and temperature, which further accelerates the aging, challenging the reliable operation of neuromorphic systems. Existing reliability-oriented techniques periodically de-stress all neuron and synapse circuits in the hardware at fixed intervals, assuming worst-case operating conditions, without actually tracking their aging at run-time. To de-stress these circuits, normal operation must be interrupted, which introduces latency in spike generation and propagation, impacting the inter-spike interval and hence, performance (e.g., accuracy). We observe that in contrast to long-term aging, which permanently damages the hardware, short-term aging in scaled CMOS transistors is mostly due to bias temperature instability. The latter is heavily workload-dependent and, more importantly, partially reversible. We propose a new architectural technique to mitigate the aging-related reliability problems in neuromorphic systems by designing an intelligent run-time manager (NCRTM), which dynamically de-stresses neuron and synapse circuits in response to the short-term aging in their CMOS transistors during the execution of machine learning workloads, with the objective of meeting a reliability target. NCRTM de-stresses these circuits only when it is absolutely necessary to do so, otherwise reducing the performance impact by scheduling de-stress operations off the critical path. We evaluate NCRTM with state-of-the-art machine learning workloads on a neuromorphic hardware. Our results demonstrate that NCRTM significantly improves the reliability of neuromorphic hardware, with marginal impact on performance.

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7

Surabhi, Virinchi Roy, Prashanth Krishnamurthy, Hussam Amrouch, Kanad Basu, Jorg Henkel, Ramesh Karri, and Farshad Khorrami. "Hardware Trojan Detection Using Controlled Circuit Aging." IEEE Access 8 (2020): 77415–34. http://dx.doi.org/10.1109/access.2020.2989735.

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8

Hernandez, Yoanlys, Bernhard Stampfer, Tibor Grasser, and Michael Waltl. "Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies." Crystals 11, no. 9 (September 21, 2021): 1150. http://dx.doi.org/10.3390/cryst11091150.

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All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

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9

Barajas, Enrique, Xavier Aragones, Diego Mateo, and Josep Altet. "Differential Temperature Sensors: Review of Applications in the Test and Characterization of Circuits, Usage and Design Methodology." Sensors 19, no. 21 (November 5, 2019): 4815. http://dx.doi.org/10.3390/s19214815.

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Differential temperature sensors can be placed in integrated circuits to extract a signature of the power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper first discusses the singularity that differential temperature sensors provide with respect to other sensor topologies, with circuit monitoring being their main application. The paper focuses on the monitoring of radio-frequency analog circuits. The strategies to extract the power signature of the monitored circuit are reviewed, and a list of application examples in the domain of test and characterization is provided. As a practical example, we elaborate the design methodology to conceive, step by step, a differential temperature sensor to monitor the aging degradation in a class-A linear power amplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how, for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamic range is required. A circuit solution for this objective is proposed, as well as recommendations for the dimensions and location of the devices that form the temperature sensor. The paper concludes with a description of a simple procedure to monitor time variability.

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10

Fodor, István, Réka Svigruha, György Kemenes, Ildikó Kemenes, and Zsolt Pirger. "The Great Pond Snail (Lymnaea stagnalis) as a Model of Aging and Age-Related Memory Impairment: An Overview." Journals of Gerontology: Series A 76, no. 6 (January 16, 2021): 975–82. http://dx.doi.org/10.1093/gerona/glab014.

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Abstract With the increase of life span, normal aging and age-related memory decline are affecting an increasing number of people; however, many aspects of these processes are still not fully understood. Although vertebrate models have provided considerable insights into the molecular and electrophysiological changes associated with brain aging, invertebrates, including the widely recognized molluscan model organism, the great pond snail (Lymnaea stagnalis), have proven to be extremely useful for studying mechanisms of aging at the level of identified individual neurons and well-defined circuits. Its numerically simpler nervous system, well-characterized life cycle, and relatively long life span make it an ideal organism to study age-related changes in the nervous system. Here, we provide an overview of age-related studies on L. stagnalis and showcase this species as a contemporary choice for modeling the molecular, cellular, circuit, and behavioral mechanisms of aging and age-related memory impairment.

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11

Al-Haidary, Jafer T., Ali M. Aldulaimi, and Ahmed A. Hamza. "Effect of Aging on Corrosion Behavior of Martensite Phase in Cu-Al-Be Shape Memory Alloy." Al-Nahrain Journal for Engineering Sciences 21, no. 1 (February 10, 2018): 127. http://dx.doi.org/10.29194/njes21010127.

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The corrosion behavior of martensite phase in Cu-Al-Be shape memory alloy with aging at 150 at time 2,4and 6 hour and quenching ice water with salt, water at room temperature and oil media study by open circuit potential, tafal polarization and cyclic polarization. The microstructure of martensite study by optical microscope and x-ray diffraction(XRD) and transformation temperature was determined by Diﬀerential Scanning Calorimeter (DSC).the result show aging martensite at 150 at 2 and 4 hour have high open circuit potential, low corrosion current density , high corrosion potential and pitting potential than martensite without aging.

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12

Abernathy, Harry, Harry O. Finklea, David S. Mebane, Xiaoke Chen, Kirk Gerdes, and Maria D. Salazar-Villalpando. "Reversible aging behavior of La0.8Sr0.2MnO3 electrodes at open circuit." Journal of Power Sources 216 (October 2012): 11–14. http://dx.doi.org/10.1016/j.jpowsour.2012.05.029.

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13

Zhang, Zuodong, Runsheng Wang, Xuguang Shen, Dehuang Wu, Jiayang Zhang, Zhe Zhang, Joddy Wang, and Ru Huang. "Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis." IEEE Transactions on Electron Devices 68, no. 9 (September 2021): 4201–7. http://dx.doi.org/10.1109/ted.2021.3096171.

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14

Kim, Kyung Ki. "Design of a new adaptive circuit to compensate for aging effects of nanometer digital circuits." Journal of the Korea Industrial Information Systems Research 18, no. 6 (December 31, 2013): 25–30. http://dx.doi.org/10.9723/jksiis.2013.18.6.025.

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15

Watts, Milton, and K. Rob Harker. "Comparative Reliability Prediction Using Physics of Failure Models." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000189–95. http://dx.doi.org/10.4071/hiten-paper3-mwatts.

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Quartzdyne Electronics has invested millions of device test hours in life testing of circuits in both powered and un-powered tests. In addition to time at temperature, these tests include thermal cycling and high impact drop testing. Recent projects have required the use of larger packages and components as we have expanded the variety of circuits that we build. It is desirable to predict the effects of these changes on long-term reliability before investing in tooling. In this study we will compare a new design which contains these larger components to the simpler, smaller designs for which we have extensive life-test data. Using a physics-of-failure approach, component mounting stresses will be analyzed using finite element modeling. These results will be compared to pre and post-aging shear strengths of actual components of varying sizes. Aging models will then be developed to predict the reliability of the new design based on the comparative stress margins of the individual components coupled with circuit complexity. Once validated, the aging models will enable reliability prediction and trade-off analysis for future designs.

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16

Tudor, Bogdan, Joddy Wang, Zhaoping Chen, Robin Tan, Weidong Liu, and Frank Lee. "An accurate MOSFET aging model for 28nm integrated circuit simulation." Microelectronics Reliability 52, no. 8 (August 2012): 1565–70. http://dx.doi.org/10.1016/j.microrel.2011.12.008.

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17

Schlünder, C., K. Puschkarsky, G. A. Rott, W. Gustin, and H. Reisinger. "NBTI: Experimental investigation, physical modelling, circuit aging simulations and verification." Microelectronics Reliability 82 (March 2018): 1–10. http://dx.doi.org/10.1016/j.microrel.2017.12.043.

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18

Wang, Yu, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, and Huazhong Yang. "Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 4 (April 2011): 615–28. http://dx.doi.org/10.1109/tvlsi.2009.2037637.

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19

Cucu Laurenciu, N., and S. D. Cotofana. "Critical transistors nexus based circuit-level aging assessment and prediction." Journal of Parallel and Distributed Computing 74, no. 6 (June 2014): 2512–20. http://dx.doi.org/10.1016/j.jpdc.2013.08.006.

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20

Zhang, Yuejun, Zhidi Jiang, Pengjun Wang, and Xuelong Zhang. "High accuracy digital aging monitor based on PLL-VCO circuit." Journal of Semiconductors 36, no. 1 (January 2015): 015004. http://dx.doi.org/10.1088/1674-4926/36/1/015004.

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21

Calazans, Ney Laert Vilar, Taciano Ares Rodolfo, and Marcos L. L. Sartori. "Robust and Energy-Efficient Hardware: The Case for Asynchronous Design." Journal of Integrated Circuits and Systems 16, no. 2 (August 19, 2021): 1–11. http://dx.doi.org/10.29292/jics.v16i2.518.

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The current technologies behind the design of semiconductor integrated circuits allow embedding billions of components in a singe silicon die, enabling the construction of very complex circuits in a tiny space, dissipating little energy and producing huge amounts of useful computational work. However, the current levels of integration for electronic components in silicon and similar materials are not easily managed, as parameter variations grow steadily, making the design tasks increasingly challenging. Synchronous techniques have dominated the digital system design landscape for many decades, but their costs are increasingly hard to cope with. Asynchronous design and particularly quasi-delay insensitive design promises to deal with the same challenges more gracefully in current advanced nodes, and possibly irrevocably in future technology nodes. This article proposes a review of the state of the art in using asynchronous circuit design techniques to achieve energy-efficient and robust digital circuit and system design. In particular, the definition of a robust digital circuit comprises addressing several aspects to which a digital system design is expected to be robust to, including: (1) voltage variations; (2) process variations; (3) temperature variations; (4) circuit aging. Besides addressing energy-efficiency and all the mentioned robustness aspects, this work also approaches some of the state-of-the-art tools available to deal with asynchronous design, and points to desirable research development to be conducted in these subjects in the future.

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22

Jayasinghe, Darshana, Aleksandar Ignjatovic, Roshan Ragel, Jude Angelo Ambrose, and Sri Parameswaran. "QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks." ACM Transactions on Design Automation of Electronic Systems 26, no. 5 (June 5, 2021): 1–36. http://dx.doi.org/10.1145/3443706.

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Side channel analysis attacks employ the emanated side channel information to deduce the secret keys from cryptographic implementations by analyzing the power traces during execution or scrutinizing faulty outputs. To be effective, a countermeasure must remove or conceal as many as possible side channels. However, many of the countermeasures against side channel attacks are applied independently. In this article, the authors present a novel countermeasure (referred to as QuadSeal ) against Power Analysis Attacks and Electromagentic Fault Injection Attacks (FIAs), which is an extension of the work proposed in Reference [27]. The proposed solution relies on algorithmically balancing both Hamming distances and Hamming weights (where the bit transitions on the registers and gates are balanced, and the total number of 1s and 0s are balanced) by the use of four identical circuits with differing inputs and modified SubByte tables. By randomly rotating the four encryptions, the system is protected against variations, path imbalances, and aging effects. After generating the ciphertext, the output of each circuit is compared against each other to detect any fault injections or to correct the faulty ciphertext to gain reliability. The proposed countermeasure allows components to be switched off to save power or to run four executions in parallel for high performance when resistance against power analysis attacks is not of high priority, which is not available with the existing countermeasures (except software based where source code can be changed). The proposed countermeasure is implemented for Advanced Encryption Standard (AES) and tested against Correlation Power Analysis and Mutual Information Attacks attacks (for up to a million traces), and none of the secret keys was found even after one million power traces (the unprotected AES circuit is vulnerable for power analysis attacks within 5,000 power traces). A detection circuit (referred to as C-FIA circuit) is operated using the algorithmic redundancy presented in four circuits of QuadSeal to mitigate Electromagnetic Fault Injection Attacks. Using Synopsys PrimeTime, we measured the power dissipation of QuadSeal registers and XOR gates to test the effectiveness of Quadruple balancing methodology. We tested the QuadSeal countermeasure with C-FIA circuit against Differential Fault Analysis Attacks up to one million traces; no bytes of the secret key were found. This is the smallest known circuit that is capable of withstanding power-based side channel attacks when electromagnetic injection attack resistance, process variations, path imbalances, and aging effects are considered.

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SKRYPNYK, S., and A. SHEINA. "Short circuits currents comparison of 6 (10) kV and 20 kV." Journal of Electrical and power engineering 14, no. 1 (February 27, 2020): 21–26. http://dx.doi.org/10.31474/2074-2630-2020-1-21-26.

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Most failures in electrical installations are caused by short circuits (short circuits), which occur as a result of a failure in the electrical strength of the insulation of the conductive parts. A short circuit is an electrical connection of two points of an electric circuit with different values of potential, which is not provided by the design of the device, which interferes with its normal operation. Short circuits may result from a failure of the insulation of the current-carrying elements or the mechanical contact of the non- insulated elements. Also called a short circuit is a condition where the load resistance is less than the internal resistance of the power source. The reasons for such violations are various: aging of insulation, breakages of wires of overhead transmission lines, mechanical damages of isolation of cable lines at ground works, lightning strikes in the transmission line and others. Most often, short-circuits occur through transient resistance, such as through the resistance of an electric arc that occurs at the point of damage to the insulation. Sometimes there are metallic short circuits in which the resistance of the electric arc is very small. The study of short circuits in the power grid is a major step in the design of modern electrical networks. The research is conducted using computer software, first by modeling the system and then simulating errors. A malfunction usually leads to an increase in the current flowing in the lines, and failure to provide reliable protection can result in damage to the power unit. Thus, short-circuit calculations are the primary consideration when designing, upgrading, or expanding a power system. The three-phase short circuit is the least likely. However, in many cases, the three-phase short circuit is associated with the most severe consequences, as it causes the highest power imbalances on the shafts of the generators. The study of transients begins with the mode of three-phase closure due to its relative simplicity in comparison with other types of asymmetry. In most cases, the analysis and calculation of the transient regime of the electrical system involves the preparation of a calculated scheme of substitution, in which the parameters of its elements are determined in named or relative units. The electrical substitution circuitry is used to further study the transients in the power system. The definition of electrical and electromagnetic quantities in relative units is widely used in the theory of electric machines. This is because it significantly simplifies the theoretical calculations and gives the results a generalized view in the practical calculations of currents and residual voltages at the short circuit. By the relative value of any value is understood as its relation to another value of the same name, taken as the base. So, before presenting any quantities in relative units, we need to choose the basic units. In the electrical system with increased voltages, the overall load capacity of the network increases, which in turn makes it possible to supply high-quality electrical energy over a greater distance. In the process of comparing the type of transmission lines, it should be noted that the advantages of the cable transmission line. According to the results of the calculation of short-circuit currents, it can be concluded that in networks with a larger line cross-section and a higher voltage, the short-circuit currents are larger. Thus, during the transition of the electric networks to the higher voltage class of 20 kV, the currents of the KZ increased by 43% compared to the 6 kV electric network. This analysis shows that the importance of reliable power supply in the power supply system for high voltage classes must be high and have equipment to prevent emergencies. In the future, it is planned to develop a systematic calculation of short-circuit currents for a number of transmission lines and to conduct mathematical modeling in the system of applications for the study of transient processes at short circuits.

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24

sriraman, Harini, and Pattabiraman Venkatasubbu. "SeRA: Self-Repairing Architecture for Dark Silicon Era." Journal of Circuits, Systems and Computers 29, no. 04 (June 13, 2019): 2050053. http://dx.doi.org/10.1142/s021812662050053x.

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The lifetime reliability of processors has become a major design constraint in the dark silicon era. Processor reliability issues are mainly due to design defects and aging. Unlike design defects, however, aging faults gradually accumulate over time. Many methods have recently been proposed to monitor the performance degradation of circuits. In this study, an architectural solution that extends the circuit-level age monitoring to processor stages is proposed for monitoring performance degradation. When degradation of a stage quantified as delay of half of the reference clock occurs, a self-repairing mechanism is triggered. This mechanism configures an field programmable gate array (FPGA), which takes over the functions of the degraded unit. The proposed self-repairing mechanism is applied to the stages of the processor data-path. This method (SeRA) has lesser area overhead compared with the state-of-art solutions.

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Shao, Lei, He Ming Zhao, Yi Biao Yu, and Tao Liu. "Design of Live Evaluation System of Organic Materials Aging." Applied Mechanics and Materials 321-324 (June 2013): 245–51. http://dx.doi.org/10.4028/www.scientific.net/amm.321-324.245.

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Organic materials (cable particularly) aging has an adverse effect on the safety of productionsituations, and it is unscientific to replace organic materials blindly. A live evaluation system of organicmaterials aging was developed in present paper. This system consists of control and detection circuit(composed by ARM chip S3C6410 and force sensor, etc.) and servo drive motor. Compressivemodulus of organic materials was tested by the system with the help of mechanical system, so as toevaluate the cable aging.

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26

Schlünder, C. "Device reliability challenges for modern semiconductor circuit design – a review." Advances in Radio Science 7 (May 19, 2009): 201–11. http://dx.doi.org/10.5194/ars-7-201-2009.

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Abstract. Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1). Degradation mechanisms like Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI) lead to parameter drifts during operation adding on top of the process variations. The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs. An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR) will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.

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27

Yi, Hyunbean. "An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring." JSTS:Journal of Semiconductor Technology and Science 13, no. 1 (February 28, 2013): 71–78. http://dx.doi.org/10.5573/jsts.2013.13.1.071.

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28

Yan, Luming, Huaguo Liang, and Zhengfeng Huang. "Aging failure protection for integrated circuit based on spatio-temporal redundancy." JOURNAL OF ELECTRONIC MEASUREMENT AND INSTRUMENT 27, no. 1 (November 29, 2013): 38–44. http://dx.doi.org/10.3724/sp.j.1187.2013.00038.

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29

Mbarek, S., F. Fouquet, P. Dherbecourt, M. Masmoudi, and O. Latry. "Gate oxide degradation of SiC MOSFET under short-circuit aging tests." Microelectronics Reliability 64 (September 2016): 415–18. http://dx.doi.org/10.1016/j.microrel.2016.07.132.

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Ma, En-Hua, Wen-En Wei, Hung-Yi Li, James Chien-Mo Li, I.-Chun Cheng, and Yung-Hui Yeh. "Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects." Journal of Display Technology 10, no. 1 (January 2014): 19–27. http://dx.doi.org/10.1109/jdt.2013.2277590.

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Zhang, Lining, Chenyue Ma, Ying Xiao, Hanyu Zhang, Xinnan Lin, and Mansun Chan. "A Dynamic Time Evolution Method for Concurrent Device-Circuit Aging Simulations." IEEE Transactions on Electron Devices 66, no. 1 (January 2019): 184–90. http://dx.doi.org/10.1109/ted.2018.2882832.

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Yazdanbakhsh, Amir, Raghuraman Balasubramanian, Tony Nowatzki, and Karthikeyan Sankaralingam. "Comprehensive Circuit Failure Prediction for Logic and SRAM Using Virtual Aging." IEEE Micro 35, no. 6 (November 2015): 24–36. http://dx.doi.org/10.1109/mm.2015.136.

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Keane, John, Wei Zhang, and Chris H. Kim. "An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization." IEEE Journal of Solid-State Circuits 46, no. 10 (October 2011): 2374–85. http://dx.doi.org/10.1109/jssc.2011.2160813.

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LIANG, Huaguo, Xiangsheng FANG, Maoxiang YI, Zhengfeng HUANG, and Yingchun LU. "A novel BIST scheme for circuit aging measurement of aerospace chips." Chinese Journal of Aeronautics 31, no. 7 (July 2018): 1594–601. http://dx.doi.org/10.1016/j.cja.2018.04.013.

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Liang, Xia, Li-Ming Hsu, Hanbing Lu, Jessica A. Ash, Peter R. Rapp, and Yihong Yang. "Functional Connectivity of Hippocampal CA3 Predicts Neurocognitive Aging via CA1–Frontal Circuit." Cerebral Cortex 30, no. 8 (April 2, 2020): 4297–305. http://dx.doi.org/10.1093/cercor/bhaa008.

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Abstract The CA3 and CA1 principal cell fields of the hippocampus are vulnerable to aging, and age-related dysfunction in CA3 may be an early seed event closely linked to individual differences in memory decline. However, whether the differential vulnerability of CA3 and CA1 is associated with broader disruption in network-level functional interactions in relation to age-related memory impairment, and more specifically, whether CA3 dysconnectivity contributes to the effects of aging via CA1 network connectivity, has been difficult to test. Here, using resting-state fMRI in a group of aged rats uncontaminated by neurodegenerative disease, aged rats displayed widespread reductions in functional connectivity of CA3 and CA1 fields. Age-related memory deficits were predicted by connectivity between left CA3 and hippocampal circuitry along with connectivity between left CA1 and infralimbic prefrontal cortex. Notably, the effects of CA3 connectivity on memory performance were mediated by CA1 connectivity with prefrontal cortex. We additionally found that spatial learning and memory were associated with functional connectivity changes lateralized to the left CA3 and CA1 divisions. These results provide novel evidence that network-level dysfunction involving interactions of CA3 with CA1 is an early marker of poor cognitive outcome in aging.

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Ait-Amar, Sonia, Daniel Roger, and Serghei Savin. "Aging monitoring of electrical machines using winding high frequency equivalent circuits." Open Physics 17, no. 1 (December 5, 2019): 670–77. http://dx.doi.org/10.1515/phys-2019-0069.

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Abstract This study defines a monitoring method based on impedance analysis in the upper part of the spectrum. It focuses on the analysis of the high frequency behavior of electrical machines windings considering the turn-to-turn capacitance variations (delta-C) due to insulation aging. An equivalent circuit is automatically generated from the turn arrangements in coils; parameters are computed considering the coil shape and the characteristics of insulation materials. PSpice analysis of the equivalent circuit yields the resonance frequencies to be monitored. With this software and a database giving the relationship between the turn-to-turn capacitance variation delta-C and the reduction of insulation performances due to aging, it is possible to build a monitoring system able to produce an alert when the probability of failure becomes higher than a predetermined level.

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Miller, Jonas G., Tiffany C. Ho, Kathryn L. Humphreys, Lucy S. King, Lara C. Foland-Ross, Natalie L. Colich, Sarah J. Ordaz, Jue Lin, and Ian H. Gotlib. "Early Life Stress, Frontoamygdala Connectivity, and Biological Aging in Adolescence: A Longitudinal Investigation." Cerebral Cortex 30, no. 7 (March 26, 2020): 4269–80. http://dx.doi.org/10.1093/cercor/bhaa057.

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Abstract Early life stress (ELS) may accelerate frontoamygdala development related to socioemotional processing, serving as a potential source of resilience. Whether this circuit is associated with other proposed measures of accelerated development is unknown. In a sample of young adolescents, we examined the relations among ELS, frontoamygdala circuitry during viewing of emotional faces, cellular aging as measured by telomere shortening, and pubertal tempo. We found that greater cumulative severity of ELS was associated with stronger negative coupling between bilateral centromedial amygdala and the ventromedial prefrontal cortex, a pattern that may reflect more mature connectivity. More negative frontoamygdala coupling (for distinct amygdala subdivisions) was associated with slower telomere shortening and pubertal tempo over 2 years. These potentially protective associations of negative frontoamygdala connectivity were most pronounced in adolescents who had been exposed to higher ELS. Our findings provide support for the formulation that ELS accelerates maturation of frontoamygdala connectivity and provide novel evidence that this neural circuitry confers protection against accelerated biological aging, particularly for adolescents who have experienced higher ELS. Although negative frontoamygdala connectivity may be an adaptation to ELS, frontoamygdala connectivity, cellular aging, and pubertal tempo do not appear to be measures of the same developmental process.

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Yeoh, Mian-En, Adrian Jaloman, and Kah-Yoong Chan. "Aging effect in dye-sensitized solar cells sealed with thermoplastic films." Microelectronics International 36, no. 2 (April 1, 2019): 68–72. http://dx.doi.org/10.1108/mi-11-2018-0075.

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Purpose The purpose of this paper is to elucidate the aging effect in dye-sensitized solar cells (DSSCs) sealed with thermoplastic film and to compare it with unsealed DSSCs. Design/methodology/approach The paper presents the steps of the fabrication of standard DSSC, as well as the DSSC-sealing processes, by using thermoplastic film. Current-voltage characterization was performed to observe the changes in efficiency, fill factor, short circuit current density and open circuit voltage for both unsealed and sealed DSSCs for aging time up to 336 h. Findings The unsealed DSSC showed significant drop in efficiency from 4.26 to 2.42 per cent within the first 5.5 h of aging time because of the leakage and volatilization of the solvent in the electrolyte. On the other hand, the sealed DSSC exhibited a gradual improvement of efficiency from 4.16 to 4.73 per cent after the first 216 h of aging time. The initial efficiency increment can be ascribed to the improved adsorption of electrolyte into the titanium dioxide film because of the gradual desorption of excess dye from TiO2 with increasing aging time. Originality/value This paper demonstrates the importance of the proper sealing process for the long-term operation of DSSC.

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WIRNSHOFER, MARTIN, NASIM POUR ARYAN, LEONHARD HEISS, DORIS SCHMITT-LANDSIEDEL, and GEORG GEORGAKOS. "ON-LINE SUPPLY VOLTAGE SCALING BASED ON IN SITU DELAY MONITORING TO ADAPT FOR PVTA VARIATIONS." Journal of Circuits, Systems and Computers 21, no. 08 (December 2012): 1240027. http://dx.doi.org/10.1142/s0218126612400270.

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The presented Pre-Error Adaptive Voltage Scaling (AVS) approach tunes the supply voltage of digital circuits dependent on the present Process, Voltage and Temperature variations as well as Aging (PVTA). By exploiting unused timing margin, produced by state-of-the-art worst-case designs, power consumption is minimized. Timing information of the circuit is obtained by in situ delay monitors (Pre-Error flip-flops), detecting late-arriving signals (pre-errors) in critical paths. Based on the occurrence of pre-errors, the voltage is adjusted by a low-overhead control unit connected to the on-chip voltage regulator. As the voltage is adapted during normal circuit operation (on-line), the randomness of the applied input pattern has to be considered. We developed a Markov chain model, based on transistor level simulations, to describe the resulting statistics of the closed-loop voltage control. With this model, the risk of overcritical voltage reductions and the effect of global and local variations on the closed-loop control can be analyzed. For an arithmetic circuit, synthesized in an industrial 65nm design-flow, an average power saving of 23% (including all overheads) is achieved for very low error rates below 1E-11.

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Wang, Chuankun, Yigang He, Yunfeng Jiang, and Lie Li. "An Anti-Interference Online Monitoring Method for IGBT Bond Wire Aging." Electronics 10, no. 12 (June 17, 2021): 1449. http://dx.doi.org/10.3390/electronics10121449.

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Due to the constant changes of the environment and load, the insulated-gate bipolar transistor (IGBT) module is subjected to a large amount of junction temperature (Tj) fluctuations, which often leads to damage to the bond wires. The monitoring parameters of IGBTs are often coupled with Tj, which increases the difficulty of monitoring IGBTs’ health status online. In this paper, based on the collector current (Ic) and collector-emitter on-state voltage (Vce_on) online monitoring circuit, an online monitoring method of IGBT bond wire aging against interference is proposed. First, the bond wire aging model is established, and the Vce_on is selected as the monitoring parameter. Secondly, taking a three-phase inverter circuit as an example, the Vce_on and Ic waveforms of the IGBT module are monitored in real time, and the process of online monitoring is introduced accordingly. Finally, the experimental results output by RT-LAB indicate that the method proposed in this paper can accurately identify the aging state of IGBT bond wires under different conditions.

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Zhang, Xin, Xiaohua Shi, Jiaoqi Wang, Zhongxin Xu, and Jinting He. "Enriched environment remedies cognitive dysfunctions and synaptic plasticity through NMDAR-Ca2+-Activin A circuit in chronic cerebral hypoperfusion rats." Aging 13, no. 16 (August 30, 2021): 20748–61. http://dx.doi.org/10.18632/aging.203462.

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42

Yu, Chun He, Chao Zhang, and Ying Bai. "A New Type Device of Detecting True and False Coin." Advanced Materials Research 429 (January 2012): 329–33. http://dx.doi.org/10.4028/www.scientific.net/amr.429.329.

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In order to reduce the loss of an automatic coin machine for using a 1-Yuan false coin, a new device is designed by applying the eddy current nondestructive testing technology. The device includes four modules: LC oscillating circuit module, signal processing module, microprocessor module and external control circuit module. The device identifies false coins by the frequency changing quantity of the circuit oscillation. For overcoming temperature drift, component aging and environment disturbance, the algorithm adopts the technology of background frequency updating and Median filter. The experiment shows the device has the character of stability, reliability and high accuracy.

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Yang, Lv, and Jing Hong Zhao. "The Design of DC Motor Excitation Regulation System Based on DSP." Advanced Materials Research 383-390 (November 2011): 5123–29. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.5123.

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The performance of excitation control system directly influences the motor’s movement characteristics. Currently, a lot of traditional excitation systems which use analog control circuits have the problem with their poor stability, aging components, slow response and great power lose. Aim to solve these problems, this text designs and implements a digital excitation regulation system based on DSP for DC motor. The regulation system takes full advantage of the powerful data processing ability of DSP chip for real-time rotational speed control of DC motor. This design is capable of ensuring the stability of the excitation system and improving the control efficiency, the circuit design is greatly simplified at the same time.

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Khelassi, A., P. Weber, D. Theilliol, and C. Aubrun. "Evaluation of Fault Tolerant System against Actuators Aging applied to Flotation Circuit." IFAC Proceedings Volumes 44, no. 1 (January 2011): 9947–52. http://dx.doi.org/10.3182/20110828-6-it-1002.01940.

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Miura-Mattausch, M., H. Miyamoto, H. Kikuchihara, T. K. Maiti, N. Rohbani, D. Navarro, and H. J. Mattausch. "Compact modeling of dynamic trap density evolution for predicting circuit-performance aging." Microelectronics Reliability 80 (January 2018): 164–75. http://dx.doi.org/10.1016/j.microrel.2017.12.003.

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Nguyen, Tien Anh, Stéphane Lefebvre, and Stéphane Azzopardi. "Effect of short circuit aging on safe operating area of SiC MOSFET." Microelectronics Reliability 88-90 (September 2018): 645–51. http://dx.doi.org/10.1016/j.microrel.2018.06.040.

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47

Afonso, Bruno, Pamela A. Silver, and Caroline M. Ajo-Franklin. "A synthetic circuit for selectively arresting daughter cells to create aging populations." Nucleic Acids Research 38, no. 8 (February 11, 2010): 2727–35. http://dx.doi.org/10.1093/nar/gkq075.

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Ma, Chenyue, Hans Jurgen Mattausch, Kazuya Matsuzawa, Seiichiro Yamaguchi, Teruhiko Hoshida, Masahiro Imade, Risho Koh, Takahiko Arakawa, and Mitiko Miura-Mattausch. "Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions." IEEE Transactions on Device and Materials Reliability 14, no. 3 (September 2014): 818–25. http://dx.doi.org/10.1109/tdmr.2014.2322673.

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Afacan, Engín, Günhan Dündar, Faík Başkaya, Alí Emre Pusane, and Mustafa Berke Yelten. "On Chip Reconfigurable CMOS Analog Circuit Design and Automation Against Aging Phenomena." ACM Transactions on Design Automation of Electronic Systems 24, no. 4 (July 24, 2019): 1–22. http://dx.doi.org/10.1145/3325069.

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Bulletti, Andrea, Lorenzo Capineri, Barrie D. Dunn, and Mara Bruzzi. "Investigation of Resistivity Variation of Printed Circuit Board Laminates Due to Aging." IEEE Transactions on Components, Packaging and Manufacturing Technology 2, no. 12 (December 2012): 2001–6. http://dx.doi.org/10.1109/tcpmt.2012.2217140.

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