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Relevant bibliographies by topics / Circuit design program / Dissertations / Theses

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Dissertations / Theses on the topic 'Circuit design program'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Zwolinski, M. "The system design of a hierarchical VLSI circuit simulator." Thesis, University of Southampton, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.375069.

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2

El-Sawi, Yehia Ali Reda Ali. "Parallel processing application to nonlinear microwave network design." Thesis, University of Kent, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.257300.

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3

Trinh, Stephen. "Component-derived manufacturing yield prediction in circuit card design and assembly." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/85774.

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Thesis: M.B.A., Massachusetts Institute of Technology, Sloan School of Management, 2013. In conjunction with the Leaders for Global Operations Program at MIT.<br>Thesis: S.M., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2013. In conjunction with the Leaders for Global Operations Program at MIT.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (page 51).<br>Circuit card manufacturing can be a highly risky and volatile proposition due to the placement of hundreds of small, high value components. Operator mistakes, design errors, and

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4

Rothenberger, James A. "Using object-oriented technology in the design of an integrated circuit macrocell registration database." Instructions for remote access. Click here to access this electronic resource. Access available to Kutztown University faculty, staff, and students only, 1999. http://www.kutztown.edu/library/services/remote_access.asp.

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Thesis (M.S.)--Kutztown University of Pennsylvania, 1999.<br>Source: Masters Abstracts International, Volume: 45-06, page: 3192. Typescript. Abstract precedes thesis as preliminary leaf. Includes bibliographical references (leaves 73-74).

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5

Schoellkopf, Jean-Pierre. "Siliciel : contributions à l'architecture des circuits intégrés et à la compilation du silicium." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00315393.

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Cette thèse présente des contributions dans les domaines de l'architecture des ordinateurs réalisés sous la forme d'un Circuit Intégré. Un assembleur de silicium, appelé LUBRICK, permet de décrire, dans un langage de programmation, la constitution d'un assemblage hiérarchisé de cellules pour réaliser la description complète des masques d'un Circuit Intégré. La compilation du silicium, discipline qui consiste à déduire les masques d'un circuit en partant d'une description fonctionnelle, est ici abordée sous un angle pratique, avec la présentation d'un compilateur prototype d'une forme de partie

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6

Lama, Filippo. "Design and characterization of a system for loss factor measurement in MV underground cable joints under temperature variation conditions." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2018. http://amslaurea.unibo.it/17165/.

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Cable joints are considered to be the weakest components of the MV cable network, being the ones with the highest failure rate. Furthermore, from statistical analysis of different cable network failure data, a noticeably increase in cable joint breakdowns has been showed during summer months. The request for Distribution System Operators to avoid line outages as much as possible indicates a significant need for non-invasive diagnostic technologies able to monitor the health condition of MV cable junctions. Moreover, a better knowledge is required on the main causes of the detected increase in

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7

Robino, Francesco. "A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA." Licentiate thesis, KTH, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-145521.

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Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embed

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8

Osseiran, Adam. "Définition, étude et conception d'un microprocesseur autotestable spécifique : cobra." Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00320884.

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Description des différentes étapes de la conception d'un microprocesseur pour le contrôle des automatismes de sécurité, en particulier pour les systèmes de transport. Ce microprocesseur est autotestable, c'est-à-dire capable de détecter ses propres erreurs. La conception du circuit est basée sur les hypothèses de pannes au niveau analytique dans la technologie NMOS. Les blocs fonctionnels «Strongly Fault Secure» et les contrôleurs «Strongly Code Disjoint» sont à la base des circuits «Self-checking», dits autotestables. Le circuit COBRA démontre la faisabilité d'un microprocesseur autotestable.

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9

So, Biu 1959. "THE METHODOLOGY AND IMPLEMENTATION OF RELAXATION METHOD TO INVESTIGATE ELECTRO-THERMAL INTERACTIONS IN SOLID-STATE INTEGRATED CIRCUITS." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276384.

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10

Sedláček, David. "Emulátor 3.5“ disketové mechaniky pomocí RS232 a SD paměťové karty." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2012. http://www.nusl.cz/ntk/nusl-219466.

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This thesis deals with the design of the 3,5" floppy drive emulator with ATMEGA microprocessor unit. The emulator has been designed according to the principles of designing electronic devices, there is also object-control application and firmware for a microcontroller, which supports MFM coding. The thesis also lists all the formats of data stored or transmitted along with some flowcharts.

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11

Vaško, Pavel. "Panelový měřicí přístroj." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219011.

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The master thesis includes a literature search, which is focused on questions around panel measure instruments for measuring analog voltage signals. There is the block diagram and the concept of measuring voltage values designed from collected information and defined requirements to the device. In the next step a design of the circuit diagram is created and published and consequently transferred into PCB. The whole board has been fabricated, assembled and tested. The firmware development starts with the definition of basic functional blocks for using of internal elements of the device, which i

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12

Newlands, D. A., and mikewood@deakin edu au. "Structured development of an asynchronous forth processor using trace theory." Deakin University. School of Sciences, 1989. http://tux.lib.deakin.edu.au./adt-VDU/public/adt-VDU20050915.140144.

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This thesis examines the use of a structured design methodology in the design of asynchronous circuits so that high level constructs can be specified purely in terms of signal exchanges and without the intrusion of lower level concepts. Trace theory is used to specify a multi-processor Forth machine at a high level then part of the design is further elaborated using trace theory operations to (insure that the behaviours of the lower level constructs will combine to give the high level specified behaviour without locking or other hazards. A novel form of threaded language to take advantage of

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13

Blackburn, Dane E. "A novel approach to calculating relative scattering parameter sensitivity in computer-aided design programs." Thesis, Virginia Polytechnic Institute and State University, 1988. http://hdl.handle.net/10919/80100.

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Relative sensitivity is a measure of the percentage change in a system parameter caused by a percentage change in a component parameter. The adjoint network method has previously been used by Monaco and Tiberio in the computation of relative scattering parameter sensitivity. A new approach is presented in this work which defines a bilinear equation and three constants that relate any component scattering parameter to any system scattering parameter. A computer-aided design program which implements this relative sensitivity in analysis and optimization is presented. Circuit analysis examples de

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14

Seo, Chung-Seok. "Physical Design of Optoelectronic System-on-a-Chip/Package Using Electrical and Optical Interconnects: CAD Tools and Algorithms." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-11102004-150844/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>David E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.

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15

Grover, Samir. "Solving layout compaction and wire-balancing problem using linear programming on the Monsoon multiprocessor." Thesis, Connect to online version, 1995. http://0-wwwlib.umi.com.mercury.concordia.ca/cr/concordia/fullcit?pMQ90885.

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16

Palanisamy, Karthikeyan. "High Level Preprocessor of a VHDL-based Design System." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4776.

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This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL -based DIADES system into a VHDL -based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL -based design system from Mentor Graphics. The high-level synthesis in the DIADES system includes two stages: data

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17

Wan, Wei. "A New Approach to the Decomposition of Incompletely Specified Functions Based on Graph Coloring and Local Transformation and Its Application to FPGA Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4698.

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The thesis presents a new approach to the decomposition of incompletely specified functions and its application to FPGA (Field Programmable Gate Array) mapping. Five methods: Variable Partitioning, Graph Coloring, Bond Set Encoding, CLB Reusing and Local Transformation are developed in order to efficiently perform decomposition and FPGA (Lookup-Table based FPGA) mapping. 1) Variable Partitioning is a high quality hemistic method used to find the "best" partitions, avoiding the very time consuming testing of all possible decomposition charts, which is impractical when there are many input varia

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18

Bodirwa, Kgashane Bethuel. "The use of computer simulations on grade eleven learners' performance in plants biodiversity, Mankweng Circuit." Thesis, 2020. http://hdl.handle.net/10386/3334.

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Thesis (M. Ed. (Science Education)) -- University of Limpopo, 2020<br>Learners’ performance largely depends on the pedagogy used. This study explored the use of Computer Simulations (CS) to teach plants biodiversity to grade eleven learners Mankweng Circuit. A randomised Solomon Four-Group design was used. Sixty-six learners from two schools equipped with computers were randomly assigned to the Experimental Group (EG), and 66 learners from two other schools without computers were the Control Group (CG). A performance pre- and post-test was used to the EG taught using CS and to the

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19

Hayward, Roger D. "Improving a sampled-data circuit simulator for Delta-Sigma modulator design." Thesis, 1992. http://hdl.handle.net/1957/36732.

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Delta-Sigma Modulator-based Analog-to-Digital converter design is an active area of research. New topologies require extensive simulations to verify their performance. A series of improvements were made to an existing circuit simulation package in order to speed the simulation process for the designer. Various examples of these improvements are presented in typical applications.<br>Graduation date: 1992

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20

Masimula, Steven Mandla. "Gene expression programming for logic circuit design." 2017. http://hdl.handle.net/10500/23617.

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Finding an optimal solution for the logic circuit design problem is challenging and time-consuming especially for complex logic circuits. As the number of logic gates increases the task of designing optimal logic circuits extends beyond human capability. A number of evolutionary algorithms have been invented to tackle a range of optimisation problems, including logic circuit design. This dissertation explores two of these evolutionary algorithms i.e. Gene Expression Programming (GEP) and Multi Expression Programming (MEP) with the aim of integrating their strengths into a new Genetic Prog

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21

Chen, Zai Xiang, and 陳在相. "Design of a windows-based load analysis program and relevant database for branch circuits lay-out in a industrial power distribution system design." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/27813704972338425888.

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