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Journal articles on the topic 'Circuit scheme'

Author: Grafiati

Published: 28 May 2022

Last updated: 30 July 2025

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1

Yang, Da Bin, Young Woo Lee, and Young-woo Lee. "Asymmetric Signal Scanning Scheme to Detect Invasive Attacks." Korean Institute of Smart Media 12, no. 1 (2023): 17–23. http://dx.doi.org/10.30693/smj.2023.12.1.17.

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Design-For-Security (DFS) methodology is to protect integrated circuits from physical attacks, and that can be implemented by adding a security circuit to detect abnormal external access. Among the abnormal accesses called invasive attack, microprobing and FIB circuit editing are classified as the most powerful methods because they have direct access. Microprobing deliberately inject defects into the wire of circuit through probes, or reads and changes data. FIB circuit editing is methods of reconnecting or destroying circuits to neutralize security circuits or to access data. Previous DFS met

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2

WAH WU, CHAI, GUO-QUN ZHONG, and LEON O. CHUA. "SYNCHRONIZING NONAUTONOMOUS CHAOTIC SYSTEMS WITHOUT PHASE-LOCKING." Journal of Circuits, Systems and Computers 06, no. 03 (1996): 227–41. http://dx.doi.org/10.1142/s0218126696000182.

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Pecora and Carroll1 have shown how two nonautonomous chaotic circuits driven by periodic forcing can be synchronized using the master-slave driving principle. However, in their scheme, the periodic forcing in both circuits needs to be phase-locked through some additional circuitry for the system to synchronize. In this paper, we show two ways in which this can be avoided. In the first scheme, the two circuits are connected in a master-slave driving configuration and the periodic forcing is included in the driving signal such that it eliminates the need for the slave circuit to have an external

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3

Jiao, Su Min, Cai Hong Wang, and Xue Mei Wang. "Large-Scale Analog Circuit Evolutionary Design Using a Real-Coded Scheme." Applied Mechanics and Materials 220-223 (November 2012): 2036–39. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.2036.

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Analog circuits are of great importance in electronic system design. Recent evolutionary design results are usually small-scale analog circuits. This paper proposes a real-coded mechanism and uses it in the large-scale analog circuit evolutionary design. The proposed scheme evolves the circuit topology and size to a uniformed continuous space, in which the circuit representation is closed and of causality. Experimental results show that the proposed scheme can work successfully on many analog circuits with different kinds of characteristics. Comparing with other evolutionary methods before, th

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Jurić-Grgić, Ivica, Tonći Modrić, and Marin Mandić. "Transient Linear Circuit Analysis Using Finite Element Technique." Applied Sciences 12, no. 19 (2022): 9554. http://dx.doi.org/10.3390/app12199554.

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In this paper, a novel algorithm for a transient linear circuit analysis based on the Finite Element Technique (FET) was established. The FET procedure allows a straightforward solution for complex electric circuits since it is based on the Finite Element Method (FEM) approach. The developed algorithm allows us to select various types of time integration schemes when forming a local system of equations for a coupled circuit finite element. To illustrate the basic principle of the developed FET-based algorithm and to perform transient analysis, a random coupled linear circuit was analyzed. Nume

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WANG, XINSHENG, YIZHE HU, LIANG HAN, JINGHU LI, CHENXU WANG, and MINGYAN YU. "A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME." Journal of Circuits, Systems and Computers 22, no. 08 (2013): 1350068. http://dx.doi.org/10.1142/s0218126613500680.

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Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (

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6

Tang, Xiao-Bin, and Masayoshi Tachibana. "A BIST Scheme for Dynamic Comparators." Electronics 11, no. 24 (2022): 4169. http://dx.doi.org/10.3390/electronics11244169.

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This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The proposed BIST scheme and the circuit under testing are realized at the transistor level. The proposed BIST scheme was simulated using HSPICE. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, six faults were injec

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Pan, Naiqiao, Tian Chen, Houjun Sun, and Xiangdong Zhang. "Electric-Circuit Realization of Fast Quantum Search." Research 2021 (July 26, 2021): 1–8. http://dx.doi.org/10.34133/2021/9793071.

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Quantum search algorithm, which can search an unsorted database quadratically faster than any known classical algorithms, has become one of the most impressive showcases of quantum computation. It has been implemented using various quantum schemes. Here, we demonstrate both theoretically and experimentally that such a fast search algorithm can also be realized using classical electric circuits. The classical circuit networks to perform such a fast search have been designed. It has been shown that the evolution of electric signals in the circuit networks is analogies of quantum particles random

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8

Chua, Leon. "Genesis of Chua's scheme." Izvestiya VUZ. Applied Nonlinear Dynamics 1, no. 3 (1993): 4–16. https://doi.org/10.18500/0869-6632-1993-1-3-4-16.

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The article is a systematic presentation of the sequence of technical steps that the author went through in developing a chaos-generating circuit. The design procedure, although clear in nature, could not have been invented without using some important properties of nonlinear circuits and their physical implementations.

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9

Al-Rufaee, F. M., B. A. Yakimovich, and V. V. Kuvshinov. "Comparative circuit analysis for piezoelectric generators in low-power applications." E3S Web of Conferences 592 (2024): 03010. http://dx.doi.org/10.1051/e3sconf/202459203010.

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This paper presents the results of experimental analysis of piezoelectric-based power conversion circuits under vibration. Three types of circuits were evaluated: a standard full bridge rectifier (S-FBR) circuit, a self power synchronous electrical charge extraction circuit (SECE-sp), and an optimized self power synchronous charge extraction circuit (SECEopt-sp). Experiments were conducted to evaluate the effectiveness of energy conversion under real operating conditions. The results showed that the SECEopt-sp scheme has the highest energy conversion effectiveness and stable output power, outp

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10

Zulkifli, Nur Shahirah, Nooraida Samsudin, Suzanna Ridzuan Aw, Wan Farah Hanan Wan Osman, Shahreen Kasim, and Tole Sutikno. "Centroidal-polygon: a new modified Euler to improve speed of resistor-inductor circuit equation." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 3 (2021): 1399. http://dx.doi.org/10.11591/ijeecs.v24.i3.pp1399-1404.

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Two types of first-order circuits are resistor-capacitor (RC) and resistorinductor (RL). This paper focuses on the RL circuit equation. The centroidalpolygon (CP) scheme will be tested using SCILAB 6.0 software. This new scheme (CP scheme) is addressed to improve the speed. For the first order circuit equation, the complexity is focused on the time complexity, which is speed of the time taken to complete the simulation in the electrical part. The CP scheme is compared with the previous studies, polygon (P) and harmonic-polygon (HP). The result shows that the CP scheme is less computational and

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11

Zulkifli, Nur Shahirah, Nooraida Samsudin, Aw Suzanna Ridzuan, Wan Farah Hanan Wan Osman, Shahreen Kasim, and Tole Sutikno. "Centroidal-polygon: a new modified Euler to improve speed of resistor-inductor circuit equation." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 3 (2021): 1399–404. https://doi.org/10.11591/ijeecs.v24.i3.pp1399-1404.

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Two types of first-order circuits are resistor-capacitor (RC) and resistorinductor (RL). This paper focuses on the RL circuit equation. The centroidalpolygon (CP) scheme will be tested using SCILAB 6.0 software. This new scheme (CP scheme) is addressed to improve the speed. For the first order circuit equation, the complexity is focused on the time complexity, which is speed of the time taken to complete the simulation in the electrical part. The CP scheme is compared with the previous studies, polygon (P) and harmonic-polygon (HP). The result shows that the CP scheme is less computational and

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12

Rangari, Faiz, and Irfan Landge. "EFFECT OF MOSFET ASPECT RATIO ON CURRENT MIRROR USING DIFFERENT CURRENT SOURCES." ICTACT Journal on Microelectronics 7, no. 3 (2021): 1199–204. https://doi.org/10.21917/ijme.2021.0206.

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A highly efficient current mirror circuit is the need of every analog integrated circuits. They are mainly used to bias amplifier stages in analog ICs. Current mirror circuit should provide constant, predictable and precise current. In order to do so reference current given to current mirror should be constant, predictable and precise. Objective of this paper is to discuss the various reference current generation schemes and their dependency on the Aspect Ratio of Current Mirror’s MOSFET. Current mirror circuit with Resistor based and MOSFET based reference current generation schemes is implem

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13

Wang, Xiaoyuan, Xinrui Zhang, Chuantao Dong, Shimul Kanti Nath, and Herbert Ho-Ching Iu. "Design and Application of Memristive Balanced Ternary Univariate Logic Circuit." Micromachines 14, no. 10 (2023): 1895. http://dx.doi.org/10.3390/mi14101895.

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This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme.

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14

Yakshin, S. V. "An analytical method for solving the problem of heat network load flow." Proceedings of Irkutsk State Technical University 25, no. 1 (2021): 80–96. http://dx.doi.org/10.21285/1814-3520-2021-1-80-96.

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The author aimed to develop an analytical solution to the problem of the load flow of a six-, eleven- and twelve-circuit heat network, as well as to solve the problem of optimisation of a multi-circuit heat network, including the choice of the objective function and the determination of a number of variable technical parameters. For accelerating the optimisation process, the method of decomposition of the heat network graph was used. Decomposition involves is cutting the network graph at some nodes for the transition of a multi-circuit scheme to a branched scheme in the form of a tree. Optimis

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15

Li, Chun Feng, Ke Ming Li, and Xiang Zhang. "Research on Circuit Design for Speed Adjusting Hardware of Brushless DC Motor Based on the Two-Dimensional Fuzzy Controller." Advanced Materials Research 705 (June 2013): 509–15. http://dx.doi.org/10.4028/www.scientific.net/amr.705.509.

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The essay first establishes the general design for intelligent rotary speed system of the brushless DC motors, then based on the general design scheme, two-dimensional fuzzy controller, adaptive current adjustor and mainly used hardware circuits are designed. The mainly used hardware circuit design includes the circuit design of current detecting circuit, voltage detecting circuit, high-speed optocoupler, motor driver circuit, zero-crossing comparator circuit, etc. At last the designed controller and hardware circuits are tested to achieve optimum effects for rotary speed control through valid

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16

Stankovic, Tatjana, Mile Stojcev, and Goran Djordjevic. "On VHDL synthesis of self-checking two-level combinational circuits." Facta universitatis - series: Electronics and Energetics 17, no. 1 (2004): 69–79. http://dx.doi.org/10.2298/fuee0401069s.

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Concurrent error detection (CED) is an important technique in the design of system in which dependability and data integrity are important. Using the separable code for CED has the advantage that no decoding is needed to get the normal output bits. In this paper, we address the problem of synthesizing totally self-checking two level combinational circuits starting from a VHDL description. Three schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a totally self-checking comparator. The second scheme for synthesizing combinational circuit

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17

Lee, Choongkeun, Taegun Yim, and Hongil Yoon. "A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM." Electronics 9, no. 11 (2020): 1769. http://dx.doi.org/10.3390/electronics9111769.

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As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge

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18

Ke, Jinkun, Jinbo Feng, Yuchao Huang, Zhaoliang Guan, Hangyu Xu, and Ming Zhao. "Design of Active Closed-loop Driver Chip for SiC." Journal of Physics: Conference Series 2625, no. 1 (2023): 012058. http://dx.doi.org/10.1088/1742-6596/2625/1/012058.

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Abstract The SiC active control scheme mainly uses phased control, which makes the circuit implementation complex and unfavorable to design due to the need for detection circuits. And the longer feedback delay will affect the accuracy of the control. In this paper, a closed-loop driving SiC scheme is proposed. By integrating the driver circuit, protection circuit, and detection circuit on one chip, the SiC drive current is controlled by a staged control scheme, which can reduce the switching loss with low current and voltage overcharge. The specific circuit design uses Hua Hong BCD350GE techno

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19

Li, Chunfeng, Dandan Sun, and Xiang Zhang. "Design and Research on Intelligent Electronic Meters with Hand Transcribers." Open Electrical & Electronic Engineering Journal 8, no. 1 (2014): 748–53. http://dx.doi.org/10.2174/1874129001408010748.

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The essay first establishes the general design scheme about software and hardware circuits of intelligent electronic meters with hand transcribers and elects the more advanced RN8209G multifunctional, anti-stealing , monophrase measurement chip as the energy measurement chip; then designs the main program flow chart of hardware and software in the systematic design scheme, such as the energy measurement chip , the current sample circuit, the voltage sample circuit, and hand transcriber, etc.

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20

Ren, Yuhan, Jinhao Wang, Runquan Meng, Tingting Li, Juan Chen, and Taotao Zhang. "A Hybrid Dynamic Voltage Sharing Scheme for Series-connected SiC MOSFETs with Single Gate Drive." Journal of Physics: Conference Series 2401, no. 1 (2022): 012052. http://dx.doi.org/10.1088/1742-6596/2401/1/012052.

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Abstract At present, the voltage level of a commercial SiC MOSFET can hardly meet the requirements of high-voltage field. For the sake of achieving the application of MOSFETs in high-voltage fields, the method of series-connected MOSFETs has become a practical and effective solution. However, multiple series-connected SiC MOSFETs face the problem of voltage unbalance, especially dynamic voltage unbalance. Generally, the problem of dynamic unbalance could be solved using load side voltage sharing schemes or the methods of gate side. This paper uses a hybrid dynamic voltage sharing scheme for th

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PARK, DONGKYU, SEOKSOO YOON, INHWA JUNG, and CHULWOO KIM. "NOISE-AWARE SPLIT-PATH DOMINO LOGIC AND ITS CLOCK DELAYING SCHEME." Journal of Circuits, Systems and Computers 16, no. 01 (2007): 139–54. http://dx.doi.org/10.1142/s0218126607003563.

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This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic pr

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Xu, Wei, and Ning Cao. "A General Chaotic Circuit Design and Hardware Implementation via the Inductance Integrators." Journal of Circuits, Systems and Computers 29, no. 10 (2019): 2050159. http://dx.doi.org/10.1142/s0218126620501595.

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This paper presents a scheme for the modified chaotic circuits based on inductance integration. In view of the fact that the DC resistance of an inductor in the circuit cannot be ignored, this way of constructing the circuits is provided that can eliminate its influence on the integral circuits. By means of cascading an inverting adder circuit and inductance integral circuit, the output signal of the integral circuit is fed back to the inverting adder circuit, and its additive term is artificially added to match the actual inductance integrated circuit to achieve integral circuit based on the

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23

Al-Rufaee, Faez M., Boris A. Yakimovich, Sergey P. Murovsky, Vladimir V. Kuvshinov, and Anton D. Kasnitsky. "A COMPARATIVE ANALYSIS OF PIEZOELECTRIC ENERGY HARVESTER CIRCUITS." Pacific Rim Countries Transportation System 1 (2025): 5–11. https://doi.org/10.31079/2415-8658-2025-1-5-11.

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In the article, various piezoelectric energy harvesting circuits including the standard full bridge rectifier (S-FBR), self-powered synchronous charge extraction (SECE) and optimized self-powered synchronous charge extraction (SECE-opt) circuits are discussed. The performance of each scheme, their ability to adapt to variable loads and overall power conversion characteristics were evaluated. The analysis showed that the self-powered SECE-opt scheme exhibits the highest efficiency due to its advanced switching technology and stable output power. It was experimentally found that the optimized SE

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Yan, Xu, Bin Lian, Yunhao Yang, et al. "A Ciphertext Reduction Scheme for Garbling an S-Box in an AES Circuit with Minimal Online Time." Symmetry 16, no. 6 (2024): 664. http://dx.doi.org/10.3390/sym16060664.

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The secure computation of symmetric encryption schemes using Yao’s garbled circuits, such as AES, allows two parties, where one holds a plaintext block m and the other holds a key k, to compute Enc(k,m) without leaking m and k to one another. Due to its wide application prospects, secure AES computation has received much attention. However, the evaluation of AES circuits using Yao’s garbled circuits incurs substantial communication overhead. To further improve its efficiency, this paper, upon observing the special structures of AES circuits and the symmetries of an S-box, proposes a novel ciph

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Zulkifli, Nur Shahirah, Nooraida Samsudin, and N. M. M. Yusof. "Improving Euler Method using Centroidal-Polygon Scheme for Better Accuracy in Resistor-Capacitor Circuit Equation." Journal of Physics: Conference Series 2319, no. 1 (2022): 012023. http://dx.doi.org/10.1088/1742-6596/2319/1/012023.

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Abstract A first-order ordinary differential equation (ODE) is a function with two variables defined in the xy-axis of a field. Various numerical methods, such as the Euler method, Runge-Kutta method, Heun’s method and others, are used to solve ODEs, with varying computational costs and accuracy. The Euler method can only solve the first derivative equation with the simplest implementation at the lowest cost of computation, but it produces less accurate results. This research focuses on improving the Euler method to increase its accuracy. A new scheme called Centroidal-Polygon (CP) is used in

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Kawal, Kevin, Steven Blair, Qiteng Hong, and Panagiotis N. Papadopoulos. "Selective Auto-Reclosing of Mixed Circuits Based on Multi-Zone Differential Protection Principle and Distributed Sensing." Energies 16, no. 6 (2023): 2558. http://dx.doi.org/10.3390/en16062558.

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Environmental concerns and economic constraints have led to increasing installations of mixed conductor circuits comprising underground cables (UGCs) and overhead transmission lines (OHLs). Faults on the OHL sections of such circuits are usually temporary, while there is a higher probability that faults on UGC sections are permanent. To maintain power system reliability and security, auto-reclose (AR) schemes are typically implemented to minimize outage duration after temporary OHL faults while blocking AR for UGC faults to prevent equipment damage. AR of a hybrid UCG–OHL transmission line, th

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Lobanov, D. K., T. G. Oreshenko, and A. E. Schmidt. "Algorithm for identifying RLC parameters." Spacecrafts & Technologies 7, no. 4 (2023): 279–87. http://dx.doi.org/10.26732/j.st.2023.4.06.

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The article discusses an algorithm capable of determining the substitution scheme of the investigated circuit and calculating the parameters of its elements without operator intervention, based on the admittance frequency characteristics. This algorithm enhances the functional capabilities of RLC meters and can be applied to solve practical problems related to identifying the substitution scheme of the investigated circuit. As an RLC meter measures the total resistance only at one or several fixed frequencies, obtaining an understanding of the substitution scheme from these measurements is cha

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Shubenko, Oleksandr, Oleksandr Senetskyi, and Mikola Babak. "BINARY ELECTRICAL GENERATING INSTALLATION FOR UTILIZATION HEAT OF BOILER FLUE GASES." Bulletin of the National Technical University "KhPI". Series: Hydraulic machines and hydraulic units, no. 1 (November 14, 2022): 15–24. http://dx.doi.org/10.20998/2411-3441.2022.1.03.

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The work is devoted to the development of modern thermal schemes for the production of electrical energy while utilizing the heat of flue gases from boilers of power units. On the example of a typical district boiler house, the parameters and potential of heat discharged into the atmosphere with the flue gases of boilers are investigated, and it is determined that they are sufficient to generate electrical energy by implementing the so-called organic Rankine cycles. To utilize the heat of exhaust gases with a temperature of 280 °С at a flow rate of 10 kg/s, a three-loop power generating plant

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Oh, Seokjin, Rina Yoon, and Kyeong-Sik Min. "Defect-Tolerant Memristor Crossbar Circuits for Local Learning Neural Networks." Nanomaterials 15, no. 3 (2025): 213. https://doi.org/10.3390/nano15030213.

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Local learning algorithms, such as Equilibrium Propagation (EP), have emerged as alternatives to global learning methods like backpropagation for training neural networks. EP offers the potential for more energy-efficient hardware implementation by utilizing only local neuron information for weight updates. However, the practical implementation of EP using memristor-based circuits has significant challenges due to the immature fabrication processes of memristors, resulting in defects and variability issues. Previous implementations of EP with memristor crossbars use two separate circuits for t

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Lin, Jie, Benjamin MacLellan, Sobhan Ghanbari, et al. "GraphiQ: Quantum circuit design for photonic graph states." Quantum 8 (August 28, 2024): 1453. http://dx.doi.org/10.22331/q-2024-08-28-1453.

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GraphiQ is a versatile open-source framework for designing photonic graph state generation schemes, with a particular emphasis on photon-emitter hybrid circuits. Built in Python, GraphiQ consists of a suite of design tools, including multiple simulation backends and optimization methods. The library supports scheme optimization in the presence of circuit imperfections, as well as user-defined optimization goals. Our framework thus represents a valuable tool for the development of practical schemes adhering to experimentally-relevant constraints. As graph states are a key resource for measureme

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Blaschenko, O. D., E. P. Razmenov, and I. M. Starkov. "Modernization of Control of Switching-on the Circuits of a Two-Circuit Pulse Current Generator." Elektronnaya Obrabotka Materialov 58, no. 1 (2022): 93–100. http://dx.doi.org/10.52577/eom.2022.58.1.93.

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A possibility of developing control devices for switching on circuits in double-circuit pulse cur-rent generators in various discharge-pulse technologies is shown. The advantages of using those devices in the technology of a high-voltage electrochemical explosion are described, which requires a specific energy input based on the time delays between switching on the circuits. A scheme is proposed for automatically starting the second circuit in a double-circuit pulse current generator, which provides smooth (non-discrete) adjustment of the time delay of operation and realizing a wider range of

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Cheng, Zhenggang, Peter Gunadisastra, and Amit Agrawal. "An Innovative Printed Circuit Board Power Delivery Scheme." International Symposium on Microelectronics 2011, no. 1 (2011): 000069–72. http://dx.doi.org/10.4071/isom-2011-ta2-paper3.

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In this paper, an innovative board power delivery scheme with two separate power planes merging at VRM (voltage regulator modular) has been studied. The two separate power planes provide power for two different core power rails with the same value. Compared to traditional board power delivery schemes such as two separate power planes with two VRMs or one shared power plane with one VRM, the new power delivery scheme has been found to be cost effective and have good performance for our application by using system level transient power noise simulation and analysis.

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Chuang, Ching-Chun, Chih-Chiang Hua, Chong-Yu Huang, and Li-Kai Jhou. "Modeling a Dual-Mode Controller Design for a Quasi-Resonant Flyback Converter." Applied Sciences 9, no. 9 (2019): 1860. http://dx.doi.org/10.3390/app9091860.

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The proposed system can overcome the disadvantage of a high peak current in quasi-resonant fly-back (QRF) converters when operated under heavy load conditions. The operating mode and control scheme of a QRF converter with dual-mode control were established and analyzed. The dual-mode control scheme not only enabled a valley-switching detection technique that satisfied the zero-voltage switching condition but also provided a constant frequency mechanism to reduce the conduction loss in QRF converters when operated in a continuous conduction mode and under heavy load conditions. The small-signal

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Zhong, Ruizhe, Junjie Ye, Zhentao Tang, et al. "PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling." Proceedings of the AAAI Conference on Artificial Intelligence 38, no. 15 (2024): 17087–95. http://dx.doi.org/10.1609/aaai.v38i15.29653.

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Pre-routing timing prediction has been recently studied for evaluating the quality of a candidate cell placement in chip design. It involves directly estimating the timing metrics for both pin-level (slack, slew) and edge-level (net delay, cell delay), without time-consuming routing. However, it often suffers from signal decay and error accumulation due to the long timing paths in large-scale industrial circuits. To address these challenges, we propose a two-stage approach. First, we propose global circuit training to pre-train a graph auto-encoder that learns the global graph embedding from c

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Chen, Wei. "Design and Improvement of Digital Communication System Based on EDA Platform." Journal of Physics: Conference Series 2396, no. 1 (2022): 012052. http://dx.doi.org/10.1088/1742-6596/2396/1/012052.

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Abstract The design of digital circuit systems based on EDA tools can greatly improve design efficiency. In this paper, a multi-mode communication signal modulation and demodulation system are designed with FPGA as the hardware carrier. Furthermore, this paper puts forward a teaching and experimental scheme of communication circuits, that is, using the EDA platform to realize different modulation and demodulation modes. The advantage of this scheme is that it can not only be realized in hardware, but also can analyze the performance accurately and that the waveform is intuitive. This scheme ca

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Li, Danqing, Huaguo Liang, Hong Zhang, et al. "BPath-RO: A Performance- and Area-Efficient In Situ Delay Measurement Scheme for Digital IC." Electronics 12, no. 23 (2023): 4853. http://dx.doi.org/10.3390/electronics12234853.

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Circuit delays are increasingly sensitive to process, voltage, temperature, and aging (PVTA) variations, severely impacting circuit performance. Accurate measurement of circuit delay is essential. However, the additional hardware structures for measuring circuit delay add to the critical path delay. To address this issue, this paper proposes a bypass-based ring oscillator (BPath-RO) that reduces the impact on the critical path delay by moving the added measurement control structures to the bypass. The proposed measurement scheme requires only two transistors inserted into the critical path, wh

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Chen, Shen Li, and C. K. Lee. "A Single-Chip Design for the Three-Phase BDCM System." Applied Mechanics and Materials 271-272 (December 2012): 742–46. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.742.

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In this work, we present a sensorless single-chip design for the three-phase brushless DC motors (BDCM) system, and which is implemented by a 0.35um CMOS process. A mixed-signal IC will be accomplished by the implementation of analog circuit and digital circuit in the same chip. Eventually, this chip system includes an analog circuit (Hall signal amplifier), a digital circuit (logic process block), and a frequency voltage converter (FVC) to complete the control & driving circuits. Experimental results are included to verify the proposed scheme.

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Geng, Yeliang, Jianping Hu, and Kaiyu Zou. "A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors." Open Electrical & Electronic Engineering Journal 8, no. 1 (2014): 306–15. http://dx.doi.org/10.2174/1874129001408010306.

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Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons betw

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Radko, I., V. Nalivayko, O. Okushko, and I. Bolbot. "Investigation of dependences of selectivity of devices of protection against the value of short circuit currents in electrical networks up to 1000 V." Energy and automation, no. 3(55) (June 23, 2021): 98–100. http://dx.doi.org/10.31548/energiya2021.03.098.

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According to PUE-2017, each group line must be protected against short circuits. Instant disconnection (cut-off) of the line in the event of short circuits provides an electromagnetic release of the circuit breaker. Reliable tripping is possible if the current of a single-phase short circuit is greater than the instantaneous tripping current. Today on the market are widely available circuit breakers with characteristics "B", "C" and "D", which are characterized by different multiplicities of the cut-off current of the electromagnetic release. Some European companies produce circuit breakers wi

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Cheng, Ye, and Jianhao Hu. "Random Error Reduction Scheme for Combinational Stochastic Circuit." Mathematical Problems in Engineering 2017 (2017): 1–14. http://dx.doi.org/10.1155/2017/4038765.

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In conventional stochastic computation, all the input streams are Bernoulli sequences (BSs), which may result in large random error. To reduce random error and improve computational accuracy, some other sequences have been reported as alternatives to BSs. However, these sequences only apply to the specific stochastic circuits, have difficulties in hardware generation, or have length constraints. To this end, new sequences without these disadvantages should be considered. This paper proposes the random error analysis method for stochastic computation based on autocorrelation sequence (AS), whic

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BATYGIN, YURIY, SVITLANA SHINDERUK, EVGEN CHAPLYGIN, and DENIS FENDRYKOV. "THE DIFFERENT APPROACHES TO THE TRANSFORMATION OF REACTIVE POWER INTO AN ACTIVE POWER." Herald of Khmelnytskyi National University. Technical sciences 319, no. 2 (2023): 27–35. http://dx.doi.org/10.31891/2307-5732-2023-319-1-27-35.

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The relevance of the development of modern problems of the electric power industry in connection with the depletion of the planet’s natural resources is undeniable and initiates the development of new physical and technical solutions with the practical use of known natural phenomena. The method of this work is to propose, justifying the expediency of a possible scheme of a resonant converter of reactive power into activity and conducting an analysis of the electromagnetic processes occurring in them. The proposed schemes combine the presence of resonant parallel and resonant circuit complexes.

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Kulshethra, Yogesh, and Manish Kule. "Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes." International Journal of Electrical and Electronics Research 7, no. 3 (2019): 11–18. http://dx.doi.org/10.37391/ijeer.070301.

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As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gat

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Wang, Youren, Zhiqiang Zhang, and Jiang Cui. "The Architecture and Circuital Implementation Scheme of a New Cell Neural Network for Analog Signal Processing." JUCS - Journal of Universal Computer Science 13, no. (9) (2007): 1344–53. https://doi.org/10.3217/jucs-013-09-1344.

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It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network SCCNN for analog signal processing circuits, designed the neural cell circuit, and developed the evolutionary design method of the SCCNN based on selfadapting genetic algorithm. In the architecture of new cellular neural network SCCNN, each neural cell connects with four neighborhood neural cells, the neural cell circuit and signal transfer line between neural cells are controlled by programmable switches. The validity

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Jeong, Jinsu, Sanguk Lee, and Rock-Hyun Baek. "Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors." Nanomaterials 14, no. 12 (2024): 1006. http://dx.doi.org/10.3390/nano14121006.

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The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat’s impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-e

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Duțu, I. C., T. Axinte, E. Maican, C. Nuțu, and M. Diaconu. "The use of double-acting cylinders in electro-hydraulic circuit." Technium: Romanian Journal of Applied Sciences and Technology 4, no. 5 (2022): 15–20. http://dx.doi.org/10.47577/technium.v4i5.6675.

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The paper presents aspects related use of double-acting cylinder. Besides, in the article are presented three hydraulic schemes that double acting cylinder. Meaning, two hydraulic circuits and one electro-hydraulic circuits. First hydraulic schemes has the following devices: fixed displacement pump, air filter, 4/3 way hand lever valve, tanks reservoir, filter and double acting cylinder (Cyli 1-1). However, second hydraulic scheme has the following devices: fixed displacement pump, 4/3 way hand lever valve, check valves, valve office and two double acting cylinders (Cyli 2-1 and Cyli 2-2). For

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Reva, Ihor, Oleh Todorov, and Maksim Bezzub. "Application of a neural network for determining the parameters of a transformer elimination circuit under the conditions of non-invasive monitoring." Electrical Engineering and Power Engineering, no. 1 (March 30, 2022): 19–29. http://dx.doi.org/10.15588/1607-6761-2022-1-2.

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Purpose. Application of a specially constructed neural network with the task of identifying the parameter substitution scheme in non-invasive monitoring conditions. Methodology. Use of electrical measurement methods by non-invasive monitoring, methods of identification and training of neural networks based on anterior and back propagation error, NARX networks. Findings. The power transformer is an important object of the power system of the electric shop substation. At the same time, frequent transitions from underload to partial overload mode are possible, which creates preconditions for the

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Heselhaus, T., and T. G. Noll. "A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement." Advances in Radio Science 9 (August 1, 2011): 247–53. http://dx.doi.org/10.5194/ars-9-247-2011.

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Abstract. The conventional sensing scheme of single-ended read-only-ports as integrated in 8T-SRAM cells suffers from low performance compared to double-ended complementary sensing schemes. In the proposed sensing scheme the pre-charge voltage of the single-ended read-bit-line is set to a level above the threshold voltage of the sensing device with an adjustable margin. This margin is minimized to speed up the read access on the one hand and kept large enough to provide a sufficient bit-line noise margin on the other hand. The pre-charge voltage level of the proposed sensing circuit tracks the

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Zandevakili, Hamed, Ali Mahani, and Mohsen Saneei. "An accurate and fast reliability analysis method for combinational circuits." COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 34, no. 3 (2015): 979–95. http://dx.doi.org/10.1108/compel-06-2014-0137.

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Purpose – One of the main issues which microelectronics industry encounter is reliability as feature sizes scale down to nano-design level. The purpose of this paper is to provide a probabilistic transfer matrix based to find the accurate and efficient method of finding circuit’s reliability. Design/methodology/approach – The proposed method provides a probabilistic description of faulty behavior and is well-suited to reliability and error susceptibility calculations. The proposed method offers accurate circuit reliability calculations in the presence of reconvergent fanout. Furthermore, a bin

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AZARYCHEV, Aleksandr N. N., and Il'ya N. SULYNENKOV. "Reliability Assessment of Circuit Breakers in Switchgear Schemes with Different Topologies." Elektrichestvo, no. 2 (2022): 38–46. http://dx.doi.org/10.24160/0013-5380-2022-2-38-46.

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The article discusses issues related to assessing the reliability of high-voltage circuit breakers in switchgear schemes with different topology of their design. A generalized formula is presented, using which it is possible to carry out calculations and further assessment of the failure flow parameter versus the switchgear scheme in which the circuit breaker is installed. To identify topological features, the standard switchgear schemes presented in the regulatory documents are analyzed. Five main types of circuit topologies and types of circuit breakers have been identified depending on the

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Baranovski, S. V., and Phyo Zaw Khaing. "Selection and optimization of a promising structural power scheme for the unmanned aerial vehicle fuselage made of polymer composite materials." Proceedings of Higher Educational Institutions. Маchine Building, no. 3 (756) (March 2023): 101–9. http://dx.doi.org/10.18698/0536-1044-2023-3-101-109.

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Fuselage is the main element of unmanned aerial vehicle, which parameters optimization could increase the structure strength and weight characteristics. Both the modern polymer composite materials with high specific characteristics and the advanced power circuits are able to assist in solving this problem. Selection and optimization of the structural power scheme of the unmanned aerial vehicle fuselage appear to be an urgent task. Structure loads under various flight and maneuver modes were analyzed. Eight fuselage structural power schemes were designed including classic, grid, auxetic and bio

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