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Journal articles on the topic 'Circuit scheme'
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1
WAH WU, CHAI, GUO-QUN ZHONG, and LEON O. CHUA. "SYNCHRONIZING NONAUTONOMOUS CHAOTIC SYSTEMS WITHOUT PHASE-LOCKING." Journal of Circuits, Systems and Computers 06, no. 03 (1996): 227–41. http://dx.doi.org/10.1142/s0218126696000182.
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Pecora and Carroll1 have shown how two nonautonomous chaotic circuits driven by periodic forcing can be synchronized using the master-slave driving principle. However, in their scheme, the periodic forcing in both circuits needs to be phase-locked through some additional circuitry for the system to synchronize. In this paper, we show two ways in which this can be avoided. In the first scheme, the two circuits are connected in a master-slave driving configuration and the periodic forcing is included in the driving signal such that it eliminates the need for the slave circuit to have an external periodic forcing signal. In addition, we can recover the periodic forcing signal at the slave circuit. In the second scheme, the two circuits are connected in a mutual coupling configuration. The two circuits will synchronize regardless of what the periodic forcing signals of the two circuits are. In particular, the two periodic forcing signals could have different phases, different frequencies, or different shapes. We discuss two interpretations of these synchronization schemes. First, we consider them as communication systems when the periodic forcing signal is replaced by a properly encoded information signal. We illustrate this in a physical circuit implementation. Second, we consider them as synchronization schemes for nonidentical systems by considering the external forcing signal as an error signal due to the difference between the two systems.
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Jiao, Su Min, Cai Hong Wang, and Xue Mei Wang. "Large-Scale Analog Circuit Evolutionary Design Using a Real-Coded Scheme." Applied Mechanics and Materials 220-223 (November 2012): 2036–39. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.2036.
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Analog circuits are of great importance in electronic system design. Recent evolutionary design results are usually small-scale analog circuits. This paper proposes a real-coded mechanism and uses it in the large-scale analog circuit evolutionary design. The proposed scheme evolves the circuit topology and size to a uniformed continuous space, in which the circuit representation is closed and of causality. Experimental results show that the proposed scheme can work successfully on many analog circuits with different kinds of characteristics. Comparing with other evolutionary methods before, the proposed scheme performs better on large-scale problems of circuit synthesis with higher search efficiency, lower computational complexity, and less computing time.
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WANG, XINSHENG, YIZHE HU, LIANG HAN, JINGHU LI, CHENXU WANG, and MINGYAN YU. "A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME." Journal of Circuits, Systems and Computers 22, no. 08 (2013): 1350068. http://dx.doi.org/10.1142/s0218126613500680.
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Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (CMS-Proposed) can acquire the same variation tolerance but consume less energy, compared with CMS-Bias with the original bias circuit (CMS-Original). Both the CMS schemes were fabricated in 180 nm CMOS technology. Simulation and measured results indicate that the two CMS interconnect circuits have the similar signal propagation delay when driving signal over a 10 mm line, but the CMS-Proposed offers about 9% reduction in energy/bit and 7.2% reduction in energy-delay-product (EDP) over the CMS-Original. Simulation results show that the two CMS schemes only change about 5% in delay when suffering intra-die variations, and have the same robustness against inter-die variations. Both simulation and measurements all show that the proposed bias circuits, employing self-biasing structure, contribute to robustness against supply variations to some extent. Jitter analysis presents the two CMS schemes have the same noise performance.
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Pan, Naiqiao, Tian Chen, Houjun Sun, and Xiangdong Zhang. "Electric-Circuit Realization of Fast Quantum Search." Research 2021 (July 26, 2021): 1–8. http://dx.doi.org/10.34133/2021/9793071.
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Quantum search algorithm, which can search an unsorted database quadratically faster than any known classical algorithms, has become one of the most impressive showcases of quantum computation. It has been implemented using various quantum schemes. Here, we demonstrate both theoretically and experimentally that such a fast search algorithm can also be realized using classical electric circuits. The classical circuit networks to perform such a fast search have been designed. It has been shown that the evolution of electric signals in the circuit networks is analogies of quantum particles randomly walking on graphs described by quantum theory. The searching efficiencies in our designed classical circuits are the same to the quantum schemes. Because classical circuit networks possess good scalability and stability, the present scheme is expected to avoid some problems faced by the quantum schemes. Thus, our findings are advantageous for information processing in the era of big data.
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Zulkifli, Nur Shahirah, Nooraida Samsudin, Suzanna Ridzuan Aw, Wan Farah Hanan Wan Osman, Shahreen Kasim, and Tole Sutikno. "Centroidal-polygon: a new modified Euler to improve speed of resistor-inductor circuit equation." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 3 (2021): 1399. http://dx.doi.org/10.11591/ijeecs.v24.i3.pp1399-1404.
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Two types of first-order circuits are resistor-capacitor (RC) and resistorinductor (RL). This paper focuses on the RL circuit equation. The centroidalpolygon (CP) scheme will be tested using SCILAB 6.0 software. This new scheme (CP scheme) is addressed to improve the speed. For the first order circuit equation, the complexity is focused on the time complexity, which is speed of the time taken to complete the simulation in the electrical part. The CP scheme is compared with the previous studies, polygon (P) and harmonic-polygon (HP). The result shows that the CP scheme is less computational and an alternative to solve the first order circuit equation, and get the result quickly compared with the previous research.
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Li, Chun Feng, Ke Ming Li, and Xiang Zhang. "Research on Circuit Design for Speed Adjusting Hardware of Brushless DC Motor Based on the Two-Dimensional Fuzzy Controller." Advanced Materials Research 705 (June 2013): 509–15. http://dx.doi.org/10.4028/www.scientific.net/amr.705.509.
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The essay first establishes the general design for intelligent rotary speed system of the brushless DC motors, then based on the general design scheme, two-dimensional fuzzy controller, adaptive current adjustor and mainly used hardware circuits are designed. The mainly used hardware circuit design includes the circuit design of current detecting circuit, voltage detecting circuit, high-speed optocoupler, motor driver circuit, zero-crossing comparator circuit, etc. At last the designed controller and hardware circuits are tested to achieve optimum effects for rotary speed control through validation of experimental devices.
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Yakshin, S. V. "An analytical method for solving the problem of heat network load flow." Proceedings of Irkutsk State Technical University 25, no. 1 (2021): 80–96. http://dx.doi.org/10.21285/1814-3520-2021-1-80-96.
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The author aimed to develop an analytical solution to the problem of the load flow of a six-, eleven- and twelve-circuit heat network, as well as to solve the problem of optimisation of a multi-circuit heat network, including the choice of the objective function and the determination of a number of variable technical parameters. For accelerating the optimisation process, the method of decomposition of the heat network graph was used. Decomposition involves is cutting the network graph at some nodes for the transition of a multi-circuit scheme to a branched scheme in the form of a tree. Optimisation of each branched circuit was carried out by the dynamic programming method, as a result of which new values of the variable parameters were obtained at the current iteration. Next, the author returned to the multi-circuit scheme to solve the load flow problem and calculate the value of the objective function. The iterative convergence of the decomposition method was not mathematically proven. The author proposed a method for splitting the graph, which eliminates the decomposition procedure when optimising a heat network. The following methods were applied: mathematical modelling of the hydraulic circuit, graph splitting method and the analytical method for solving the algebraic equation of the fourth degree. The following results were achieved: a scheme of the minimum element of a multi-circuit heat network was determined, the possibility of series and parallel circuits of minimum elements was shown, and analytical dependencies for the problem of load flow of a heat network of these schemes were obtained. The proposed analytical solution of the load flow problem for a multi-circuit heat network allows the problem of calculating a complex network to be reduced to the calculation of several minimum elements, which significantly reduces the amount of computational work when modelling a hydraulic circuit. The provided examples show that the calculation error does not exceed 3%.
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Stankovic, Tatjana, Mile Stojcev, and Goran Djordjevic. "On VHDL synthesis of self-checking two-level combinational circuits." Facta universitatis - series: Electronics and Energetics 17, no. 1 (2004): 69–79. http://dx.doi.org/10.2298/fuee0401069s.
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Concurrent error detection (CED) is an important technique in the design of system in which dependability and data integrity are important. Using the separable code for CED has the advantage that no decoding is needed to get the normal output bits. In this paper, we address the problem of synthesizing totally self-checking two level combinational circuits starting from a VHDL description. Three schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a totally self-checking comparator. The second scheme for synthesizing combinational circuits with CED uses Bose-Lin code. The third scheme is based on parity codes on the outputs of a combinational circuit. The area overheads and operating speed decreases for seven combinational circuits of standard architecture are reported in this paper.
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PARK, DONGKYU, SEOKSOO YOON, INHWA JUNG, and CHULWOO KIM. "NOISE-AWARE SPLIT-PATH DOMINO LOGIC AND ITS CLOCK DELAYING SCHEME." Journal of Circuits, Systems and Computers 16, no. 01 (2007): 139–54. http://dx.doi.org/10.1142/s0218126607003563.
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This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han–Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.
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Wilson, P. R. "Modeling the Non Linear Behavior of a Magnetic Fault Current Limiter." Advanced Electromagnetics 4, no. 3 (2015): 1. http://dx.doi.org/10.7716/aem.v4i3.265.
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Fault Current Limiters are used in a wide array of applications from small circuit protection at low power levels to large scale high power applications which require superconductors and complex control circuitry. One advantage of passive fault current limiters (FCL) is the automatic behavior that is dependent on the intrinsic properties of the circuit elements rather than on a complex feedback control scheme making this approach attractive for low cost applications and also where reliability is critical. This paper describes the behavioral modeling of a passive Magnetic FCL and its potential application in practical circuits.
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Lee, Choongkeun, Taegun Yim, and Hongil Yoon. "A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM." Electronics 9, no. 11 (2020): 1769. http://dx.doi.org/10.3390/electronics9111769.
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As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.
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Li, Chunfeng, Dandan Sun, and Xiang Zhang. "Design and Research on Intelligent Electronic Meters with Hand Transcribers." Open Electrical & Electronic Engineering Journal 8, no. 1 (2014): 748–53. http://dx.doi.org/10.2174/1874129001408010748.
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The essay first establishes the general design scheme about software and hardware circuits of intelligent electronic meters with hand transcribers and elects the more advanced RN8209G multifunctional, anti-stealing , monophrase measurement chip as the energy measurement chip; then designs the main program flow chart of hardware and software in the systematic design scheme, such as the energy measurement chip , the current sample circuit, the voltage sample circuit, and hand transcriber, etc.
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Nosker, Zachary, Yasunori Kobori, Haruo Kobayashi, et al. "A High Efficiency, Extended Load Range Boost Regulator Optimized Forenergy Harvesting Applications." Key Engineering Materials 534 (January 2013): 206–19. http://dx.doi.org/10.4028/www.scientific.net/kem.534.206.
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A small, low power bootstrapped boost regulator is introduced that can start upwith an input voltage of 240mV and achieve a maximum efficiency of 96%. The proposed circuituses two separate control schemes for startup and steady-state operation. A xed-frequencyoscillator is used to initially start up the circuit and raise the output voltage. Once the outputvoltage has reached a level adequate to bias the internal circuitry, a constant-on-time stylehysteretic control scheme is used, which helps increase system efficiency compared to using aconventional Pulse-Width-Modulated control scheme. While maintaining a high efficiency, theproposed circuit only requires 3 external components|2 capacitors (input and output) and aninductor. The e ectiveness of this approach is shown through Spectre simulation results.
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Cheng, Zhenggang, Peter Gunadisastra, and Amit Agrawal. "An Innovative Printed Circuit Board Power Delivery Scheme." International Symposium on Microelectronics 2011, no. 1 (2011): 000069–72. http://dx.doi.org/10.4071/isom-2011-ta2-paper3.
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In this paper, an innovative board power delivery scheme with two separate power planes merging at VRM (voltage regulator modular) has been studied. The two separate power planes provide power for two different core power rails with the same value. Compared to traditional board power delivery schemes such as two separate power planes with two VRMs or one shared power plane with one VRM, the new power delivery scheme has been found to be cost effective and have good performance for our application by using system level transient power noise simulation and analysis.
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Cheng, Ye, and Jianhao Hu. "Random Error Reduction Scheme for Combinational Stochastic Circuit." Mathematical Problems in Engineering 2017 (2017): 1–14. http://dx.doi.org/10.1155/2017/4038765.
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In conventional stochastic computation, all the input streams are Bernoulli sequences (BSs), which may result in large random error. To reduce random error and improve computational accuracy, some other sequences have been reported as alternatives to BSs. However, these sequences only apply to the specific stochastic circuits, have difficulties in hardware generation, or have length constraints. To this end, new sequences without these disadvantages should be considered. This paper proposes the random error analysis method for stochastic computation based on autocorrelation sequence (AS), which is more general than the conventional one based on BS. The analysis results show that we can use the proper ASs as input streams of stochastic circuits to reduce random error. On the basis of that conclusion, we propose the random error reduction scheme based on maximal concentrated autocorrelation sequence (MCAS) and BS, both of which are ASs. MCAS and BS are applicable to any combinational stochastic circuit, are easily generated by hardware, and have no length constraints, which avoid the disadvantages of sequences in the previous work. Moreover, we apply the proposed random error reduction scheme into several typical stochastic circuits as case studies. The simulation results confirm the effectiveness of the proposed scheme.
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Xu, Wei, and Ning Cao. "A General Chaotic Circuit Design and Hardware Implementation via the Inductance Integrators." Journal of Circuits, Systems and Computers 29, no. 10 (2019): 2050159. http://dx.doi.org/10.1142/s0218126620501595.
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This paper presents a scheme for the modified chaotic circuits based on inductance integration. In view of the fact that the DC resistance of an inductor in the circuit cannot be ignored, this way of constructing the circuits is provided that can eliminate its influence on the integral circuits. By means of cascading an inverting adder circuit and inductance integral circuit, the output signal of the integral circuit is fed back to the inverting adder circuit, and its additive term is artificially added to match the actual inductance integrated circuit to achieve integral circuit based on the actual inductor which can offset the effect of its DC resistance. In order to verify the generality of the design, the process of designing Lorenz chaotic circuit is given and its attractors can also be observed from the oscilloscope.
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Shieh, Yeong-Ruey, and Cheng-Wen Wu. "Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults." VLSI Design 5, no. 4 (1998): 357–72. http://dx.doi.org/10.1155/1998/24951.
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We present in this paper an approach to designing partially strongly code-disjoint (PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in addition to gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only a small number of extra transistors for monitoring abnormal static currents, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry not only can detect the faults in the functional circuit but also can detect or tolerate faults in itself, making it a good candidate for checker design. Switch and circuit level simulations were performed on a sample circuit, and a sample 4-out-of-8 code checker chip using the proposed technique has been designed, fabricated, and tested, showing the correctness of the method. Performance penalty is reduced by a novel BiCMOS checker circuit.
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Blaschenko, O. D., E. P. Razmenov, and I. M. Starkov. "Modernization of Control of Switching-on the Circuits of a Two-Circuit Pulse Current Generator." Elektronnaya Obrabotka Materialov 58, no. 1 (2022): 93–100. http://dx.doi.org/10.52577/eom.2022.58.1.93.
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A possibility of developing control devices for switching on circuits in double-circuit pulse cur-rent generators in various discharge-pulse technologies is shown. The advantages of using those devices in the technology of a high-voltage electrochemical explosion are described, which requires a specific energy input based on the time delays between switching on the circuits. A scheme is proposed for automatically starting the second circuit in a double-circuit pulse current generator, which provides smooth (non-discrete) adjustment of the time delay of operation and realizing a wider range of delay times
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Kulshethra, Yogesh, and Manish Kule. "Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes." International Journal of Electrical and Electronics Research 7, no. 3 (2019): 11–18. http://dx.doi.org/10.37391/ijeer.070301.
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As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gating scheme with 45nm technology parameters. The simulation results by using this scheme in BPTM 45nm technology with supply voltage of 0.9V at room temperature shows that leakage reduction can be improved by 47.14% as on comparison with single transistor gating scheme on comparing with conventional scheme Also, another novel approach has been analyzed with diode based stacking power gating scheme for further reduction in leakage power. The simulation results depicts that the analyzed design leads to efficient carry look ahead adder circuit in terms of leakage power, active power and delay.
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Chuang, Ching-Chun, Chih-Chiang Hua, Chong-Yu Huang, and Li-Kai Jhou. "Modeling a Dual-Mode Controller Design for a Quasi-Resonant Flyback Converter." Applied Sciences 9, no. 9 (2019): 1860. http://dx.doi.org/10.3390/app9091860.
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The proposed system can overcome the disadvantage of a high peak current in quasi-resonant fly-back (QRF) converters when operated under heavy load conditions. The operating mode and control scheme of a QRF converter with dual-mode control were established and analyzed. The dual-mode control scheme not only enabled a valley-switching detection technique that satisfied the zero-voltage switching condition but also provided a constant frequency mechanism to reduce the conduction loss in QRF converters when operated in a continuous conduction mode and under heavy load conditions. The small-signal equivalent circuit model of QRF converter circuits was constructed using an average approximation method. The technological advancement of a QRF converter with a dual-mode controller was presented in this study. The circuit simulation result of the proposed QRF converter with a mix control scheme proved that the derived circuit component parameters meet the requirements of the converter.
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Geng, Yeliang, Jianping Hu, and Kaiyu Zou. "A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors." Open Electrical & Electronic Engineering Journal 8, no. 1 (2014): 306–15. http://dx.doi.org/10.2174/1874129001408010306.
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Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons between conventional MCML and proposed power-gating MCML circuits are carried out. The 1-bit MCML full adder based on the proposed scheme nearly saves 36% of energy dissipations with respect to no-power-gating MCML one, for a power-gating activity of 0.6. Moreover, the proposed power-gating MCML circuit also has a great advantage in power dissipations in high frequency regions compared with the power-gating static CMOS ones. The power consumption of the MCML 1-bit full adder based on the proposed scheme is 63.2%, 44.8%, and 36.97% compared with the powergating static CMOS one when the operating frequency is 1GHz, 1.5GHz, and 2GHz, respectively.
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Chen, Shen Li, and C. K. Lee. "A Single-Chip Design for the Three-Phase BDCM System." Applied Mechanics and Materials 271-272 (December 2012): 742–46. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.742.
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In this work, we present a sensorless single-chip design for the three-phase brushless DC motors (BDCM) system, and which is implemented by a 0.35um CMOS process. A mixed-signal IC will be accomplished by the implementation of analog circuit and digital circuit in the same chip. Eventually, this chip system includes an analog circuit (Hall signal amplifier), a digital circuit (logic process block), and a frequency voltage converter (FVC) to complete the control & driving circuits. Experimental results are included to verify the proposed scheme.
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Radko, I., V. Nalivayko, O. Okushko, and I. Bolbot. "Investigation of dependences of selectivity of devices of protection against the value of short circuit currents in electrical networks up to 1000 V." Energy and automation, no. 3(55) (June 23, 2021): 98–100. http://dx.doi.org/10.31548/energiya2021.03.098.
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According to PUE-2017, each group line must be protected against short circuits. Instant disconnection (cut-off) of the line in the event of short circuits provides an electromagnetic release of the circuit breaker. Reliable tripping is possible if the current of a single-phase short circuit is greater than the instantaneous tripping current. Today on the market are widely available circuit breakers with characteristics "B", "C" and "D", which are characterized by different multiplicities of the cut-off current of the electromagnetic release. Some European companies produce circuit breakers with other characteristics, which greatly expands the possibilities protection of electrical equipment. The difficulty in organizing the selectivity of protection is that the circuit breakers of modular design when switching off short circuits are characterized by the same switching time (not more than 0.05 s). The purpose of the research is to find ways to organize the selectivity of protection in electrical networks with voltage up to 1000 V using reliable values of short-circuit currents. In networks with a voltage of up to 1000 V, the current of a single-phase short circuit can be calculated fairly accurately if the exact values of all sections of the electrical network are known. In practice, it is not always possible to obtain reliable data on the numerical characteristics of the 0.4 kV network to which a new energy facility is connected. Therefore, it is proposed to consider part of the network as an active quadrupole, the characteristics of which are obtained by measurements at the point of connection. For further calculations it is necessary to know the voltage at the clamps of the four-pole scheme and the internal impedance. Based on the theory of four-pole scheme, you can get the original data for calculations without calculating the internal parameters of four-poles scheme. Thus, it is proposed to use a hybrid method for estimating the magnitude of probable short-circuit currents in electrical networks up to 1000 V when designing new energy facilities. Credible values of short-circuit currents will allow to organize selective protection of electric networks.
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Bulacio, M. F., T. A. González, G. Marinelli, R. Alonso, and H. E. Tacca. "Power-Integrated Circuit Active Leakage Current Detector." Advances in Power Electronics 2012 (May 29, 2012): 1–8. http://dx.doi.org/10.1155/2012/270680.
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Most of the failures of induction motors become insulation faults, causing a permanent damage. Using differential current transformers, a system capable of insulation fault detection was developed, based on the differential relay protection scheme. Both signal injection and fault detection circuitry were integrated in a single chip. The proposed scheme is faster than other existing protection and not restricted to protect induction motors, but several other devices (such as IGBTs) and systems. This paper explains the principle of operation of fault protection scheme and analyzes an integrated implementation through simulations and experimental results. A power-integrated circuit (PIC) implementation is presented.
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Reva, Ihor, Oleh Todorov, and Maksim Bezzub. "Application of a neural network for determining the parameters of a transformer elimination circuit under the conditions of non-invasive monitoring." Electrical Engineering and Power Engineering, no. 1 (March 30, 2022): 19–29. http://dx.doi.org/10.15588/1607-6761-2022-1-2.
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Purpose. Application of a specially constructed neural network with the task of identifying the parameter substitution scheme in non-invasive monitoring conditions. Methodology. Use of electrical measurement methods by non-invasive monitoring, methods of identification and training of neural networks based on anterior and back propagation error, NARX networks. Findings. The power transformer is an important object of the power system of the electric shop substation. At the same time, frequent transitions from underload to partial overload mode are possible, which creates preconditions for the development of undesirable phenomena in transformers. Monitoring of the power transformer based on control of its substitution scheme, allows to pass to control of its basic parameters irrespective of an operating mode. Non-invasive monitoring works well in the context of the task, because research shows that the parameters of voltage and current, which it operates well reflect the dependence on changes in the parameters of the substitution scheme. Based on T equivalent the substitution scheme can detect and predict changes in parameters substitution schemes according to the parameters of the current and voltage regime flowing in this system. Many neural networks will work out the calculation of electrical and electrotechnical equivalent circuits as a task of identifying the parameters of electrical circuits in static conditions. In the process of identification, the ability of neural networks of different designs to identify one of the substitution scheme parameters, to resist damage was tested, which corrected the value of an unknown parameter. The experiment made it possible to obtain data for comparing the effectiveness of various architectures of neural networks in relation to the real parameters of the equivalent circuit. Concretizing the obtained results, we say that the NARX architecture is able to identify parameters in standard modes for all elements of the substitution circuit, which further opens up opportunities for its improvement in the calculation of nonlinear elements of the transformer when operating in a saturated state. Originality. It is established that the neural boundaries studied in the work are able to determine the parameters of the replacement circuit of a transformer or electric machine in static operating modes, which allows in the future to monitor the state of windings and magnetic circuit according to their values. Practical value. Using a neural network in the monitoring system allows you to get clear values of the equivalent circuit parameters, regardless of the mode, the proposed method significantly reduces the amount of time spent on monitoring the transformer parameters, allows you to control the power level, and, if necessary, reduce the amount of information required for the transformer monitoring.
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Zandevakili, Hamed, Ali Mahani, and Mohsen Saneei. "An accurate and fast reliability analysis method for combinational circuits." COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 34, no. 3 (2015): 979–95. http://dx.doi.org/10.1108/compel-06-2014-0137.
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Purpose – One of the main issues which microelectronics industry encounter is reliability as feature sizes scale down to nano-design level. The purpose of this paper is to provide a probabilistic transfer matrix based to find the accurate and efficient method of finding circuit’s reliability. Design/methodology/approach – The proposed method provides a probabilistic description of faulty behavior and is well-suited to reliability and error susceptibility calculations. The proposed method offers accurate circuit reliability calculations in the presence of reconvergent fanout. Furthermore, a binary probability matrix is used to not only resolve signals correlation problem but also improve the accuracy of the obtained reliability in the presence of reconverging signals. Findings – The results provide the accuracy and computation time of reliability evaluation for ISCAS85 benchmark schemes. Also, simulations have been conducted on some digital circuits involving LGSynth’91 circuits. Simulation results show that proposed solution is a fast method with less complexity and gives an accurate reliability value in comparison with other methods. Originality/value – The proposed method is the only scheme giving the low calculation time with high accuracy compared to other schemes. The library-based method also is able to evaluate the reliability of every scheme independent from its circuit topology. The comparison exhibits that a designer can save its evaluation time in terms of performance and complexity.
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Heselhaus, T., and T. G. Noll. "A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement." Advances in Radio Science 9 (August 1, 2011): 247–53. http://dx.doi.org/10.5194/ars-9-247-2011.
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Abstract. The conventional sensing scheme of single-ended read-only-ports as integrated in 8T-SRAM cells suffers from low performance compared to double-ended complementary sensing schemes. In the proposed sensing scheme the pre-charge voltage of the single-ended read-bit-line is set to a level above the threshold voltage of the sensing device with an adjustable margin. This margin is minimized to speed up the read access on the one hand and kept large enough to provide a sufficient bit-line noise margin on the other hand. The pre-charge voltage level of the proposed sensing circuit tracks the threshold voltage of the sensing device under process variations in order to maintain a minimum required bit-line noise margin. To avoid unnecessary bit-line discharging, the proposed sensing scheme employs a modified 8T-SRAM cell. Compared to the conventional 8T-SRAM cell, the read port of the proposed cell provides a virtual ground line running in parallel to the bit-lines. An internal driver of the sensing circuit releases the virtual ground line during the evaluation period to prevent the charge dissipation resulting in a raised voltage level. The reduced pre-charge level and the increased virtual ground lead to a reduced bit-line voltage swing and thus a bit-line power reduction. Access time, energy dissipation, and noise margin of the proposed sensing circuit are compared with conventional sensing circuits from the literature for different numbers of memory cells connected to the bit-line. It is shown, that for a specific number of memory cells per bit-line the proposed circuit achieves fastest access time at low power operation.
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Mei, Feng Na, and Peng Jun Wang. "Design of Ternary Clocked Adiabatic Synchronous Reversible Counter." Applied Mechanics and Materials 88-89 (August 2011): 154–59. http://dx.doi.org/10.4028/www.scientific.net/amm.88-89.154.
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Based on the study of synchronous counter and adiabatic circuits, a new design scheme of ternary adiabatic synchronous reversible counter is proposed. According to the theory of three essential circuit elements, circuit structure of four-bit ternary adiabatic synchronous reversible counter is realized by using NMOS transistors with different thresholds and cross-storage structure and combining with the principle of energy recovery. Computer simulation results indicate that the designed circuits have correct logic function. Compared with traditional CMOS counter, the average power consumption of circuits saves up to 67.5%.
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Zhu, Jun, Wan Kui Li, Hai Xing Wang, and Li Li Han. "The Hardware System Design of PMSM Controller Based on DSP2812." Applied Mechanics and Materials 273 (January 2013): 454–59. http://dx.doi.org/10.4028/www.scientific.net/amm.273.454.
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For the efficiency of PMSM, in the paper the matched controller was developed to improve the servo performance of permanent magnet synchronous servo system. According to the basic principle of vector control for PMSM, the hardware system of PMSM controller was constituted based on TMS320F2812, it contains power drive circuit, control circuit, feedback circuit and other auxiliary circuits. It can provide reference scheme for the design of PMSM controller, and laid the foundation for the industrial production of the PMSM controller.
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Ghavami, Behnam. "Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no. 3 (2018): 1189–203. http://dx.doi.org/10.1108/compel-03-2016-0118.
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Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.
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AZARYCHEV, Aleksandr N. N., and Il'ya N. SULYNENKOV. "Reliability Assessment of Circuit Breakers in Switchgear Schemes with Different Topologies." Elektrichestvo, no. 2 (2022): 38–46. http://dx.doi.org/10.24160/0013-5380-2022-2-38-46.
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The article discusses issues related to assessing the reliability of high-voltage circuit breakers in switchgear schemes with different topology of their design. A generalized formula is presented, using which it is possible to carry out calculations and further assessment of the failure flow parameter versus the switchgear scheme in which the circuit breaker is installed. To identify topological features, the standard switchgear schemes presented in the regulatory documents are analyzed. Five main types of circuit topologies and types of circuit breakers have been identified depending on the type of switched connections. For carrying out comparative calculations, one typical option was selected for each type of circuit topology. The distribution of circuit breakers by types in these schemes is presented. Calculations of the circuit breaker failure rates in schemes with the same initial data and with breaking down by types are carried out. Conclusions on the extent to which various types of schemes influence the reliability of high-voltage circuit breakers both as a whole and separately, depending on the type of switched connection are presented.
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Chamberland, Christopher, and Andrew W. Cross. "Fault-tolerant magic state preparation with flag qubits." Quantum 3 (May 20, 2019): 143. http://dx.doi.org/10.22331/q-2019-05-20-143.
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Magic state distillation is one of the leading candidates for implementing universal fault-tolerant logical gates. However, the distillation circuits themselves are not fault-tolerant, so there is additional cost to first implement encoded Clifford gates with negligible error. In this paper we present a scheme to fault-tolerantly and directly prepare magic states using flag qubits. One of these schemes requires only three ancilla qubits, even with noisy Clifford gates. We compare the physical qubit and gate cost of our scheme to the magic state distillation protocol of Meier, Eastin, and Knill (MEK), which is efficient and uses a small stabilizer circuit. For low enough noise rates, we show that in some regimes the overhead can be improved by several orders of magnitude compared to the MEK scheme which uses Clifford operations encoded in the codes considered in this work.
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Chen, Shu Wang, Shu Hai Wang, and Xiao Qin Xie. "Design of Current Temperature Transmitter Circuit." Applied Mechanics and Materials 63-64 (June 2011): 886–90. http://dx.doi.org/10.4028/www.scientific.net/amm.63-64.886.
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The temperature transmitter is a kind of device circuit, which is made up of temperature sensor and assistant electronic circuits. It can change temperature signal into electric signal. The paper introduces a two-wire current temperature transmitter which consists of platinum resistance and the new type integrated chip-AD693. It mainly analyzes the theoretical basis of the system and chooses an appropriate hardware implementation scheme. This paper analyzes the basic principle of temperature transmitter and the composed units of current temperature transmitter, chooses and calculates the circuit modules components, finishes the systematic design of electric circuit schematic.
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Biswal, P. K., K. Mishra, S. Biswas, and H. K. Kapoor. "A Discrete Event System Approach to Online Testing of Speed Independent Circuits." VLSI Design 2015 (April 30, 2015): 1–16. http://dx.doi.org/10.1155/2015/651785.
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With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that verifies the correctness of the protocol. This checker involves Mutex blocks making its area overhead quite high. In this paper, we have adapted the Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of speed independent asynchronous circuits. The scheme involves development of a state based model of the circuit, under normal and various stuck-at fault conditions, and finally designing state estimators termed as detectors. The detectors monitor the circuit online and determine whether it is functioning in normal/failure mode. The main advantages are nonintrusiveness and low area overheads compared to similar schemes reported in the literature.
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Zharkov, Yu I., N. A. Popova, and E. P. Figurnov. "Accounting power supply schemes for traction substations in the calculation of short circuits in the AC traction network." Vestnik of the Railway Research Institute 78, no. 1 (2019): 10–18. http://dx.doi.org/10.21780/2223-9731-2019-78-1-10-18.
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When calculating short-circuit currents in the AC traction network, it is assumed that each of the traction substations receives power from uncoupled external power supply sources with known resistances. In some cases, especially when powering a group of traction substations from a high-voltage power line of a longitudinal power supply, the external power supply system affects not only the magnitude of short-circuit currents, but also their redistribution between adjacent traction substations of the interstation area where this circuit is considered. Such unrecorded redistribution can have a negative effect on short circuit protection. The article considers the equivalent circuit of the traction network, taking into account resistance of the external power supply system. Particular attention is paid to the fact that in replacement circuits of direct and negative sequence value of reduced resistance of one phase of a multiwinding transformer, calculated from the short circuit voltage, does not depend on the connection scheme of its windings. It is noted that in some cases it is difficult to obtain a complete scheme of an external power supply system. Considering that the short circuit in the traction network for the external power supply system is remote, it is proposed taking into account the reference network or traction substations as power sources, from which high-voltage transmission lines power the traction substations. Resistance of the supporting substations as power sources must takes into account connected equivalent power system.Such equivalenting should be carried out by known values of currents or short-circuit powers at the inputs of the reference substation or, if such information is not available, by the rated values of the switched-off currents or powers of the switches of high-voltage line connections.The following power schemes for traction substations are considered: each from its own supporting substation, which is part of an electrically uncoupled external power supply system; from the double-circuit high-voltage line of longitudinal power supply when it is powered from different supporting substations; from the supporting network substation, the traction substation receives power from two lines, and from this the traction substations receive power from two lines in a circle pattern.These three common cases cover all the most common power schemes for traction substations. For each of them formulas are given to determine the resulting equivalent resistance of the external power supply circuit, which should be taken into account in the replacement circuit of the traction network.
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Li, Xin, Yonggang Li, Hongqiu Zhu, Renchao Wu, and Can Zhou. "Short Circuit Fault Detection against High Thermal Background Using a Two-Level Scheme Based on DoG Filter." Complexity 2021 (January 28, 2021): 1–13. http://dx.doi.org/10.1155/2021/8824768.
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Short circuit is a key factor which drastically affects the efficiency of metal electrorefining. Infrared image of the intercell busbar region is used to perform short circuit detection. To cope with the high thermal background, a two-level short circuit detection method is designed. Firstly, with background subtraction, high intensity short circuit electrodes, as well as the background, are removed, and normal working electrodes are preserved. In the second stage, suspicious short circuit areas are sifted out by normal electrode detecting and texture period estimation. Gaussian difference filter (DoG) which is based on the human visual system is improved to match the target gray distribution. A comparative experiment indicates that the proposed orthogonal DoG outperforms the original DoG and top-hat in the accuracy of normal electrode detection. The two-level detection method in this paper is applied in a copper electrolysis plant and exhibits superiority in locating short circuits and avoiding miss detection.
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Spector, Lee, and Jon Klein. "Machine invention of quantum computing circuits by means of genetic programming." Artificial Intelligence for Engineering Design, Analysis and Manufacturing 22, no. 3 (2008): 275–83. http://dx.doi.org/10.1017/s0890060408000188.
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AbstractWe demonstrate the use of genetic programming in the automatic invention of quantum computing circuits that solve problems of potential theoretical and practical significance. We outline a developmental genetic programming scheme for such applications; in this scheme the evolved programs, when executed, build quantum circuits and the resulting quantum circuits are then tested for “fitness” using a quantum computer simulator. Using the PushGP genetic programming system and the QGAME quantum computer simulator we demonstrate the invention of a new, better than classical quantum circuit for the two-oracle AND/OR problem.
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Tong, Jin, Honghao Wu, Yujuan Lin, Yigang He, and Junyong Liu. "Fog-Computing-Based Short-Circuit Diagnosis Scheme." IEEE Transactions on Smart Grid 11, no. 4 (2020): 3359–71. http://dx.doi.org/10.1109/tsg.2020.2964805.
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Li, Xiao Jing, Zhi Hua Gao, Di Wang, and Dong Man Yu. "Study on System Design Scheme for Electrical Control Scheme of Boiler." Applied Mechanics and Materials 556-562 (May 2014): 2397–400. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.2397.
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The breeding plumbing boiler is a full automatic temperature adjustment system with double efficacy of winter heating and summer cooling, constituted by host, auxiliary engine, control system and plumbing pipes, etc. Intermediate between PLC output port and AC contactor is to achieve the isolation between weak current and strong current, enhance the reliability of the system. Two frequency changers are designed for the hardware of system. Frequency converter input power linked up front access air switch. Frequency converter input terminals main circuit switch and the three phase power through air connection, frequency converter main circuit output terminals connected to the contactor three-phase motor. It is proved by field experimental operation that the control system proposed not only can realize automatic control of boiler burning process efficiently, but also reduced energy consumption greatly and effectively improved the level of boiler control management.
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Elshin, Anatoly, Vyacheslav Kozhukhov, and Petr Elshin. "Calculation of substitution scheme parameters inductive-conductive heater." Proceedings of the Russian higher school Academy of sciences, no. 4 (January 20, 2021): 7–16. http://dx.doi.org/10.17212/1727-2769-2020-4-7-16.
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To reduce production costs in the design and creation of an inductive-conductive heater (ICH), it is necessary to carry out a preliminary calculation as accurately as possible. This is possible when using the most approximate electrical circuit for replacing the ICH to a real object. It becomes possible to assess the work of the ICH in various operating conditions, including emergency conditions, using simpler modeling. An inductive-conductive heater transformertype is a three-rod W-shaped magnetic circuit with primary windings, which are covered by a heat exchanger (HE) of three concentric systems of electrically conductive cylinders with an internal slotted channel for the coolant. The energy from the mains supply is inductively transferred to the heat exchanger through the air gap by means of the primary winding. The secondary circuit of an electromagnetic device is a heat exchanger in which electrical energy is converted into heat. The heat flux from the heated cylindrical walls of the HE conductively heats the coolant circulating in the system to the required temperature. The large surface area of the HE allows you to avoid its overheating in relation to the coolant, which has a positive effect during the operation of the ICH in heating and hot water supply systems, significantly reducing the deposition of water impurities on the walls of the HE. The service life of the device is increased to 100 thousand hours or more. In the work, the synthesis of elements of the ICH equivalent circuit is carried out and the results of calculating the characteristics of the stationary mode of a number of products are presented. The equivalent circuit allows you to simulate electromagnetic processes in devices of different power, voltage and industrial frequencies in the range of 50…1000 Hz. If the configuration of the heating chamber (secondary circuit) is changed, the parameters of the elements of the equivalent circuit are adjusted without changing the general construction algorithm. For new products of inductive-conductive heating, there are no bibliographic data for calculating the elements of the equivalent circuit, especially regarding the formation of the replacement circuit of the secondary circuit, determined by the design of the heating chamber. To fill this gap, the authors have done this work.
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Bundalo, Dusanka, Zlatko Bundalo, and Branimir Ðordjevic. "Design of quaternary logic systems and circuits." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 45–56. http://dx.doi.org/10.2298/fuee0501045b.
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The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm includes the most important aspects of design of quaternary logic circuits: logic circuit scheme synthesis and logic circuit optimization. Methods for synthesis of quaternary CMOS combinational logic circuits are proposed and described. Also, method for optimization of CMOS quaternary logic circuits, according to operation conditions and needed characteristics, is proposed and described. Design procedure is realized by personal computer using PSPICE for circuit simulation. Computer PSPICE simulation results confirming described methods and conclusions are given in the paper.
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Мазуха, N. Mazukha, Мазуха, and A. Mazukha. "Using the multifunction relay insulation monitoring and control phases in the control circuit by a crane." Voronezh Scientific-Technical Bulletin 4, no. 3 (2015): 66–71. http://dx.doi.org/10.12737/14011.
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The proposed control scheme for the engine crane at low speed before brak-ing. The circuit has multifunction relay RKF-M-2-15 for the control of unbalance mains and isolation control circuits to which it is connected.
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Huang, Yang Qi, Nian Liu, and Jian Hua Zhang. "Study on Main Electrical Connection of 500kV Smart Terminal Substation." Advanced Materials Research 945-949 (June 2014): 2850–53. http://dx.doi.org/10.4028/www.scientific.net/amr.945-949.2850.
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With the rapid development of city construction, contradiction between power supply and demand becomes more marked, so the idea of building 500kV terminal substation is put forward. This paper analyzes the design principle of main electrical connection of 500kV terminal substation, introduces several typical main electrical connection forms and compares the reliability and economy of referred forms between traditional schemes with circuit breakers and disconnecting switches and new schemes with disconnecting circuit breakers (DCB). The new scheme of transformer line block connection with disconnecting circuit breaker is recommended as the prior of 500kV main electrical connection in 500kV smart terminal substation.
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Tang, Xiao-Bin, and Masayoshi Tachibana. "A BIST Scheme for Bootstrapped Switches." Electronics 10, no. 14 (2021): 1661. http://dx.doi.org/10.3390/electronics10141661.
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This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in bootstrapped switches. The clock signal and the gate voltage of the sampling MOS transistor are taken as the observation signals in the proposed BIST scheme. Usually, the gate voltage of the sampling MOS transistor is greater than or equal to the supply voltage when the switch is turn on, and such a voltage is not suitable for observation. To solve this problem, a low power supply voltage is provided for the bootstrapped switch to obtain a suitable observation voltage. The proposed BIST scheme and the circuit under test (CUT) are realized with transistor level. The proposed BIST scheme was simulated by HSPICE. The simulated fault coverage is approximately 87.9% with 66 test circuits.
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Mukwata, Wonder, and Josiah Munda. "Analysis of 3 kV DC Contact Line High-Speed Circuit Breaker Unit Protection Scheme Limitations." International Journal of Electronics and Electrical Engineering 10, no. 1 (2022): 7–13. http://dx.doi.org/10.18178/ijeee.10.1.7-13.
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The High-Speed Circuit Breaker (HSCB) is a de-facto electro-mechanical contact line protection device employed in the 3 kV DC traction power supply system. The breakers installed at the terminal ends of the contact line make a unit protection scheme configuration. While the HSCBs seem to trip under fault conditions, there is an unknown source that keeps on supplying residual current into the faults. This necessitates some explanation of the source of energy of the continual flow of residual energy. This paper makes an analysis of the limitations in the HSCB unit protection scheme using MATLAB simulation and how the scheme can be optimized with digital protection devices augmented with a peer-to-peer transfer trip as an end-to-end protection solution.
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Kuznetsov, Sergey. "Monad Theory of Structural Synthesis of Mechanisms." MATEC Web of Conferences 346 (2021): 03041. http://dx.doi.org/10.1051/matecconf/202134603041.
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Structural synthesis creates a structural scheme according to the given structural characteristics - the degree of abnormality of the structure S and the degree of its irrationality s. Structural scheme is created at the first stage of synthesis, containing only rotational kinematic pairs and corresponds to a given degree of abnormality, which is ensured by the ratio of structural units – plus monads, minus monads and null monads. At the second stage, the independence of structural characteristics makes it possible to bring the obtained scheme to a given degree of irrationality by downgrading the class of kinematic pairs. The proposed algorithm makes it possible to synthesize structural schemes of both normal structure and adaptive (with redundant motions), as well as indifferent (with redundant links). Monadic approach to structure research allows to formalize the structural features of the circuit and to create a knowledge base for automated design of structural circuits with given structural properties.
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Agarwal, Neeru, Neeraj Agarwal, Chih-Wen Lu, and Masahito Oh-e. "A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator." Electronics 10, no. 18 (2021): 2257. http://dx.doi.org/10.3390/electronics10182257.
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A chopper-embedded bandgap reference (BGR) scheme is presented using 0.18 μm CMOS technology for low-frequency noise suppression in the clock generator application. As biasing circuitry produces significant flicker noise, along with thermal noise from passive components, the proposed low-noise chopper-stabilized BGR circuit was designed and implemented for wide temperature range from −40 to 125 °C, including a startup and self-biasing circuit to reduce critical low-frequency noise from the bias circuitry and op amp input offset voltage. The BGR circuit generated a reference voltage of 1.25 V for a supply voltage range of 2.5–3.3 V. The gain of the implemented BGR operational transconductance amplifier is 84.1 dB. A non-overlapping clock circuit was implemented to reduce the clock skew effect, which is also one of the noise contributors. The noise analysis of a chopped bandgap voltage reference was evaluated through cadence periodic steady-state (PSS) analysis and periodic noise (PNoise) analysis. The low-frequency flicker noise was reduced from 1.5 to 0.4 μV/sqrt(Hz) at 1 KHz, with the proposed chopping scheme in the bandgap. Comparisons of the noise performance of the chopper-embedded BGR, with and without a low-pass filter, were also performed, and the results show a further reduction in the overall noise. A reduction in the flicker noise, from 181.3 to 10.26 mV/sqrt(Hz) at 100 KHz, was observed with the filter. All circuit blocks of the proposed BGR scheme were designed and simulated using the EDA tool HSPICE, and layout generation was carried out by Laker. The BGR architecture layout dimensions are 285.25 μm × 125.38 μm.
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Varaprasad, B. K. S. V. L., L. M. Patnaik, H. S. Jamadagni, and V. K. Agrawal. "An Efficient Test Pattern Generation Scheme for an On Chip BIST." VLSI Design 12, no. 4 (2001): 551–62. http://dx.doi.org/10.1155/2001/45324.
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Testing and power consumption are becoming two critical issues in VLSI design due to the growing complexity of VLSI circuits and remarkable success and growth of low power applications (viz. portable consumer electronics and space applications). On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation (TPG) schemes in BIST. We present a novel methodology based on the use of a suitable Linear Feedback Shift Register (LFSR) which cycles through the required sequences (test vectors) aiming at a desired fault coverage causing minimum circuit toggling and hence low power consumption while testing. The proposed technique uses circuit simulation data for modeling. We show how to identify the LFSR using graph theory techniques and compute its feedback coefficients (i.e., its characteristic polynomial) for realization of a Test Pattern Generator.
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Shigematsu, S., S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada. "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits." IEEE Journal of Solid-State Circuits 32, no. 6 (1997): 861–69. http://dx.doi.org/10.1109/4.585288.
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Hegendörfer, Andreas, Paul Steinmann, and Julia Mergheim. "Nonlinear finite element system simulation of piezoelectric vibration-based energy harvesters." Journal of Intelligent Material Systems and Structures 33, no. 10 (2021): 1292–307. http://dx.doi.org/10.1177/1045389x211048222.
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Piezoelectric vibration-based energy harvesters consist of an electromechanical structure and an electric circuitry, influencing each other. We propose a novel approach that allows a finite element based system simulation of nonlinear electromechanical structures coupled to nonlinear electric circuitries. In the finite element simulation the influence of the electric circuit on the electromechanical structure is considered via the vector of external forces, using an implicit time integration scheme. To demonstrate the applicability of the new simulation method an active power circuit is considered. Several examples of piezoelectric vibration-based energy harvesters, connected to standard or synchronized switch harvesting on inductor (SSHI) circuits, showing linear or nonlinear mechanical behavior, are studied to validate the proposed simulation method against numerical results reported in the literature. The advocated method allows for consistent and efficient simulations of complete nonlinear energy harvesters using only one software tool.