Relevant bibliographies by topics / Circuits CMOS

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Circuits CMOS'

Author: Grafiati
Published: 4 June 2021
Last updated: 20 May 2022

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Journal articles on the topic "Circuits CMOS"

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HURST, S. L. "Open-circuit testing of CMOS circuits." International Journal of Electronics 62, no. 2 (1987): 161–65. http://dx.doi.org/10.1080/00207218708920964.

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Bundalo, Dusanka, Zlatko Bundalo, and Branimir Ðordjevic. "Design of quaternary logic systems and circuits." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 45–56. http://dx.doi.org/10.2298/fuee0501045b.

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The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm inclu
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Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

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Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF cir
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Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria, and S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits." ISRN Electronics 2013 (February 10, 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.

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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been dev
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Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to
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Tiwari, Ayush. "Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 962–66. http://dx.doi.org/10.22214/ijraset.2021.35065.

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Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits
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WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high p
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KIM, JEONG BEOM. "CURRENT MODE CMOS QUATERNARY LOGIC FULL-ADDER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 199–208. http://dx.doi.org/10.1142/s0218126609005022.

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This paper proposes a quaternary-to-binary logic decoder, a quaternary current buffer, and a quaternary full-adder using current-mode multiple-valued logic (MVL) CMOS circuits. The proposed full-adder is superior to the previous MVL CMOS circuit in both the circuit occupied area and the performance. Comparing with the binary logic full-adder, the proposed full-adder is superior in the circuit occupied area. However, the circuit performance is inferior to the binary logic full-adder. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 μm stan
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JIAO, HAILONG, and VOLKAN KURSUN. "NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS." Journal of Circuits, Systems and Computers 20, no. 01 (2011): 125–45. http://dx.doi.org/10.1142/s0218126611007116.

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Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the
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Sedaghat, Mahsa, and Mahdi Salimi. "Evaluation and Comparison of CMOS logic circuits with CNTFET." Journal of Research in Science, Engineering and Technology 3, no. 04 (2019): 1–9. http://dx.doi.org/10.24200/jrset.vol3iss04pp1-9.

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In this paper, a comparison between CMOS and MOSFET base circuits HSPICE is done with software. 0.13 CMOS transistor model for simulation and CNTFET Model of Stanford University used. In simulations amounts of power, circuit delay and PDP is calculated and these values were compared at the end. And tried to CNTFET applications of transistors in circuit design, including memory and logic circuits Ternary be expressed.
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Dissertations / Theses on the topic "Circuits CMOS"

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Chen, Yonggang Suhling J. C. Jaeger Richard C. "CMOS stress sensor circuits." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Fall/Dissertations/CHEN_YONGGANG_42.pdf.

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Madhyastha, Sadhana. "Design of circuit breakers for large area CMOS VLSI circuits." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59551.

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Large-area ICs require adequate defect-tolerance to achieve a reasonable yield. One concern is that the power distribution network is shared by a number of modules, and any single short between the supply (V$ sb{dd}$) and ground can disable all these modules. The object of this thesis is to evaluate the feasibility of incorporating circuit breakers in large area ICs, which provide protection against such defects by disconnecting the defective modules from the array. A critical analysis and comparison of MOS transistors and parasitic bipolar transistors as circuit breakers are carried out. It i
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Wang, Guoyu. "CMOS VLSI circuits for imaging." Thesis, University of Edinburgh, 1993. http://hdl.handle.net/1842/13190.

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MOS technology is very attractive for achieving low-cost miniature cameras. It also permits the inclusion of the sensor with other control and processing functions on the same chip. However, this technique has never been developed to the point at which MOS sensor performance matches that of CCD cameras. The objective of this project has been to develop design techniques to achieve single chip video cameras, in unmodified CMOS processes, with improved performance (aimed to match the performance of CCD cameras) and enhanced functionality. In this thesis, following an overview of solid state imag
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Miranda, Fernando Pedro Henriques de. "Estudo e projeto de circuitos dual-modulus prescalers em tecnologia CMOS." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14122006-154818/.

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Este trabalho consiste no estudo e projeto de circuitos Dual-Modulus Prescaler utilizados em sistemas de comunicação RF (radio frequency). Sistemas de comunicação RF trabalham em bandas de freqüência pré-definidas e dentro destas há, normalmente, vários canais para transmissão. Neste caso, decidido o canal onde se vai trabalhar, o receptor e o transmissor geram, através de um circuito chamado Sintetizador de Freqüências, sinais que têm a freqüência igual a freqüência central do canal utilizado. Esses sinais ou tons são empregados na modulação e demodulação das informações transmitidas ou receb
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Ramirez, Ortiz Rolando. "Circuit design rules for mixed static and dynamic CMOS logic circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ37076.pdf.

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Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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Neto, Murillo Fraguas Franco. "Técnica para o projeto de um amplificador operacional folded cascode, classe AB, em tecnologia CMOS." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-05092006-152855/.

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A tendência mundial em torno de sistemas SoC – System on Chip – baseados em processo CMOS – Complementary Metal Oxide Semiconductor – digital, apresenta cada vez mais desafios aos projetistas de circuitos integrados. Em especial se observa que enquanto os projetistas de circuitos digitais podem contar com bibliotecas cada vez mais completas de células digitais semi-prontas e ferramentas cada vez mais poderosas para o aprimoramento do projeto, os projetistas analógicos não contam com tais facilidades, sendo necessário realizar o projeto de novas células analógicas para cada especificação recebi
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Shenoy, Sandeep P. (Sandeep Pundalika). "Switching activity in CMOS digital circuits." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=24071.

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In (48, 47) a pattern-independent method to estimate the switching activity of a CMOS circuit was presented. The technique relies on the use of abstract waveforms, described down to the level of individual transitions, which are propagated through the circuit. In order to improve the switching activity estimate so obtained, case analysis is undertaken on nodes with large fanout.<br>The objective of this thesis is to develop and implement a method to further improve upon the switching activity estimate through consideration of reconvergent fanout regions in the circuit. The idea is to impose fu
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Olson, Michael Garth. "Bridging fault diagnosis in CMOS circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp04/mq21198.pdf.

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Söderquist, Ingemar. "CMOS circuits for digital RF systems /." Linköping : Univ, 2002. http://www.bibl.liu.se/liupubl/disp/disp2002/tek775s.pdf.

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Books on the topic "Circuits CMOS"

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Haraszti, Tegze P. CMOS memory circuits. Kluwer Academic, 2000.

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CMOS memory circuits. Kluwer Academic, 2000.

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Marston, R. M. Modern CMOS circuits manual. 2nd ed. Newnes, 1996.

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Shoji, Masakazu. Theory of CMOS digital circuits and circuit failures. Princeton University Press, 1992.

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Shoji, Masakazu. Theory of CMOS digital circuits and circuit failures. Princeton University Press, 1992.

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Jea-Hong, Luo, ed. Low-voltage CMOS VLSI circuits. Wiley, 1999.

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Anis, Mohab, and Mohamed Elmasry. Multi-Threshold CMOS Digital Circuits. Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0.

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Gharavi, Sam, and Babak Heydari. Ultra High-Speed CMOS Circuits. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0305-0.

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Corporation, National Semiconductor. CMOS logic databook. National Semiconductor Corp., 1988.

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Design of analog CMOS integrated circuits. McGraw-Hill, 2001.

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Book chapters on the topic "Circuits CMOS"

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Veendrick, H. J. M. "CMOS circuits." In Nanometer CMOS ICs. Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8333-4_4.

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Kolawole, Michael Olorunfunmi. "CMOS Circuits." In Electronics. CRC Press, 2020. http://dx.doi.org/10.1201/9781003052913-6.

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J.M. Veendrick, Harry. "CMOS Circuits." In Nanometer CMOS ICs. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-47597-4_4.

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Veendrick, H. J. M. "CMOS circuits." In Deep-Submicron CMOS ICs. Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4133-2_4.

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Brzozowski, Janusz A., and Carl-Johan H. Seger. "CMOS Transistor Circuits." In Asynchronous Circuits. Springer New York, 1995. http://dx.doi.org/10.1007/978-1-4612-4210-9_5.

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Kuo, James B., and Ker-Wei Su. "SOI CMOS Circuits." In CMOS VLSI Engineering. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2823-1_3.

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Seevinck, Evert. "CMOS Translinear Circuits." In Analog Circuit Design. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4613-1443-1_15.

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Uyemura, John P. "Analog CMOS Circuits." In Circuit Design for CMOS VLSI. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_9.

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Bhushan, Manjul, and Mark B. Ketchen. "CMOS Circuits Basics." In CMOS Test and Evaluation. Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4939-1349-7_2.

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Yazicioglu, R. Firat. "Readout Circuits." In Bio-Medical CMOS ICs. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6597-4_4.

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Conference papers on the topic "Circuits CMOS"

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Kulakova, Anastasiya, and E. Lukyanenko. "THE SYNTHESIS OF MEMORY ELEMENTS FOR CMOS CIRCUITS." In CAD/EDA/SIMULATION IN MODERN ELECTRONICS 2019. Bryansk State Technical University, 2019. http://dx.doi.org/10.30987/conferencearticle_5e0282139bcfc0.73318616.

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Two-stage triggers synthesized on CMOS-transistors are given. Triggers are based on a “weak” latch and a symmetrical control circuit. The results of comparing the above triggers for energy efficiency are presented, revealing the advantages of synthesized elements over circuits based on standard logic elements.
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Polonsky, Stas, Alan Weger, and Moyra McManus. "Picosecond Imaging Circuit Analysis of Leakage Currents in CMOS Circuits." In ISTFA 2002. ASM International, 2002. http://dx.doi.org/10.31399/asm.cp.istfa2002p0387.

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Abstract The light emission from ever increasing OFF-state leakage currents in advanced CMOS technologies can now be reliably measured using existing photon detectors. The measurements of such an emission provide valuable information about the operation of ICs. In this paper we suggest and experimentally confirm two new techniques based on such measurements - Transient Logic State Detection and Power Supply Noise Analysis.
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Jung, Seung-Ho, Jong-Humn Baek, and Seok-Yoon Kim. "Short circuit power estimation of static CMOS circuits." In the 2001 conference. ACM Press, 2001. http://dx.doi.org/10.1145/370155.370528.

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Bult, Klaas, and Hans Wallinga. "Analog CMOS Computational Circuits." In Twelfth European Solid-State Circuits Conference. IEEE, 1986. http://dx.doi.org/10.1109/esscirc.1986.5468339.

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Ram, Rajeev J. "CMOS Photonic Integrated Circuits." In Optical Fiber Communication Conference. OSA, 2012. http://dx.doi.org/10.1364/ofc.2012.om2e.1.

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Strukov, D. B., D. R. Stewart, J. Borghetti, et al. "Hybrid CMOS/memristor circuits." In 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5537020.

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Lee, Thomas H. "Terahertz CMOS integrated circuits." In 2014 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT). IEEE, 2014. http://dx.doi.org/10.1109/rfit.2014.6933268.

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Jianping Hu, Ling Wang, and Huiying Dong. "Interface circuits between adiabatic and standard CMOS circuits." In 2007 Joint 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) and the IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007). IEEE, 2007. http://dx.doi.org/10.1109/mwscas.2007.4488646.

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Stan, M. R., G. S. Rose, and M. M. Zielger. "Hybrid CMOS/Molecular Electronic Circuits." In 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06). IEEE, 2006. http://dx.doi.org/10.1109/vlsid.2006.99.

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Cirit, M. A. "Transistor sizing in CMOS circuits." In 24th ACM/IEEE conference proceedings. ACM Press, 1987. http://dx.doi.org/10.1145/37888.37906.

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Reports on the topic "Circuits CMOS"

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Brocco, Lynne M. Macromodeling CMOS Circuits for Timing Simulation. Defense Technical Information Center, 1987. http://dx.doi.org/10.21236/ada459654.

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Likharev, Konstantin K., and James Lukens. Fundamental Problems of Hybrid CMOS/Nanodevice Circuits. Defense Technical Information Center, 2010. http://dx.doi.org/10.21236/ada565890.

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Likharev, Konstantin K., and James Lukens. Fundamental Problems of Hybrid CMOS/Nanodevice Circuits. Defense Technical Information Center, 2010. http://dx.doi.org/10.21236/ada564340.

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Resnick, Douglas, and Konstantin Likharev. Hybrid CMOS/Nanodevice Integrated Circuits Design and Fabrication. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada487894.

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Pouliquen, Philippe O., and Mark N. Martin. Latch-Up Detection and Cancellation in CMOS VLSI Circuits. Defense Technical Information Center, 2000. http://dx.doi.org/10.21236/ada399884.

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Chang, Young-hoon, and Jon T. Butler. The Design of Current Mode CMOS Multiple-Valued Circuits. Defense Technical Information Center, 1991. http://dx.doi.org/10.21236/ada608087.

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Onneweer, Siep, Hans Kerkhoff, and Jon Butler. Structural Computer-Aided Design of Current-Mode CMOS Logic Circuits. Defense Technical Information Center, 1988. http://dx.doi.org/10.21236/ada608071.

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Sainudeen, Zuhail, and Navid Yazdi. Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem. Defense Technical Information Center, 2001. http://dx.doi.org/10.21236/ada402437.

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Saripalli, Ganesh. CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories. Office of Scientific and Technical Information (OSTI), 2002. http://dx.doi.org/10.2172/806590.

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Van Duzer, T., Stephen R. Whiteley, Lizhen Zheng, et al. Hybrid Josephson-CMOS Random Access Memory with Interfacing to Josephson Digital Circuits. Defense Technical Information Center, 2013. http://dx.doi.org/10.21236/ada596658.

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