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Journal articles on the topic 'Circuits CMOS'

Author: Grafiati

Published: 4 June 2021

Last updated: 20 May 2022

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1

HURST, S. L. "Open-circuit testing of CMOS circuits." International Journal of Electronics 62, no. 2 (1987): 161–65. http://dx.doi.org/10.1080/00207218708920964.

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2

Bundalo, Dusanka, Zlatko Bundalo, and Branimir Ðordjevic. "Design of quaternary logic systems and circuits." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 45–56. http://dx.doi.org/10.2298/fuee0501045b.

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The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm inclu

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3

Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

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Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF cir

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4

Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria, and S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits." ISRN Electronics 2013 (February 10, 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.

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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been dev

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5

Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to

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6

Tiwari, Ayush. "Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 962–66. http://dx.doi.org/10.22214/ijraset.2021.35065.

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Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits

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WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high p

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8

KIM, JEONG BEOM. "CURRENT MODE CMOS QUATERNARY LOGIC FULL-ADDER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 199–208. http://dx.doi.org/10.1142/s0218126609005022.

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This paper proposes a quaternary-to-binary logic decoder, a quaternary current buffer, and a quaternary full-adder using current-mode multiple-valued logic (MVL) CMOS circuits. The proposed full-adder is superior to the previous MVL CMOS circuit in both the circuit occupied area and the performance. Comparing with the binary logic full-adder, the proposed full-adder is superior in the circuit occupied area. However, the circuit performance is inferior to the binary logic full-adder. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 μm stan

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9

JIAO, HAILONG, and VOLKAN KURSUN. "NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS." Journal of Circuits, Systems and Computers 20, no. 01 (2011): 125–45. http://dx.doi.org/10.1142/s0218126611007116.

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Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the

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Sedaghat, Mahsa, and Mahdi Salimi. "Evaluation and Comparison of CMOS logic circuits with CNTFET." Journal of Research in Science, Engineering and Technology 3, no. 04 (2019): 1–9. http://dx.doi.org/10.24200/jrset.vol3iss04pp1-9.

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In this paper, a comparison between CMOS and MOSFET base circuits HSPICE is done with software. 0.13 CMOS transistor model for simulation and CNTFET Model of Stanford University used. In simulations amounts of power, circuit delay and PDP is calculated and these values were compared at the end. And tried to CNTFET applications of transistors in circuit design, including memory and logic circuits Ternary be expressed.

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11

O, K. K., S. SANKARAN, C. CAO, et al. "MILLIMETER WAVE TO TERAHERTZ IN CMOS." International Journal of High Speed Electronics and Systems 19, no. 01 (2009): 55–67. http://dx.doi.org/10.1142/s0129156409006084.

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The feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and a 180-GHz detector circuit in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible. Though these results are significant, output power of signal generators must be increased and acceptable noise performance of detectors must be achieved in order to demonstrate the applicability of CMOS for im

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12

Bae, Woorham. "CMOS Inverter as Analog Circuit: An Overview." Journal of Low Power Electronics and Applications 9, no. 3 (2019): 26. http://dx.doi.org/10.3390/jlpea9030026.

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedba

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Bansal, Deepika, Brahmadeo Prasad Singh, and Ajay Kumar. "Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic." Bulletin of Electrical Engineering and Informatics 6, no. 2 (2017): 122–32. http://dx.doi.org/10.11591/eei.v6i2.597.

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The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s an

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14

Panwar, Shikha, Mayuresh Piske, and Aatreya Vivek Madgula. "Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits." VLSI Design 2014 (July 15, 2014): 1–5. http://dx.doi.org/10.1155/2014/380362.

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This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Com

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Kumar, Manish, Md Anwar Hussain, and Sajal K. Paul. "Effective Circuit Design Methodologies for Standby Leakage Power Reduction." Advanced Science, Engineering and Medicine 12, no. 2 (2020): 168–72. http://dx.doi.org/10.1166/asem.2020.2484.

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This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software

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16

Kushwah, Ravindra Singh, and Shyam Akashe. "FinFET Based Tunable Analog Circuit: Design and Analysis at 45 nm Technology." Chinese Journal of Engineering 2013 (October 24, 2013): 1–8. http://dx.doi.org/10.1155/2013/165945.

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We included a designing of low power tunable analog circuits built using independently driven FinFETs devices, where the controlling of the back gate provide the output on the front gate. We show that this could be an effective solution to conveniently tune the output of bulk CMOS analog circuits particularly for Schmitt trigger and operational transconductance amplifier circuits. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both are independently controlled. FinFET device has a higher controllability

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17

Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with g

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18

Jiang, Jin Tao, Yu Zhang, and Jian Ping Hu. "P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits." Advanced Materials Research 159 (December 2010): 155–61. http://dx.doi.org/10.4028/www.scientific.net/amr.159.155.

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With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65n

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19

Schlachta, C., and M. Glesner. "Resonance circuits for adiabatic circuits." Advances in Radio Science 1 (May 5, 2003): 223–28. http://dx.doi.org/10.5194/ars-1-223-2003.

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Abstract. One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

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20

FLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.

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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to fi

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21

Kocanda, Piotr, and Andrzej Kos. "Energy losses and DVFS effectiveness vs technology scaling." Microelectronics International 32, no. 3 (2015): 158–63. http://dx.doi.org/10.1108/mi-01-2015-0008.

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Purpose – This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS). Design/methodology/approach – Using analytical equations and Spice models of var

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22

Lee, Hyung K., and Dong S. Ha. "An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits." VLSI Design 2, no. 3 (1994): 199–207. http://dx.doi.org/10.1155/1994/71941.

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In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, called SOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives test patterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing tim

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23

Shokrani, Mohammad Reza, Mojtaba Khoddam, Mohd Nizar B. Hamidon, Noor Ain Kamsani, Fakhrul Zaman Rokhani, and Suhaidi Bin Shafie. "An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/963709.

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This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is expl

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24

Soeleman, H., K. Roy, and Tan-Li Chou. "Estimating circuit activity in combinational CMOS digital circuits." IEEE Design & Test of Computers 17, no. 2 (2000): 112–19. http://dx.doi.org/10.1109/54.844340.

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NASEH, SASAN, and M. JAMAL DEEN. "RF CMOS RELIABILITY." International Journal of High Speed Electronics and Systems 11, no. 04 (2001): 1249–95. http://dx.doi.org/10.1142/s0129156401001088.

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In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits mode of them, but DC parameters of the device such as its I-V characteristics and threshold volt

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26

Chung, Seungjun, and Takhee Lee. "Towards flexible CMOS circuits." Nature Nanotechnology 15, no. 1 (2019): 11–12. http://dx.doi.org/10.1038/s41565-019-0596-6.

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27

SASI, SREELA, and DAMU RADHAKRISHNAN. "Hazards in CMOS circuits." International Journal of Electronics 68, no. 6 (1990): 967–90. http://dx.doi.org/10.1080/00207219008921238.

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28

Yuan, J. R. "Efficient CMOS counter circuits." Electronics Letters 24, no. 21 (1988): 1311. http://dx.doi.org/10.1049/el:19880891.

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29

Wu, X. W., and F. P. Prosser. "CMOS ternary logic circuits." IEE Proceedings G Circuits, Devices and Systems 137, no. 1 (1990): 21. http://dx.doi.org/10.1049/ip-g-2.1990.0005.

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30

Radhakrishnan, D. "Design of CMOS circuits." IEE Proceedings G Circuits, Devices and Systems 138, no. 1 (1991): 83. http://dx.doi.org/10.1049/ip-g-2.1991.0016.

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31

Sasi, Sreela, and Damu Radhakrishnan. "Transients in CMOS Circuits." IETE Journal of Research 36, no. 3-4 (1990): 306–12. http://dx.doi.org/10.1080/03772063.1990.11436898.

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32

Isern, E., and J. Figueras. "IDDQ Detectable Bridges in Combinational CMOS Circuits." VLSI Design 5, no. 3 (1997): 241–52. http://dx.doi.org/10.1155/1997/93809.

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Undetectable stuck-at faults in combinational circuits are related to the existence of logic redundancy (s-redundancy). Similarly, logically equivalent nodes may cause some bridging faults to become undetectable by IDDQ testing. An efficient method for the identification and removal of such functionally equivalent nodes (f-redundant nodes) in combinational circuits is presented. OBDD graphs are used to identify the functional equivalence of candidate to f-redundancy nodes. An f-redundancy removal algorithm based on circuit transformations to improve bridging fault testability, is also proposed

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33

Khadir, Mohammad, S. Renukarani, Tunikipati Usharani, and D. Hemanth Kumar. "Design of High Performance Decoder with Mixed Logic Styles." International Journal of Engineering & Technology 7, no. 2.20 (2018): 119. http://dx.doi.org/10.14419/ijet.v7i2.20.12187.

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The CMOS technology is the mostly portable technology used in the designing of the circuits and in its fabrication. Designing of the circuits using CMOS technology requires the high power, high transistors count and low performance. The basic idea of the project is in order to reduce the count of transistors, time delay, and power consumption and to increase the performance of the circuits such as line decoders. The line decoder is a combinational circuits to which „n‟ no .of inputs are given as input and the output is 2^n based on the selected input and it requires 20 and more than 20 transis

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34

Ramsay, E., James Breeze, David T. Clark, et al. "High Temperature CMOS Circuits on Silicon Carbide." Materials Science Forum 821-823 (June 2015): 859–62. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.859.

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This paper presents the characteristics and performance of a range of Silicon Carbide (SiC) CMOS integrated circuits fabricated using a process designed to operate at temperatures of 300°C and above. The properties of Silicon carbide enable both n-channel and p-channel MOSFETS to operate at temperatures above 400°C [1] and we are developing a CMOS process to exploit this capability [4]. The operation of these transistors and other integrated circuit elements such as resistors and contacts is presented across a temperature range of room temperature to +400°C. We have designed and fabricated a w

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35

Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circu

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Xiang-jie, Niu, and Li Hua. "Lower Power Design for UHF RF CMOS Circuits Based on the Power Consumption Acuity." Mathematical Problems in Engineering 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/512398.

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Excessive energy consumption of UHF tag is the bottleneck of energy saving in its wide range of applications. To address this issue, a lower power design for UHF RF CMOS circuits based on power consumption acuity is proposed in this paper. Through in-depth analysis of the static and dynamic power generation principle of UHF RF circuits in the work, the power consumption acuity can be calculated by using the correlation of circuit power and input vector. Subsequently, under the guide of this acuity, the UHF RF CMOS circuits with better energy saving can be designed. Furthermore, according to th

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37

SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C KHN FILTER USING VOLTAGE OP AMP, CFOA, OTRA AND DCVC." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 733–69. http://dx.doi.org/10.1142/s021812660900523x.

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MOS-C realizations of the Kerwin–Huelsman–Newcomb (KHN) circuit using the commercially available Voltage Operational Amplifier (VOA) and the Current Feedback Operational Amplifier (CFOA) are reviewed in this paper. Additional MOS-C KHN realizations using the Operational Transresistance Amplifier (OTRA) and the Differential Current Voltage Conveyor (DCVC) are also included. MOS-C realizations of the KHN circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS tech

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38

Mahnoor Maghroori and Mehdi Dolatshahi. "Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms." World Journal of Advanced Research and Reviews 12, no. 1 (2021): 215–24. http://dx.doi.org/10.30574/wjarr.2021.12.1.0427.

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This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed an

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SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C TOW-THOMAS FILTER USING VOLTAGE OP AMP, CURRENT FEEDBACK OP AMP AND OPERATIONAL TRANSRESISTANCE AMPLIFIER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 151–79. http://dx.doi.org/10.1142/s0218126609004995.

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Several MOS-C realizations of the Tow-Thomas circuit using the commercially available voltage operational amplifier and the current feedback operational amplifier are reviewed in this paper. Additional MOS-C Tow-Thomas realizations using the operational transresistance amplifier and the differential current voltage conveyor are also included. MOS-C realizations of the Tow-Thomas circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS

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40

Ghoshal, U., S. V. Kishore, A. R. Feldman, Luong Huynh, and T. Van Duzer. "CMOS amplifier designs for Josephson-CMOS interface circuits." IEEE Transactions on Appiled Superconductivity 5, no. 2 (1995): 2640–43. http://dx.doi.org/10.1109/77.403132.

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41

PRAMOD, M., and T. LAXMINIDHI. "LOW POWER CONTINUOUS TIME COMMON MODE SENSING FOR COMMON MODE FEEDBACK CIRCUITS." Journal of Circuits, Systems and Computers 19, no. 03 (2010): 519–28. http://dx.doi.org/10.1142/s0218126610006268.

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Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 μm CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27–34% less power than previous high swing CMFB circuits.

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Clark, David T., Ewan P. Ramsay, A. E. Murphy, et al. "High Temperature Silicon Carbide CMOS Integrated Circuits." Materials Science Forum 679-680 (March 2011): 726–29. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.726.

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The wide band-gap of Silicon Carbide (SiC) makes it a material suitable for high temperature integrated circuits [1], potentially operating up to and beyond 450°C. This paper describes the development of a 15V SiC CMOS technology developed to operate at high temperatures, n and p-channel transistor and preliminary circuit performance over temperature achieved in this technology.

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43

WAWRYN, KRZYSZTOF. "AN ARTIFICIAL INTELLIGENCE APPROACH TO ANALOG CIRCUIT DESIGN." Journal of Circuits, Systems and Computers 01, no. 02 (1991): 149–76. http://dx.doi.org/10.1142/s0218126691000033.

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This article deals with a new approach to an intelligent analog circuit design. The iterative closed loop design methodology adopts an expert system approach to provide topological synthesis, the SPICE circuit simulator to evaluate the circuit performance and a new approach of the diagnostic expert system to provide advice on how to improve the design. Unlike previous design methods, this approach introduces formal circuit representation for both numerical and heuristic knowledge of the design system. The predicate logic circuit representation is proposed to introduce a new concept of a formal

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Thompson, R. F., D. T. Clark, A. E. Murphy, et al. "High Temperature Silicon Carbide CMOS Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (2011): 000115–19. http://dx.doi.org/10.4071/hiten-paper5-dclark.

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The wide band-gap of Silicon Carbide makes it a material suitable for IC's [1] operating up to 450°C. The maximum operating temperature achieved will depend on the transistor technology selected, interconnect metallisation and device packaging. This paper describes transistor and circuit results achieved in SiC CMOS technology, where the major issue addressed is the gate dielectric performance. N and p-channel MOSFET structures have been demonstrated operating at temperatures up to 400°C Test circuits including simple logic cells, ring oscillators, operational amplifiers and gate drive circuit

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Leeser, Miriam, and Valerie Ohm. "Accurate Power Estimation for Sequential CMOS Circuits Using Graph-based Methods." VLSI Design 12, no. 2 (2001): 187–203. http://dx.doi.org/10.1155/2001/73872.

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We present a novel method for estimating the power of sequential CMOS circuits. Symbolic probabilistic power estimation with an enumerated state space is used to estimate the average power switched by the circuit. This approach is more accurate than simulation based methods. Automatic circuit partitioning and state space exploration provide improvements in run-time and storage requirements over existing approaches. Circuits are automatically partitioned to improve the execution time and to allow larger circuits to be processed. Spatial correlation is dealt with by minimizing the cutset between

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Awang Salleh, Dayang Nur Salmi Dharmiza, and Rohana Sapawi. "A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes." Applied Mechanics and Materials 833 (April 2016): 135–39. http://dx.doi.org/10.4028/www.scientific.net/amm.833.135.

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Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

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Aylapogu, Pramod Kumar, B. L. V. S. S. Aditya, G. Sony, et al. "Estimation of power and delay in CMOS circuits using LCT." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (2019): 990. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp990-998.

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<p>With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techn

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Sayed, Shimaa Ibrahim, Mostafa Mamdouh Abutaleb, and Zaki Bassuoni Nossair. "Optimization of CNFET Parameters for High Performance Digital Circuits." Advances in Materials Science and Engineering 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/6303725.

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The Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current d

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Setiabudi, Agung, Hiroki Tamura, and Koichi Tanno. "High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (2018): 4148. http://dx.doi.org/10.11591/ijece.v8i6.pp4148-4156.

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<p>A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and

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FOSSUM, JERRY G. "A SIMULATION-BASED PREVIEW OF EXTREMELY SCALED DOUBLE-GATE CMOS DEVICES AND CIRCUITS." International Journal of High Speed Electronics and Systems 12, no. 02 (2002): 563–72. http://dx.doi.org/10.1142/s0129156402001460.

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This paper gives a simulation-based preview of device-design issues and performance of extremely scaled DG CMOS. A suite of simulation tools, including a 2D numerical device simulator, a 1D numerical Poisson-Schrödinger solver, and a generic, physics/process-based DG MOSFET compact model in Spice, is applied to both asymmetrical-and symmetrical-gate DG CMOS devices and circuits to provide physical insight at the device and circuit levels. The results give added motivation as well as preliminary guidance for the development of DG CMOS.

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