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Dissertations / Theses on the topic 'Circuits - computer hardware'

Author: Grafiati

Published: 28 July 2024

Last updated: 31 July 2025

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1

Stamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.

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The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application t

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2

Dutta, Sumit Ph D. Massachusetts Institute of Technology. "Magnetic logic circuits with high bit resolution for hardware acceleration." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/111997.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 109-120).<br>The ever-increasing demand for high-performance and low-power computing warrants an investigation of technologies beyond conventional digital transistor circuits. We explore a logic device based on magnetic domai

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3

Staunstrup, Jørgen. "A formal approach to hardware design /." Boston [u.a.] : Kluwer Acad. Publ, 1994. http://www.loc.gov/catdir/enhancements/fy0820/93043582-d.html.

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4

Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

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5

Taesopapong, Somboon. "A VLSI-nMOS hardware implementation of a high speed parallel adder." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183379787.

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6

Basak, Abhishek. "INFRASTRUCTURE AND PRIMITIVES FOR HARDWARE SECURITY IN INTEGRATED CIRCUITS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=case1458787036.

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7

Meana, Richard William Piper. "Approximate Sub-Graph Isomorphism For Watermarking Finite State Machine Hardware." Scholar Commons, 2013. http://scholarcommons.usf.edu/etd/4728.

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We present a method of mitigating theft of sequential circuit Intellectual Property hardware designs through means of watermarking. Hardware watermarking can be performed by selectively embedding a watermark in the state encoding of the Finite State Machine. This form of watermarking can be achieved by matching a directed graph representation of the watermark with a sub-graph in state transition graph representation of the FSM. We experiment with three approaches: a brute force method that provides a proof of concept, a greedy algorithm that provides excellent runtime with a drawback of sub-op

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8

Imvidhaya, Ming. "VHDL simulation of the implementation of a costfunction circuit." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA240430.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990.<br>Thesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.

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9

Chu, Ming-Cheung. "Hazard detection with VHDL in combinational logic circuits with fixed delays." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10062009-020040/.

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10

Moseley, Ralph. "Transcending static deployment of circuits : dynamic run-time systems and mobile hardware processes for FPGAs." Thesis, University of Kent, 2002. https://kar.kent.ac.uk/13733/.

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The usefulness of reconfigurable hardware has been shown in research and commercial applications. Unquestionably, this has and will lead to, unique avenues of thought within computer science being explored. The interest by researchers in some specific areas has led to manufacturers developing devices which were enhanced in their ability to dynamically be configured within a run-time context. These improvements are on-going and rapid progress is being made, producing high density, system-on-a-chip capable devices, with fast run-time reconfiguration. The advancements in this technology have part

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11

Khairullah, Shawkat Sabah. "Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices." VCU Scholars Compass, 2018. https://scholarscompass.vcu.edu/etd/5671.

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Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes. One of the more essential concepts for achieving this goal is the notion of resilient and survivable digital I&C systems. In recent years, self-healing concepts based on biological physiology have received attention for the design of robust digital systems. However, many of these approaches have not been architected from the outset with safety in mind, nor have they been targeted for the automation c

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12

Ardeishar, Raghu. "Automatic verification of VHDL models." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/.

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13

Pan, Bi-Yu. "Hierarchical test generation for VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-09052009-040449/.

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14

Thulasi, Raman Sudheer Ram. "Logic Encryption of Sequential Circuits." University of Cincinnati / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143.

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15

Palanisamy, Karthikeyan. "High Level Preprocessor of a VHDL-based Design System." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4776.

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This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL -based DIADES system into a VHDL -based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL -based design system from Mentor Graphics. The high-level synthesis in the DIADES system includes two stages: data

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16

Kapoor, Shekhar. "Process level test generation for VHDL behavioral models." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-05022009-040753/.

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17

Narayanaswamy, Sathyanarayanan. "Development of VHDL behavioral models with back annotated timing." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06112009-063442/.

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18

Vamja, Harsh. "Reverse Engineering of Finite State Machines from Sequential Circuits." University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1530267556456191.

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19

Schaeffer, Ben. "Synthesis of Linear Reversible Circuits and EXOR-AND-based Circuits for Incompletely Specified Multi-Output Functions." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3783.

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At this time the synthesis of reversible circuits for quantum computing is an active area of research. In the most restrictive quantum computing models there are no ancilla lines and the quantum cost, or latency, of performing a reversible form of the AND gate, or Toffoli gate, increases exponentially with the number of input variables. In contrast, the quantum cost of performing any combination of reversible EXOR gates, or CNOT gates, on n input variables requires at most O(n2/log2n) gates. It was under these conditions that EXOR-AND-EXOR, or EPOE, synthesis was developed. In this work, the G

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20

Franz, Jonathan D. Duren Russell Walker. "An evaluation of CoWare Inc.'s Processor Designer tool suite for the design of embedded processors." Waco, Tex. : Baylor University, 2008. http://hdl.handle.net/2104/5254.

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21

O'Hara, Joshua Martin. "TouchSPICE vs. ReActive-SPICE: A Human-Computer Interaction Perspective." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/845.

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Traditional SPICE simulation tools and applications of circuit theory lack real-time interaction and feedback. The goal of this thesis was to create an interactive physical environment to allow the manipulation and simulation of discrete electrical components in near-real-time while optimizing and streamlining the human-computer interaction (HCI) elements to make the user experience as positive and transparent as possible. This type of HCI and near-real-time simulation feedback would allow for the instant realization of how the parameters of each discrete component or hardware module affect th

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22

Chaparro-Baquero, Gustavo A. "Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems." FIU Digital Commons, 2018. https://digitalcommons.fiu.edu/etd/3712.

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As a major component of a computing system, memory has been a key performance and power consumption bottleneck in computer system design. While processor speeds have been kept rising dramatically, the overall computing performance improvement of the entire system is limited by how fast the memory can feed instructions/data to processing units (i.e. so-called memory wall problem). The increasing transistor density and surging access demands from a rapidly growing number of processing cores also significantly elevated the power consumption of the memory system. In addition, the interference of m

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23

Scheiblauer, Kristopher S. "Quadded GasP: a Fault Tolerant Asynchronous Design." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3475.

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As device scaling continues, process variability and defect densities are becoming increasingly challenging for circuit designers to contend with. Variability reduces timing margins, making it difficult and time consuming to meet design specifications. Defects can cause degraded performance or incorrect operation resulting in circuit failure. Consequently test times are lengthened and production yields are reduced. This work assess the combination of two concepts, self-timed asynchronous design and fault tolerance, as a possible solution to both variability and defects. Asynchronous design is

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24

Goto, Samuel Shoji Fukujima. "Síntese de linguagens de descrição de arquitetura." [s.n.], 2010. http://repositorio.unicamp.br/jspui/handle/REPOSIP/275779.

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Orientador: Rodolfo Jardim de Azevedo<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação<br>Made available in DSpace on 2018-08-17T02:11:17Z (GMT). No. of bitstreams: 1 Goto_SamuelShojiFukujima_M.pdf: 4578638 bytes, checksum: c8297ac26a037d8b90ccb1c1ad3d6c43 (MD5) Previous issue date: 2010<br>Resumo: Desde sua popularização, processadores dobraram de capacidade e desempenho à cada dois anos. No entanto, paralelamente, essa tendência foi apenas sustentada pelo crescimento da sofisticação das implementações utilizadas. Atualmente, apesar de eficientes, proce

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25

Chakkaravarthy, Manoj. "BDD Based Synthesis Flow for Design of DPA Resistant Cryptographic Circuits." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1330025314.

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26

Kumar, Sharad Kumar. "Analysis of Machine Learning Modeling Attacks on Ring Oscillator based Hardware Security." University of Toledo / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1541759752027838.

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27

Chandorkar, Chaitrali Santosh. "Data Driven Feed Forward Adaptive Testing." PDXScholar, 2013. https://pdxscholar.library.pdx.edu/open_access_etds/1049.

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Test cost is a critical component in the overall cost of the product. Test cost varies in direct proportion with test time. This thesis introduces a data driven feed forward adaptive technique for reducing test time at wafer sort while maintaining the product defect level. Test data from first insertion of wafer is statistically analyzed to make a decision about adaptive test flow at subsequent insertions. The data driven feed forward technique uses a statistical screen to analyze test data from first probe of wafer and provides recommendations for test elimination at second insertions. At the

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28

Hoffman, Joseph A. "VHDL modeling of ASIC power dissipation." Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/.

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29

Webb, Robert L. "ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/381.

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The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronou

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30

De, Guzman Ethan Paul Palisoc. "Energy Efficient Computing using Scalable General Purpose Analog Processors." DigitalCommons@CalPoly, 2021. https://digitalcommons.calpoly.edu/theses/2305.

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Due to fundamental physical limitations, conventional digital circuits have not been able to scale at the pace expected from Moore’s law. In addition, computationally intensive applications such as neural networks and computer vision demand large amounts of energy from digital circuits. As a result, energy efficient alternatives are needed in order to provide continued performance scaling. Analog circuits have many well known benefits: the ability to store more information onto a single wire and efficiently perform mathematical operations such as addition, subtraction, and differential equatio

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31

Ajdari, Bahar. "Laser as a Tool to Study Radiation Effects in CMOS." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3769.

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Energetic particles from cosmic ray or terrestrial sources can strike sensitive areas of CMOS devices and cause soft errors. Understanding the effects of such interactions is crucial as the device technology advances, and chip reliability has become more important than ever. Particle accelerator testing has been the standard method to characterize the sensitivity of chips to single event upsets (SEUs). However, because of their costs and availability limitations, other techniques have been explored. Pulsed laser has been a successful tool for characterization of SEU behavior, but to this day,

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32

Joshi, Anand Mukund. "Behavioral delay fault modeling and test generation." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-07292009-090436/.

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33

Yanambaka, Venkata Prasanth. "Exploring Physical Unclonable Functions for Efficient Hardware Assisted Security in the IoT." Thesis, University of North Texas, 2019. https://digital.library.unt.edu/ark:/67531/metadc1505261/.

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Modern cities are undergoing rapid expansion. The number of connected devices in the networks in and around these cities is increasing every day and will exponentially increase in the next few years. At home, the number of connected devices is also increasing with the introduction of home automation appliances and applications. Many of these appliances are becoming smart devices which can track our daily routines. It is imperative that all these devices should be secure. When cryptographic keys used for encryption and decryption are stored on memory present on these devices, they can be retrie

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34

Leija, Antonio M. "AN INVESTIGATION INTO PARTITIONING ALGORITHMS FOR AUTOMATIC HETEROGENEOUS COMPILERS." DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1546.

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Automatic Heterogeneous Compilers allows blended hardware-software solutions to be explored without the cost of a full-fledged design team, but limited research exists on current partitioning algorithms responsible for separating hardware and software. The purpose of this thesis is to implement various partitioning algorithms onto the same automatic heterogeneous compiler platform to create an apples to apples comparison for AHC partitioning algorithms. Both estimated outcomes and actual outcomes for the solutions generated are studied and scored. The platform used to implement the algorithms

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35

Lee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers." DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.

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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly. A meth

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36

Bondehagen, Brent. "FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT." UKnowledge, 2013. http://uknowledge.uky.edu/ece_etds/23.

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Structured Light Illumination (SLI) is the process where spatially varied patterns are projected onto a 3-D surface and based on the distortion by the surface topology, phase information can be calculated and a 3D model constructed. Phase Measuring Profilometry (PMP) is a particular type of SLI that requires three or more patterns temporarily multiplexed. High speed PMP attempts to scan moving objects whose motion is small so as to have little impact on the 3-D model. Given that practically all machine vision cameras and high speed cameras employ a Field Programmable Gate Array (FPGA) interfac

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37

Fitzsimmons, Sean. "Reliable Software Updates for On-orbit CubeSat Satellites." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/804.

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CubeSat satellites have redefined the standard solution for conducting missions in space due to their unique form factor and cost. The harsh environment of space necessitates examining features that improve satellite robustness and ultimately extend lifetime, which is typical and vital for mission success. The CubeSat development team at Cal Poly, PolySat, has recently redefined its standard avionics platform to support more complex mission capabilities with this robustness in mind. A significant addition was the integration of the Linux operating system, which provides the flexibility to deve

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38

Joginipelly, Arjun Kumar. "Efficient FPGA Architectures for Separable Filters and Logarithmic Multipliers and Automation of Fish Feature Extraction Using Gabor Filters." ScholarWorks@UNO, 2014. http://scholarworks.uno.edu/td/1876.

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Convolution and multiplication operations in the filtering process can be optimized by minimizing the resource utilization using Field Programmable Gate Arrays (FPGA) and separable filter kernels. An FPGA architecture for separable convolution is proposed to achieve reduction of on-chip resource utilization and external memory bandwidth for a given processing rate of the convolution unit. Multiplication in integer number system can be optimized in terms of resources, operation time and power consumption by converting to logarithmic domain. To achieve this, a method altering the filter weights

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39

Chen, Amy. "Oceanographic Instrument Simulator." DigitalCommons@CalPoly, 2016. https://digitalcommons.calpoly.edu/theses/1585.

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The Monterey Bay Aquarium Research Institute (MBARI) established the Free Ocean Carbon Enrichment (FOCE) experiment to study the long-term effects of decreased ocean pH levels by developing in-situ platforms [1]. Deep FOCE (dpFOCE) was the first platform, which was deployed in 950 meters of water in Monterey Bay. After the conclusion of dpFOCE, MBARI developed an open source shallow water FOCE (swFOCE) platform located at around 250 meter of water to facilitate worldwide shallow water experiments on FOCE [1][2]. A shallow water platform can be more ubiquitous than a deep-water platform as shal

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40

Sanchez, Delano Christopher. "A circuit based Evolvable Hardware Architecture." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37919.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.<br>Includes bibliographical references (p. 69-72).<br>This thesis presents an Evolvable Hardware Architecture that was developed in the Quantum Nanostructures and Nanofabrication Laboratory. We believe intrinsic evolution is a promising tool that can be used to exploit the physics of complex systems. I present a reconfigurable analog circuit platform that is coupled with a genetic algorithm to evolve circuit functions. The design process is detailed along with the results of three

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41

Khan, Muhammad S. "Design and Development of Smart Brain-Machine-Brain Interface (SBMIBI) for Deep Brain Stimulation and Other Biomedical Applications." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2724.

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Machine collaboration with the biological body/brain by sending electrical information back and forth is one of the leading research areas in neuro-engineering during the twenty-first century. Hence, Brain-Machine-Brain Interface (BMBI) is a powerful tool for achieving such machine-brain/body collaboration. BMBI generally is a smart device (usually invasive) that can record, store, and analyze neural activities, and generate corresponding responses in the form of electrical pulses to stimulate specific brain regions. The Smart Brain-Machine-Brain-Interface (SBMBI) is a step forward with compar

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42

Marusiak, David. "MOS CURRENT MODE LOGIC (MCML) ANALYSIS FOR QUIET DIGITAL CIRCUITRY AND CREATION OF A STANDARD CELL LIBRARY FOR REDUCING THE DEVELOPMENT TIME OF MIXED-SIGNAL CHIPS." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1363.

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Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, no

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43

Pasca, Bogdan Mihai. "Calcul flottant haute performance sur circuits reconfigurables." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2011. http://tel.archives-ouvertes.fr/tel-00654121.

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De plus en plus de constructeurs proposent des accélérateurs de calculs à base de circuits reconfigurables FPGA, cette technologie présentant bien plus de souplesse que le microprocesseur. Valoriser cette flexibilité dans le domaine de l'accélération de calcul flottant en utilisant les langages de description de circuits classiques (VHDL ou Verilog) reste toutefois très difficile, voire impossible parfois. Cette thèse a contribué au développement du logiciel FloPoCo, qui offre aux utilisateurs familiers avec VHDL un cadre C++ de description d'opérateurs arithmétiques génériques adapté au calcu

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Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.

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Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis p

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Hu, Jhy-Fang 1961. "AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276948.

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Sake, Lekhya Sai. "ESTIMATION ON GIBBS ENTROPY FOR AN ENSEMBLE." CSUSB ScholarWorks, 2015. https://scholarworks.lib.csusb.edu/etd/264.

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In this world of growing technology, any small improvement in the present scenario would create a revolution. One of the popular revolutions in the computer science field is parallel computing. A single parallel execution is not sufficient to see its non-deterministic features, as same execution with the same data at different time would end up with a different path. In order to see how non deterministic a parallel execution can extend up to, creates the need of the ensemble of executions. This project implements a program to estimate the Gibbs Entropy for an ensemble of parallel executions. T

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47

Moussa, Imed. "Applications des circuits numériques en arseniure de gallium dans les systèmes à haut débit de communication et dans les calculateurs performants." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0077.

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Ce document presente diverses applications des circuits numeriques en arseniure de gallium (asga) dans les systemes a haut debit de communication et dans les calculateurs performants. Ces applications ont guidees l'ensemble des recherches effectuees au cours de la these dont ce document est l'aboutissement. La necessite de performances elevees, inherentes aux applications traitees, a necessite l'etude et la mise en uvre de topologies differentes qui ont donne lieu a un ensemble de solutions efficaces. Dans le but d'obtenir une marge de bruit assez elevee et de bonnes performances en vitesse, e

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48

Yang, Xiaokun. "A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2477.

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With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can fram

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49

Marathe, Vikrant A. "Analog Single Sideband-Pulse Width Modulation Processor for Parametric Acoustic Arrays." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2056.

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Parametric acoustic arrays are ultrasonic-based loudspeakers that produce highly directive audio. The audio must first be preprocessed and modulated into an ultrasonic carrier before being emitted into the air, where it will self-demodulate in the far field. The resulting audio wave is proportional to the double time-derivative of the square of the modulation envelope. This thesis presents a fully analog processor which encodes the audio into two Pulse Width Modulated (PWM) signals in quadrature phase and sums them together to produce a Single Sideband (SSB) spectrum around the fundamental fre

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King, Matthew E. "Linear Power-Efficient RF Amplifier with Partial Positive Feedback." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/811.

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Abstract:

Over the last decade, the number of mobile wireless devices on the market has increased substantially. New “multi-carrier” modulation schemes, such as OFDM, WCDMA, and WiMAX, have been developed to accommodate the increasing number of wireless subscribers and the demand for faster data rates within the limited commercial frequency spectrum. These complex modulation schemes create signals with high peak-to-average power ratios (PAPR), exhibiting rapid changes in the signal magnitude. To accommodate these high-PAPR signals, RF power amplifiers in mobile devices must operate under backed-off gain

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