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Journal articles on the topic 'Circuits digitaux'

Author: Grafiati

Published: 4 June 2021

Last updated: 28 January 2023

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1

Alexeyev, Alexander A., and Michael M. Green. "Secure Communications Based on Variable Topology of Chaotic Circuits." International Journal of Bifurcation and Chaos 07, no. 12 (1997): 2861–69. http://dx.doi.org/10.1142/s0218127497001941.

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A new technique for synchronization of chaotic circuits is proposed. This technique, based on varying a circuit's overall topology rather than varying a set of continuous parameters, offers a possible resolution to the tradeoff between security and synchronizability inherent in existing chaotic systems. The encryption key is represented by a mapping from a set of nodes to a set of switches in the circuit. This method significantly improves reliability and can be easily interfaced to digital control circuits.

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2

Raman, Karthik, and Andreas Wagner. "The evolvability of programmable hardware." Journal of The Royal Society Interface 8, no. 55 (2010): 269–81. http://dx.doi.org/10.1098/rsif.2010.0212.

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In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly u

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Stavrinidou, Eleni, Roger Gabrielsson, Eliot Gomez, et al. "Electronic plants." Science Advances 1, no. 10 (2015): e1501136. http://dx.doi.org/10.1126/sciadv.1501136.

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The roots, stems, leaves, and vascular circuitry of higher plants are responsible for conveying the chemical signals that regulate growth and functions. From a certain perspective, these features are analogous to the contacts, interconnections, devices, and wires of discrete and integrated electronic circuits. Although many attempts have been made to augment plant function with electroactive materials, plants’ “circuitry” has never been directly merged with electronics. We report analog and digital organic electronic circuits and devices manufactured in living plants. The four key components o

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4

D., Vaithiyanathan, Megha Singh Kurmi, Alok Kumar Mishra, and Britto Pari J. "Performance analysis of multi-scaling voltage level shifter for low-power applications." World Journal of Engineering 17, no. 6 (2020): 803–9. http://dx.doi.org/10.1108/wje-02-2020-0043.

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Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need f

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Pawase, Ramesh, and N. P. Futane. "MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 2 (2018): 120. http://dx.doi.org/10.11591/ijres.v6.i2.pp120-126.

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<p>Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed. A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with le

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Farmer, Hugo S. W. "How Do You Qualify as a Whistleblower Under The Dodd-Frank Act? Blowing the Whistle on a Circuit Split." Journal of Law and Commerce 36, no. 2 (2018): 101–30. http://dx.doi.org/10.5195/jlc.2018.139.

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Recently, a circuit split has arisen with regard to the Dodd-Frank Wall Street Reform and Consumer Protection Act. The circuit split concerns the question of what it takes for an individual to qualify as a “whistleblower” under the terms of the statute. This circuit split is surprising, as the Dodd- Frank Act purports to answer this question itself by providing a definition of this term, a definition which the Fifth Circuit has treated as being conclusive. Nonetheless, the Second and the Ninth Circuits have held that with respect to some, but not all, of the Dodd-Frank Act, this statutory “whi

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JimÃ©nez, Alejandro DueÃ±as, and Francisco JimÃ©nez HernÃ¡ndez. "Confirming the Signal Integrity in Transmission of Digital Signals on Microstrip Straight Circuits via the Eye Diagrams." JOURNAL OF ADVANCES IN PHYSICS 5, no. 1 (2014): 737–41. http://dx.doi.org/10.24297/jap.v5i1.1972.

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Because of the high volume of processing, transmission, and information storage, electronic systems presently requires faster clock speeds tosynchronizethe integrated circuits. Presently the â€œspeedsâ€ on the connections of a printed circuit board (PCB) are in the order of the GHz. At these frequencies the behavior of the interconnects are more like that of a transmission line, and hence distortion, delay, and phase shift- effects caused by phenomena like cross talk, ringing and over shot are present and may be undesirable for the performance of a circuit or system.Some of these phrases were

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8

Zhang, Xiao Feng, Fo Chang Xie, Guo Wei Yang, and Wei Zhang. "The Transceiver Circuit Design of Digital Ultrasonic System." Advanced Materials Research 834-836 (October 2013): 968–73. http://dx.doi.org/10.4028/www.scientific.net/amr.834-836.968.

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This paper introduces the design process of the digital ultrasonic transmission circuit: echo receiving circuit and the echo signal regulate circuit. Among them, outside 500 V DC - DC module for high voltage power input, use non-tuned type circuit design ultrasonic transmission circuit ; Select high voltage fast recovery diode FR107 design echo receiving limiter circuit; Using ultra-high speed, low noise, low distortion of the integrated operational amplifier MAX4104ESA design preamplifier circuits and the band-pass filter circuits; Using linear decibels, low noise, wide bandwidth, high gain a

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CARD, HOWARD C., DEAN K. McNEILL, CHRISTIAN R. SCHNEIDER, ROLAND S. SCHNEIDER, and BRION K. DOLENKO. "TOLERANCE OF ON-CHIP LEARNING TO VARIOUS CIRCUIT INACCURACIES." Journal of Circuits, Systems and Computers 08, no. 02 (1998): 315–27. http://dx.doi.org/10.1142/s0218126698000146.

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An investigation is made of the tolerance of various in-circuit learning algorithms to component imprecision and other circuit limitations in artificial neural networks. In contrast with most previous work, the various circuit limitations are treated separately for their effects on learning. Supervised learning mechanisms including backpropagation and contrastive Hebbian learning, and unsupervised soft competitive learning were found to be sufficiently tolerant of those levels of arithmetic inaccuracy, noise, nonlinearity, weight decay, and statistical variation from fabrication that we have e

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10

Ferreira Pontes, Matheus, Clayton Farias, Rafael Schvittz, Paulo Butzen, and Leomar Da Rosa Jr. "Survey on Reliability Estimation in Digital Circuits." Journal of Integrated Circuits and Systems 16, no. 3 (2021): 1–11. http://dx.doi.org/10.29292/jics.v16i3.568.

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The aggressive technology scaling has significantly affected the circuit reliability. The interaction of environmental radiation with the devices in the integrated circuits (ICs) may be the dominant reliability aspect of advanced ICs. Several techniques have been explored to mitigate the radiation effects and guarantee a satisfactory reliability levels. In this context, estimating circuit radiation reliability is crucial and a challenge that has not yet been overcome. For decades, several different methods have been proposed to provide circuit reliability. Recently, the radiation effects have

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11

Shiri, Ahmadreza, Abdalhossein Rezai, and Hamid Mahmoodian. "Design of efficient coplanar 1-bit comparator circuit in QCA technology." Facta universitatis - series: Electronics and Energetics 32, no. 1 (2019): 119–28. http://dx.doi.org/10.2298/fuee1901119s.

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QCA technology is an emerging and promising technology for implementation of digital circuits in nano-scale. The comparator circuits play an important role in digital circuits. In this work, a new and efficient coplanar 1-bit comparator circuit is proposed and evaluated in the QCA technology. The designed coplanar 1-bit QCA comparator circuit is constructed based on majority gate, XNOR gate and inverter gate that are designed carefully. The functionality of the designed coplanar 1-bit QCA comparator circuit is verified by using QCADesigner version 2.0.3. The obtained results indicate that the

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Schmidt, Alexander, Holger Kappert, Wolfgang Heiermann, and Rainer Kokozinski. "A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (2012): 000214–19. http://dx.doi.org/10.4071/hitec-2012-wp13.

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Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation,

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Gavrilenkov, Sergey I., Elizaveta O. Petrenko, and Evgeny V. Arbuzov. "A Digital Device for Automatic Checking of Homework Assignments in the Digital Circuits Course." ITM Web of Conferences 35 (2020): 04009. http://dx.doi.org/10.1051/itmconf/20203504009.

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This paper considers a digital device for automatic checking of homework assignments in the digital circuits course. The assignment is to make a digital circuit corresponding to a given logical expression; the circuit is comprised of elementary logic gates. The process of manual testing the built circuit is very labor-intensive because checking a circuit with N inputs variables requires checking the correctness of the output variable for 2N cases. We propose automating this pro-cess with a special digital device. The device is comprised of a microcontroller connected to the circuit tested. The

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14

Mokhtarnia, Hossein, Shahram Etemadi Borujeni, and Mohammad Saeed Ehsani. "Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults." Journal of Circuits, Systems and Computers 28, no. 14 (2019): 1950240. http://dx.doi.org/10.1142/s0218126619502402.

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Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the propo

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15

Gu, Youzhi, Xinjie Feng, Runze Chi, Jiangfeng Wu, and Yongzhen Chen. "A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver." Electronics 11, no. 21 (2022): 3489. http://dx.doi.org/10.3390/electronics11213489.

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With the great increases in data transmission rate requirements, analog-to-digital converter (ADC)-based wireline receivers have received more and more attention due to their flexible and powerful equalization capabilities. Considering power consumption, baud-rate Mueller–Muller clock and data recovery (MM-CDR) circuits are widely used in ADC-based wireline receivers since MM-CDR circuits only need one sample signal per unit interval (UI). However, MM-CDR circuits need to set an additional Vref voltage to match the size of the main tap of the channel. If the Vref matching is not appropriate or

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16

Soeleman, H., K. Roy, and Tan-Li Chou. "Estimating circuit activity in combinational CMOS digital circuits." IEEE Design & Test of Computers 17, no. 2 (2000): 112–19. http://dx.doi.org/10.1109/54.844340.

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Strle, Drago, та Janez Trontelj. "On Self-Aware Mixed-Signal Systems Based on S-Δ ADC". International Journal of Embedded and Real-Time Communication Systems 3, № 2 (2012): 92–110. http://dx.doi.org/10.4018/jertcs.2012040105.

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In this paper the authors discuss the issues related to the self-awareness of high-resolution, mixed-signal circuits and systems, based on S-? ADC, which is the most important and sensitive module and the key element for analogue to digital conversion. The basic methodology and framework for improving the self-awareness of such systems are presented. The methodology is based on efficient real-time measurements of a high-resolution, mixed-signal system using pseudo random signal source, real-time calculation of a distance between responses, the possibility to adapt measured circuit to minimize

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18

Pour Aryan, N., L. Heiß, D. Schmitt-Landsiedel, G. Georgakos, and M. Wirnshofer. "Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling." Advances in Radio Science 10 (September 18, 2012): 215–20. http://dx.doi.org/10.5194/ars-10-215-2012.

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Abstract. In Adaptive Voltage Scaling (AVS) the supply voltage of digital circuits is tuned according to the circuit's actual operating condition, which enables dynamic compensation to PVTA variations. By exploiting the excessive safety margins added in state-of-the-art worst-case designs considerable power saving is achieved. In our approach, the operating condition of the circuit is monitored by in-situ delay monitors. This paper presents different designs to implement the in-situ delay monitors capable of detecting late but still non-erroneous transitions, called Pre-Errors. The developed P

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Santhi, C., and Dr Moparthy Gurunadha Babu. "Symmetric stacked fast binary counters based on reversible logic." International Journal of Engineering & Technology 7, no. 4 (2018): 2747. http://dx.doi.org/10.14419/ijet.v7i4.14141.

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A Symmetric Stacked Fast Binary counter design is proposed in this paper. In the circuit design, the first phase is occupied by 3-bit stacking circuits, which are further followed by combining circuits. The resultant novel circuit thus becomes a 6-bit stacker. A 6:3 counter has been chosen as an example to demonstrate the working of the proposed circuit. The proposed circuit is further implemented by using reversible logic gates. Heat dissipation is a major problem in the designing of a digital circuit. Rolf Landauer has proved that the information loss in a digital circuit is directly proport

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20

Frank, Steve. "Brief Introduction to High Speed Analog Failure Analysis." EDFA Technical Articles 5, no. 3 (2003): 23–28. http://dx.doi.org/10.31399/asm.edfa.2003-3.p023.

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Abstract This article provides a high level overview of high speed analog circuits and associated failure analysis techniques. It discusses the failure modes and mechanisms of voltage reference circuits, high speed op amps, and digital-to-analog and analog-to-digital converters, the fundamental building blocks used to create high speed analog devices. It also explains how to deal with difficulties involving circuit node access, circuit loading, and performance.

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Pan, Zhong Liang, and Ling Chen. "Test Method for Crosstalk Faults in VLSI Circuits Based on Multiple-Valued Decision Diagrams." Applied Mechanics and Materials 20-23 (January 2010): 641–46. http://dx.doi.org/10.4028/www.scientific.net/amm.20-23.641.

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The crosstalk fault in VLSI circuits is one of the interference effects being caused by parasitic capacitance and inductance coupling, it can lead to functional errors of circuits. It is necessary to detect the crosstalk faults in order to insure the functions of circuits. A new test method for crosstalk faults in VLSI circuits based on multiple-valued decision diagrams is presented in this paper, the test vectors of crosstalk faults are generated by building a multiple-valued decision diagram that is a difference operation of the two multiple-valued decision diagrams corresponding to the norm

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22

Dereli, Serkan, and Mahmut Uç. "Exponential Computing Digital Circuit Design Developed for FPGA-based Embedded Systems." Academic Perspective Procedia 3, no. 1 (2020): 291–300. http://dx.doi.org/10.33793/acperpro.03.01.59.

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Digital systems consist of thousands of digital circuit blocks operating in the background, working in their simplest form such as addition, subtraction, multiplication, division. In exponential expressions like square roots and cube roots, just like these circuits, it is found in many digital systems and performs tasks. Although these processes seem to be used only in circuits carrying out mathematical operations, they actually take an active role in solving many engineering problems. In this study, a digital circuit design that computes both the integer and a floating point exponent of a 32-

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Jurnal, Redaksi Tim. "RANCANGAN RANGKAIAN ANTI BOUNCING UNTUK RANGKAIAN DIGITAL." Sutet 7, no. 1 (2018): 24–31. http://dx.doi.org/10.33322/sutet.v7i1.168.

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Push-On switches or toggle switches and mechanical relays are mechanical contacts made of metal which, when supplied with electric current, will result in a spike of electrical sparks, called Bouncing Effects. Bounce effects are often a problem in digital circuits, especially in digital electronics circuits, because these Bounce Effects will cause the value of data or signals coming into the circuit inaccurate or indeterminate, when the mechanical switch is pressed as input data. This will undoubtedly lead to undesirable conditions and must be overcome with an electronic circuit called De-Boun

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Seyedi, Saeid, Nima Jafari Navimipour, and Akira Otsuki. "A New Nano-Scale and Energy-Optimized Reversible Digital Circuit Based on Quantum Technology." Electronics 11, no. 23 (2022): 4038. http://dx.doi.org/10.3390/electronics11234038.

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A nano-scale quantum-dot cellular automaton (QCA) is one of the most promising replacements for CMOS technology. Despite the potential advantages of this technology, QCA circuits are frequently plagued by numerous forms of manufacturing faults (such as a missing cell, extra cell, displacement cell, and rotated cell), making them prone to failure. As a result, in QCA technology, the design of reversible circuits has received much attention. Reversible circuits are resistant to many kinds of faults due to their inherent properties and have the possibility of data reversibility, which is importan

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Li, Huang, and Li Feng Lin. "Design of a Digital Breathing Rate Tester Circuit." Applied Mechanics and Materials 556-562 (May 2014): 2161–64. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.2161.

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Digital breathing rate tester uses amplifier circuit, filter circuit, shaping circuit, and frequency quadruplicator circuit to process respiration signals. The signals processed are mixed with signals from logic controller circuit, pass the NAND gate, combine with signals from NAND gate and enter the pulse counter circuit. Pulse counter circuit’s digital tube shows the breathing rates.

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Kerschbaumer, Ricardo, Robson R. Linhares, Jean M. Simão, Paulo C. Stadzisz, and Carlos R. Erig Lima. "Notification-Oriented Paradigm to Implement Digital Hardware." Journal of Circuits, Systems and Computers 27, no. 08 (2018): 1850124. http://dx.doi.org/10.1142/s0218126618501244.

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The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C/C[Formula: see text] derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (N

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Dokic, B. L. "A Review on Energy Efficient CMOS Digital Logic." Engineering, Technology & Applied Science Research 3, no. 6 (2013): 552–61. http://dx.doi.org/10.48084/etasr.389.

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Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in th

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Maris Ferreira, Pietro, Emilie Avignon-Meseldzija, Philippe Bénabès, and Francis Trélin. "Surface versus Performance Trade-offs: A Review of Layout Techniques." Journal of Integrated Circuits and Systems 17, no. 1 (2022): 1–16. http://dx.doi.org/10.29292/jics.v17i1.589.

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Selecting the relevant layout techniques is a key point to obtain a high-performance integrated circuit. Most of the common layout techniques, beside allowing the improvement of performance, also leads to an area overhead. Moreover, this area overhead is generally not accurately evaluated. It is proposed in this review to analyze and to evaluate the surface versus performance trade-off in three types of circuits : digital, low-frequency and radiofrequency analog circuits. Each circuit is post-layout simulated using BiCMOS SiGe 55 nm technology from STMicroelectronics. The first analysis evalua

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Žemva, Andrej, Andrej Trost, and Baldomir Zajc. "Educational Programmable System for Prototyping Digital Circuits." International Journal of Electrical Engineering & Education 35, no. 3 (1998): 236–44. http://dx.doi.org/10.1177/002072099803500306.

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In this paper, we present an educational programmable system for prototyping digital circuits. The system is composed of the PC and the prototyping board composed of 3 FPGAs. PC is used for designing a digital circuit, programming the FPGAs, automatic generation of the interface logic and hardware verification of the designed circuit.

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Hou, Yue Wei, Xin Xu, Wei Wang, Xiao Bo Tian, and Hai Jun Liu. "Titanium Oxide Memristor Based Digital Encoder Circuit." Applied Mechanics and Materials 644-650 (September 2014): 3430–33. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3430.

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Memristors have the ability to remember their last resistance and quickly switch between different states, such characteristics could make logic circuits simple in structure and fast in boolean computations. A kind of digital encoder circuit utilizing titanium oxide memristors is proposed. A logic NAND gate which acts as key part in the circuit is designed. The works in this letter also provide a practical approach for designing logic gate circuit with memristors.

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Kobayashi, Haruo, and Anna Kuwana. "Study of analog-to-digital mixed integrated circuit configuration using number theory." Impact 2022, no. 3 (2022): 9–11. http://dx.doi.org/10.21820/23987073.2022.3.9.

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Electronic circuits form the basis of much of the technology we use today. Professor Haruo Kobayashi and Assistant Professor Anna Kuwana, Division of Electronics and Informatics, Gunma University, Japan, are utilising classical mathematics, including theorems such as number theory and control theory in their design of circuits that contain elements of analogue signalling. Analogue circuit planning is regarded as an art as these circuits are typically designed based on mature designers' intuition and experiences in a process that is less systematic for coming up with new architectures and more

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Mahnoor Maghroori and Mehdi Dolatshahi. "Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms." World Journal of Advanced Research and Reviews 12, no. 1 (2021): 215–24. http://dx.doi.org/10.30574/wjarr.2021.12.1.0427.

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This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed an

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Ali, Mumtaz, and Osman Hasan. "SAT Based Fitness Scoring for Digital Circuit Evolution." Journal of Circuits, Systems and Computers 27, no. 06 (2018): 1850099. http://dx.doi.org/10.1142/s0218126618500998.

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Evolutionary computation uses Darwinian principles to find solutions from a given search space and forms the basis for evolving digital circuits. One of the most computationally expensive steps in evolutionary computation is the comparison of the candidate circuit or chromosome with the target truth table. We propose to use a satisfiability solver, to improve upon the efficiency of this process, which is traditionally done using exhaustive simulation. The paper presents an implementation of the satisfiability solver, which is in turn used to develop a digital circuit evolution methodology base

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Rashidi, Hamid, and Abdalhossein Rezai. "Design of novel multiplexer circuits in QCA nanocomputing." Facta universitatis - series: Electronics and Energetics 34, no. 1 (2021): 105–14. http://dx.doi.org/10.2298/fuee2101105r.

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Quantum-dot Cellular Automata (QCA) technology is a promising alternative nano-scale technology for CMOS technology. In digital circuits, a multiplexer is one of the most important components. In this study, an efficient and single layer 2 to 1 QCA multiplexer circuit is proposed using majority gate and inverter gate. In addition, efficient 4 to 1 and 8 to 1 QCA multiplexer circuits are implemented using this 2 to 1 multiplexer circuit. The developed multiplexer circuits are implemented in QCADesigner tool. According to the results, the developed 2 to 1, 4 to 1, and 8 to 1 multiplexer circuits

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Pan, Zhong Liang, and Ling Chen. "A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams." Applied Mechanics and Materials 29-32 (August 2010): 1040–45. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.1040.

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The formal verification is able to check whether the implementation of a circuit design is functionally equivalent to an earlier version described at the same level of abstraction, it can show the correctness of a circuit design. A new circuit verification method based on cone-oriented circuit partitioning and decision diagrams is presented in this paper. First of all, the structure level of every signal line in a circuit is computed. Secondly, the circuit is partitioned into a lot of cone structures. The multiple-valued decision diagram corresponding to every cone structure is generated. The

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Duncan, Philip N., Siavash Ahrar, and Elliot E. Hui. "Scaling of pneumatic digital logic circuits." Lab on a Chip 15, no. 5 (2015): 1360–65. http://dx.doi.org/10.1039/c4lc01048e.

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We present strategies for scaling pneumatic logic circuits to smaller dimensions. Our process achieves order-of-magnitude increases in both circuit density and speed, enabling the construction of a 12-bit counter.

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Rajeswaran, N., T. Madhu, and M. Suryakalavathi. "Hardware Testable Design of Genetic Algorithm for VLSI Circuits." Applied Mechanics and Materials 367 (August 2013): 245–49. http://dx.doi.org/10.4028/www.scientific.net/amm.367.245.

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Accurate and fast testing of digital circuits is very much essential in real time applications. Hardware analysis of digital circuits, which is otherwise very tedious and time consuming, is attempted using the artificial intelligence technique: Genetic Algorithms (GA). GA is used to find an input sequence to a digital circuit for testing, as it reduces the hardware utilization, complexity and computational time of the circuits. All the GA processes are simulated and implemented by using Xilinx 10.1 and SPARTAN 3E.

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Wang, Zicheng, Zijie Cai, Zhonghua Sun, Jian Ai, Yanfeng Wang, and Guangzhao Cui. "Research of Molecule Logic Circuit Based on DNA Strand Displacement Reaction." Journal of Computational and Theoretical Nanoscience 13, no. 10 (2016): 7684–91. http://dx.doi.org/10.1166/jctn.2016.5194.

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Because of its outstanding advantages, DNA strand displacement (DSD) reaction has been widely used for signals processing and molecular logic circuit constructing. Two digital logic circuits are constructed in this paper. One is the encoder circuit with four inputs and two outputs, and the other is the decoder circuit with two inputs and four outputs. Of particular interest to us is the multicolor fluorescent gold nanoprobe detection part, where a gold nanoparticle is modified with multicolor fluorophores which exploits the ultrahigh quenching ability of gold nanoparticles (AuNPs). Finally, th

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Lin, Shan, Tao Lin, and Zhan Wen Liu. "A Discussion of the Design Method of Full Adder Circuit." Applied Mechanics and Materials 135-136 (October 2011): 15–20. http://dx.doi.org/10.4028/www.scientific.net/amm.135-136.15.

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A bit full adder is a very important component in the digital system. Design of a full-adder circuit, as an example, by changing its output function expression in the form of expression, use the gates, decoder, multiplexer etc 74 series devices, the eight circuits realization form are given respectively, and briefly analyzed the advantages and disadvantages of the various circuit implementation. The example show that the design of combinational logic circuits has mobility and variety, it could give the instructiveness and the guiding for other design of combinational logic circuits.

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Chen, Ling, and Zhong Liang Pan. "Fault Detection of Bridging Faults in Digital Circuits by Shared Binary Decision Diagram." Key Engineering Materials 439-440 (June 2010): 1235–40. http://dx.doi.org/10.4028/www.scientific.net/kem.439-440.1235.

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A new test generation method for the bridging faults in digital circuits is proposed in this paper, the method is based on shared binary decision diagram. The shared binary decision diagram can represent many logic functions simultaneously by sharing isomorphic subgraphs, it is used to represent the digital circuits with multiple primary outputs. The binary decision diagram is constructed respectively for the normal circuit and faulty circuit having a bridging fault. The test vectors of the bridging fault can be produced by a XOR operation of the two binary decision diagrams. The experimental

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Y. N., Sharath Kumar, and Dinesha P. "TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 3 (2021): 2704. http://dx.doi.org/10.11591/ijece.v11i3.pp2704-2710.

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Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the

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Aaron D’costa, Mr, Dr Abdul Razak, and Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters." International Journal of Engineering & Technology 7, no. 3 (2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.

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Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so

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Gao, Hua Qiang, Yu Jing Wang, Shou Qiang Kang, Zhang Le, Jian Qing Wang, and Jing Jing Wei. "Realization of Digital Chaotic Signal Generation Circuits." Applied Mechanics and Materials 716-717 (December 2014): 1352–55. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1352.

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To overcome the shortcomings of realizing chaotic system by analog circuits, digital chaotic signal generation circuits based on DSP are designed. Computer simulation of chaotic system is performed firstly, and the discrete equations are obtained using discretization algorithm. On this basis, the design of hardware circuits based on DSP is made, and the corresponding C programs are constructed. Through the debugging of software and hardware, digital design of chaotic system based on DSP is achieved, and chaotic attractor is observed through an oscilloscope by digital-to-analog conversion circu

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Jóźwiak, Lech. "General Decomposition and Its Use in Digital Circuit Synthesis." VLSI Design 3, no. 3-4 (1995): 225–48. http://dx.doi.org/10.1155/1995/16259.

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Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide diversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized that advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this paper, we present the fundamentals of a logic design methodology which meets the requirements of today's complex circuits and modem building blocks. The methodology is based on the theory of general full-decompositions which consti

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Li, Hongtao, Chunbiao Li, Zeshi Yuan, Wen Hu, and Xiaochen Zhen. "A New Class of Chaotic Circuit with Logic Elements." Journal of Circuits, Systems and Computers 24, no. 09 (2015): 1550136. http://dx.doi.org/10.1142/s0218126615501364.

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When signum operation is applied in chaotic systems to realize piecewise-linearity, the original nonlinearity turns to be a kind of Boolean calculation, and correspondingly the chaotic circuit can be implemented by an analog structure embedded with some logic-gate circuits. In this paper, as examples based on the diffusionless Lorenz system we proposed a couple of chaotic flows with signum piecewise-linearity, which experimentally resorts to digital gate circuits. The experimental chaotic circuit with logic elements was built, and the oscillation in the physical circuit agrees well with the nu

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Shukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (2015): 213. http://dx.doi.org/10.11591/ijres.v4.i3.pp213-218.

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Shifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsi

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Barkalov, Oleksandr O., Larisa O. Titarenko, Oleksandr M. Golovin, and Oleksandr V. Matvienko. "Optimization of a Composition Microprogram Control Unit with Elementary Circuits." Control Systems and Computers, no. 2-3 (292-293) (July 2021): 40–51. http://dx.doi.org/10.15407/csc.2021.02.040.

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Introduction. The control unit coordinating interaction of all other blocks of a digital system is one of the central blocks and is a sequential circuit. As a rule, when synthesizing control unit circuits, the problem arises of reducing hardware costs. Methods for solving this problem depend on features of both the architecture of the control unit and the elemental basis. Purpose. The main goal of this work is to reduce hardware costs and power consumption of control units of digital systems by taking into account features of the element base of the control unit and rational organization of ad

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Li, Shuo, Nan Pan, Sen Gao, and Lei Li. "Three State Output Module and Digital Switch Circuit Based on Threshold Memristor." Journal of Physics: Conference Series 2395, no. 1 (2022): 012021. http://dx.doi.org/10.1088/1742-6596/2395/1/012021.

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Abstract A memristor is a new electronic device with small volumes and small fluctuations. As a two-terminal device, it is mainly characterized by non-volatility and nanoscale characteristic size. Memristors can also calculate and store at the same time, which has a broad application prospect in logic circuits. Traditional integrated circuit technology has been very mature. And CMOS technology has almost reached the limit of physical size. Compared with traditional circuit components, memristor devices are compatible with CMOS circuits with their fast computing speed, low power consumption, an

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Chen, Jinjie. "A Simulation Research on the Grid-Connected Control Technology of Single-Phase Inverters Based on MATLAB." Journal of Electronic Research and Application 6, no. 4 (2022): 7–12. http://dx.doi.org/10.26689/jera.v6i4.4154.

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This paper primarily discusses the main circuit of single-phase inverter circuits. It begins by introducing the research context and the significance of the subject, then discusses the topology of grid-connected single-phase inverter circuits, continues by discussing the control strategy for grid-connected single-phase inverter circuits, realizes a sinusoidal pulse width modulation (SPWM) signal generation circuit and an inverse control algorithm program, and finally ensures good output waveform and fast dynamic response. In view of the hysteresis feature of the grid voltage’s synchronous sign

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Oyebola, Blessed Olalekan, and E. Eze Blessing. "Simulation and Implementation of Microcontroller Based Printed Circuit Board Ready Circuits for Technical Training and Demonstration." Asian Journal of Engineering and Applied Technology 7, no. 1 (2018): 29–36. http://dx.doi.org/10.51983/ajeat-2018.7.1.981.

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The paper presents designed and constructed microcontroller based PCB ready on five automation circuits as an attempt to aid technical education on microcontroller circuits’ simulation in Computer Engineering Technology. The designs were of three stages that include circuit design and simulation by using Proteus software, printed circuit board (PCB) production using manual techniques and construction of five selected circuits (Seven Segment to Display Number 0-9, seven Segment Counter to Count 0-99, Matrix Led to Display A-Z, Digital Thermometer and Motion Sensor to Switch 10 Points of Loads)

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