Dissertations / Theses on the topic 'Circuits intégrés à grande échelle'
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Portal, Jean-Michel. "Test des circuits configurables de type FPGA à base de SRAM." Montpellier 2, 1999. http://www.theses.fr/1999MON20055.
Full textFagot, Christophe. "Méthodes et algorithmes pour le test intégré de circuits VLSI combinatoires." Montpellier 2, 2000. http://www.theses.fr/2000MON20003.
Full textPham, Jean-Marie. "Caractérisation électrique des structures bipolaires VLSI : évaluation de paramètres critiques." Bordeaux 1, 1991. http://www.theses.fr/1991BOR10554.
Full textSaez, José Antonio. "Contribution à l'étude des circuits VLSI bipolaires : caractérisation et évaluation des technologies de type ECL : recherche d'optimisation des opérateurs CML." Bordeaux 1, 1990. http://www.theses.fr/1990BOR10580.
Full textLopez, Alain. "Réduction de Grosstalk, fenêtre inductive et modèles équivalents de lignes de transmission couplées." Montpellier 2, 2004. http://www.theses.fr/2004MON20112.
Full textDupuy, Gilles. "Application des cristaux liquides à l'analyse de fonctionnalité et de défaillance des composants électroniques." Bordeaux 1, 1985. http://www.theses.fr/1985BOR10616.
Full textTrauchessec, Joe͏̈l. "Contribution à la synthèse topologique de circuits intégrés CMOS." Montpellier 2, 1991. http://www.theses.fr/1991MON20132.
Full textVirazel, Arnaud. "Test intégré des circuits digitaux : analyse et génération de séquences aléatoires adjacentes." Montpellier 2, 2001. http://www.theses.fr/2001MON20094.
Full textGuiller, Loïs. "Réduction de la consommation durant le test des circuits VLSI." Montpellier 2, 2000. http://www.theses.fr/2000MON20108.
Full textKenmei, Nganguem II Louis Bertrand. "Mise en oeuvre d'une méthode d'éléments finis à éléments d'arêtes en deux et trois dimensions : applications aux lignes de topologies complexes pour circuits intégrés monolithiques micro-ondes et aux interconnexions sur circuit silicium." Lille 1, 1999. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/1999/50376-1999-215.pdf.
Full textCathébras, Guy. "Contribution à la compilation structurelle des circuits intégrés cmos." Montpellier 2, 1990. http://www.theses.fr/1990MON20034.
Full textIhs, Hassan. "Test intégré autonome des circuits analogiques et mixtes." Montpellier 2, 1997. http://www.theses.fr/1997MON20213.
Full textAntri-Bouzar, Riad. "Du cablâge à la micro-programmation : le micro-programme câblé." Toulouse, INPT, 1998. http://www.theses.fr/1998INPT019H.
Full textLemonnier, Pascal. "Étude d'une architecture VLSI pour un algorithme d'estimation de mouvement bloc-récursif." Rennes 1, 1996. http://www.theses.fr/1996REN10061.
Full textPatard, Olivier. "Etude des reprises d'épitaxie MOVPE pour intégration sur InP de circuits photoniques à guides enterrés." Rennes, INSA, 2012. http://www.theses.fr/2012ISAR0010.
Full textThe need for reduction of the cost and the size of the equipments for optical telecommunication systems while increasing data rates has lead to the integration of the photonic functions located in a transceiver or a receiver. The buried waveguide ridge structure with semi-insulating InP (SIBH) can simplify and improve the planarization of the buried waveguide. The InP growth doped with Ruthenium as an alternative dopant of iron is studied depending on the growth parameters. A perfect stability of the dopant without any interdiffusion with zinc is shown and resistivities higher than 108 Ω. Cm are obtained. These good results of the material lead to its integration in a reflective amplified modulator which showed high performances reaching bitrates of 40Gb/s over a large spectral range and temperature going to 85°C
Léger, Crémoux Séverine. "Evaluation et optimisation de chemins combinatoires de circuits VLSI." Montpellier 2, 1998. http://www.theses.fr/1998MON20129.
Full textDiguet, Jean-Philippe. "Estimation de complexité et transformations d'algorithmes de traitement du signal pour la conception de circuits VLSI." Rennes 1, 1996. http://www.theses.fr/1996REN10118.
Full textKerouedan, Sylvie. "Conception et réalisation de circuits VLSI-CLF pour le traitement de l'information optique." Brest, 1998. http://www.theses.fr/1998BRES2012.
Full textBaumann, Christophe. "Etude expérimentale de l'électrohydrodynamique des cristaux liquides : applications à la visualisation du fonctionnement des circuits intégrés complexes." Bordeaux 1, 1986. http://www.theses.fr/1986BOR10602.
Full textChevalier, Cyril. "Contribution au test intégré : générateurs de vecteurs de test mixtes déterministes et pseudo-aléatoires." Montpellier 2, 1994. http://www.theses.fr/1994MON20141.
Full textGourram, Saïd. "Réseau multi-niveaux : nouvel outil de modélisation des ordinateurs : Définition et implémentation." Lille 1, 1985. http://www.theses.fr/1985LIL10071.
Full textChehade, Fahed. "Etude et modélisation de l'injection de porteurs énergétiques dans l'isolant des structures MIS." Ecully, Ecole centrale de Lyon, 1988. http://www.theses.fr/1988ECDL0006.
Full textLubowiecki, Véronique. "Développement d'une filière technologique CMOS à grille tungstène." Lyon, INSA, 1988. http://www.theses.fr/1988ISAL0035.
Full textAssous, Myriam. "Caractérisation de transistors bipolaires à hétérojonctions Si/SiGe intégrés : corrélation à la technologie et éléments de modélisation." Lyon, INSA, 1999. http://www.theses.fr/1999ISAL0018.
Full textMy thesis is concerned with is Si/ SiGe hetero-junction bipolar transistors (SiGe HBT) behavior, related to the SiGe base epitaxy. These specific phenomena leading to non standard operation compared to Si BJTs are underscored. We focused on the study of base-collector junction leakage current and of neutral base recombination. Correlation of electrical results to the fabrication process contributed to the improvement of pre-epitaxial surface preparation and of strained SiGe layer quality. From the electrical characterization of neutral base recombination, we deduced a method for extracting the apparent electron lifetime in the base. The basic equations needed to include neutral base recombination in compact models of the SiGe HBT (suitable for circuit simulation) were established. •finally, based on our measurements it was demonstrated that improved performance could be obtained at circuit level although the HBTs used in this study had their performance limited by integration constraints
Angui, Ettiboua. "Conception d'un circuit intégré VLSI turbo-décodeur." Brest, 1994. http://www.theses.fr/1994BRES2005.
Full textDure, Daniel. "Simulation multi-mode de circuits VLSI." Paris 11, 1989. http://www.theses.fr/1989PA112025.
Full textWhereas design of VLSI circuits has been sped up by a new crop of synthetisis tools, simulation still constitutes a bottleneck in this process. In this paper, we review existing simulation methods and some improvements of our own. We also advocate for better integration of simulation within the design system, and we present new techniques to this end. To be more precise, a systematic study of simulation usages highlights potential problems during simulation and data exchange. This leads to a new organization of the design system, supported by an event driven communication protocol. The kernel of an event driven simulator is detailed, along with a general purpose model for logic simulation, which enables simulation speed of 50000 events per second per MIPS, on sequential computers. This level of performance has been reached through the usage of new simulatable data structures and currying of device evaluation functions. This method also uses a continuous charge delay model, which handles spikes more accurately than classical one pass delay models. Other methods tailored for the simulation of higher and lower level devices are also presented, and practical problems encountered during development of multi-mode simulators are listed and addressed through an object oriented methodology supported by a new simulation and software environment
Ferrigno, Julie. "Caractérisation de circuits intégrés par émission de lumière statique et dynamique." Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13719/document.
Full textVLSI (”Very Large Scale Integration”) et ULSI (”Ultra Large Scale Integration”) take the most important place in semi-conductor domain. Their complexi?cation is growing and is due to the bigger and bigger request from the manufacturers such as automotive domain or space application. However, this complexicity generates a lot of defects inside the components. We need to predict or to detect and analyze these defects in order to stop these phenomena. Lot of failure analyzis techniques were developped inside the laboratories and are still used. Nevertheless, we developped a new approach for failure analysis process : the faults simulation for CMOS integrated circuits. This particular kind of approach allows us to reach the analysis in more e?ective and easier way than usual. But the simulations play a predictive role for structures of MOS transistors
Flottes, Marie-Lise. "Contribution au test déterministe des circuits cmos : équivalences de pannes." Montpellier 2, 1990. http://www.theses.fr/1990MON20060.
Full textHadji, Mohamed. "Contributions à l'étude d'un processeur s'intégrant dans un réseau systolique linéaire dédié à la comparaison des séquences biologiques." Rennes 1, 1995. http://www.theses.fr/1995REN10044.
Full textHornik, Armand. "Contribution à la définition et à la mise en oeuvre de NAUTILE." Grenoble INPG, 1989. http://tel.archives-ouvertes.fr/tel-00333065.
Full textBelgnaoui, Ibrahim. "Contribution au développement d'une méthode de conception optimisée d'opérateurs logiques VLSI : application à la technologie STL." Bordeaux 1, 1990. http://www.theses.fr/1990BOR10535.
Full textAkrout, Nabil. "Contribution à la compression d'images par quantification vectorielle : algorithmes et circuit intégré spécifique." Lyon, INSA, 1995. http://www.theses.fr/1995ISAL0017.
Full textRecently, Vector Quantization (VQ) has received considerable attention and become an effective tool for image compression. It provides High compression ratio and simple decoding process. However, studies on practical implementation of VQ have revealed some major difficulties such as edge integrity and code book design efficiency. After doing the state-of-the-art in the field of Vector Quantization, we focus on: - Iterative and non-iterative code book generation algorithms. The main idea of non-iterative algorithms consists of creating progressively the code words, during only one scanning of the training set. At the beginning, the code book is initialized by the first vector found in the training set, then each input vector is mapped into the nearest neighbor codeword, which minimizes the distortion error. This error is then compared with per-defined thresholds. The performance of iterative and non-iterative code book generation algorithms are compared: the code books generated by non-iterative algorithms require less than 2 percent of the time required by iterative algorithms. - To propose a new procedure for image compression as an improvement on vector quantization of sub-bands. Codewords having vertical and horizontal shape will be used to vector quantize the high-frequency sub-images, obtained from a multiresolution analysis scheme. The codewords shapes take into account the orientation and resolution of each subband details in order to -preserve edges at low bit rates. Their sizes are defined according to the correlation distances in each subband for the horizontal and vertical directions. - The intensive computational demands of vector quantization (V. Q. ) for important applications in speech and image compression have motivated the need for dedicated processors with very high throughput capabilities. Bit-serial systolic architectures offer one of the most promising approaches for fulfilling the demanding V. Q. Speed requirements in many applications. We propose a novel family of architectural techniques which offer efficient computation of Manhattan distance measures for nearest neighbor code book searching. Manhattan distance requires much less computation and VLSI chip area, because there is no multiplier. Compared to Euclidean distance. This gave rise to the idea of implementing Manhattan distance directly in hardware for real-time image coding. Very high V. Q. Throughput can be achieved by a massive parallelism. Therefore, it requires an important VLSI chip area. To avoid this difficulty, we carry out a "bit-serial" pipelined processing for nearest neighbor code book searching. This architecture is more suitable for real-time coding. Several alternative configurations allow reasonable tradeoffs between speed and VLSI chip area required
Vanier, Eric. "Caractérisation et optimisation temporelles des interconnexions dans les circuits sub-microniques CMOS." Montpellier 2, 1998. http://www.theses.fr/1998MON20126.
Full textAmmari, Abdelaziz. "Analyse de sûreté des circuits complexes décrits en langage de haut niveau." Grenoble INPG, 2006. https://tel.archives-ouvertes.fr/tel-00101622.
Full textThe probability of transient faults increases with the evolution of the technologies. Several approaches have been proposed to early analyze the impact of these faults in a digital circuit. It is in particular possible to use an approach based on the injection of faults in a RT-Level VHDL description. In this thesis, we make several contributions to this type of analysis. A first considered aspect is to take into account the digital circuit's environment during the injection campaigns. So, an approach based on multi-level dependability analysis has been developed and applied to an example. The injections are performed in the digital circuit described at the RT-Level while the rest of the system is described at a higher level of abstraction. The results' analysis shows that failures appearing at circuit's level have in fact no impact on the system. We then present the advantages of the combination of two types of analyses : classification of faults with respect to their effects, and a more detailed analysis of error configurations activated in the circuit. An injection campaign of SEU-like faults was performed on a 8051 microcontroller described at RT-Level. The results show that the combination of the two type analyses allows a designer to localize the critical points, facilitating the hardening stage. They also show that, in the case of a general processor, the error configurations can be dependent on the executed program. This study also demonstrates that injecting a very small percentage of the possible faults gives useful information to the designer. The same methodology has been used to validate the robustness obtained with a software hardening. The results show that some faults are not detected by the implemented mechanisms although those were previously validated by fault injections based on an instruction set simulator. The last aspect of this thesis concerns the fault injection in analog blocks. In fact very few works cover this subject. We thus propose a global analysis flow for digital, analog or mixed circuits, described at behavioral level. The possibility to inject faults in analog blocks is discussed. The results obtained on a PLL, chosen as case study, have been analysed and show the feasibility of fault injections in analog blocks. To validate this flow, fault injections were also performed at transistor level and compared to those performed at high level. It appears a good correlation between the results obtained at the two levels
Baschiera, Daniel. "Modélisation de pannes et méthodes de test de circuits intégrés CMOS." Phd thesis, Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00320020.
Full textServel, Grégory. "Effets parasites dus aux interconnexions." Montpellier 2, 2001. http://www.theses.fr/2001MON20037.
Full textDescamps, Gilles-Eric. "Méthode de distribution hiérarchique d'outils de vérification de circuits intégrés VLSI sur un réseau de stations de travail : application à un vérificateur de règles de dessin." Paris 6, 1996. http://www.theses.fr/1996PA066808.
Full textTomas, Jean. "Caractérisation par simulation de la métastabilité des circuits séquentiels : application à des structures VLSI." Bordeaux 1, 1988. http://www.theses.fr/1988BOR10580.
Full textKarabernou, Si Mahmoud. "Conception et réalisation d'un processeur pour une architecture cellulaire massivement parallèle intégrée." Grenoble INPG, 1993. http://tel.archives-ouvertes.fr/tel-00343216.
Full textCourbis, Anne-Lise. "Contribution à l'étude et au développement d'un générateur de séquences de test comportemental." Montpellier 2, 1991. http://www.theses.fr/1991MON20274.
Full textGryba, Tadeusz. "Calcul des circuits électroniques VLSI avec optimisation des tolérances." Lille 1, 1985. http://www.theses.fr/1985LIL10081.
Full textDeyine, Amjad. "Contribution au développement de techniques de stimulation laser dynamique pour la localisation de défauts dans les circuits VLSI." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14252/document.
Full textThe principal objective of the project is to investigate laser based techniques for failure analysis of VLSI integrated circuits. The investigations will be performed on the DCGSystems’ Meridian laser scanning microscope coupled with the Credence’s Diamond D10 tester available at CNES. This study was interested more specifically in the improvement of dynamic laser stimulation techniques said DLS like Dynamic Laser Stimulation. DLS techniques consists in modifying the operation of a dynamically failing integrated circuit by photoelectric effect or photothermal effect using a continuous laser beam sweeping the surface of the circuit. A laser beam modulated in the nanosecond range synchronously with the electrical test through a TTL signal can also be advantageously used. Analysis of the electrical parameters response to the laser disturbance leads to an identification of the dynamic failure origin. The optimization of current DLS techniques will increase the failure analyses success rate and bring information hardly accessible by other means, which allows determining the failure root cause. The work performed was the improvement of the DLS process flow by closely integrating the test to monitor any relevant electrical parameters upon DLS. The « Pass-Fail Mapping » technique and the parametric techniques were implemented on the test tools combining the D10 and the Meridian. The synchronization of the test with the laser scan allows establishing methodologies and techniques in order to add timing information to the defect localisation. Indeed, by modulating the laser beam depending on the test pattern sequences, we show our capability to identify precisely which are the vectors responsible for the IC defective behaviour. We are able now to correlate the defective IC functions with the IC structures involved. This technique is known as F-DLS for Full Dynamic Laser Stimulation.In some cases, we know when the failure occurs in the test pattern but we ignore which IC structures are involved. So, we also developed a dynamic current measurement under laser stimulation technique. This technique proved to be efficient to obtain information about the internal IC behaviour. As an example, for the latched component which signals are synchronised just before the outputs, it is hard to measure shift in the signal propagation. Nevertheless, the IC internal activities can be characterized by monitoring on a scope the current variations under laser stimulation when the IC is activated. The information about the shift in the signal propagation could be extracted then by observing of the IC internal activities.Finally, these DLS techniques proved their efficiency for device qualification for reliability issues. Their accuracy allows early detection of operational parameter tiny variations. This is used to highlight electrical parameter margin evolutions during accelerated aging process. DLS techniques demonstrate their potential to deal with the IC robustness evolution facing external perturbation for reliability purposes.The techniques and methodologies developed during this work have been successfully integrated in the IC analysis and characterisation process in the laboratory. We exposed these techniques but the main case studies remain confidential
Gasser, Jean-Luc. "Analyse de signature des circuits intégrés complexes par test aléatoire utilisant les méthodes de traitement du signal : application à un microprocesseur." Toulouse, INPT, 1986. http://www.theses.fr/1986INPT079H.
Full textOugouag, Omar. "Étude et réalisation d'un contrôleur, temps réel, des procédés de gravure de circuits intégrés à haute intégration." Paris 11, 1985. http://www.theses.fr/1985PA112119.
Full textFrydman, Claudia. "DeBuMA : système pour la description : la construction et l'exécution d'applications en CAO." Montpellier 2, 1990. http://www.theses.fr/1990MON20293.
Full textPélissier, Jean-Luc. "Automatisation d'une station de test par faisceau d'électrons : localisation dynamique de fautes." Montpellier 2, 1987. http://www.theses.fr/1987MON20269.
Full textKoester, Cécile. "Étude de l'intégration de PEARLS : processeur expérimental d'aide à la recherche dans les langages symboliques." Paris 11, 1988. http://www.theses.fr/1988PA112277.
Full textThis dissertation deals with micro-architecture, design and layout of a VLSI processor well suited for symbolic processing languages. We first present the specific features of PEARLS which are improvements both on the environment system and the processor. Then, the timing required for the execution of the instructions is identified and we study the fundamental timing dependencies as implied by the instruction set and the pipeline scheme. According to that chosen pipeline scheme and the instruction set requirement, the data-path is designed. Two critical points of the data-path, the register file and the arithmetic and logic unit are examined. Next, we had to create a CAD tool, in order to easy the layout of complex processors. This tool, a silicon assembler for CMOS parametrable cells, leads to a short design time, thus allowing quick exploitation of new technologies. Finally, after laying out the test chips, the performance of PEARLS are evaluated
Bakowski, Przemyslaw. "Contribution à la conception de l'architecture matérielle des ordinateurs : projet LIDO, préprocesseur pour la compilation en silicium." Lille 1, 1986. http://www.theses.fr/1986LIL10122.
Full textLombaert, Isabelle. "Elaboration et caractérisation des siliciures utilisés comme matériaux de grille ou d'interconnexion dans les circuits VLSI." Bordeaux 1, 1988. http://www.theses.fr/1988BOR10572.
Full textConard, Didier. "Traitement d'images en analyse de défaillances de circuits intégrés par faisceau d'électrons." Grenoble INPG, 1991. http://tel.archives-ouvertes.fr/tel-00339510.
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