Academic literature on the topic 'CISC microprocessors'

Performance of the decoder unit is critical for CISC microprocessors. To take x86 ISA for an example, we analyzes the x86 instruction formats in detail. We compare two decoding strategies used in Longteng C1&C2 microprocessors: One is a simply direct serial decoder; another is a massively parallel decoder. Simulation results show speedups around 2.2~3.6 are obtained by using 10 parallel sub-decoders.

Nowadays, heat dissipation for electronic chips, microprocessors in electrical and electronic equipment, especially in Site Router telecommunication equipment when operating at high intensity is an urgent process to increase life expectancy, productivity and performance. Many telecom providers such as Huawei, Ericsson, Cisco etc have offered solutions for liquid cooling, cold air, heat pipes. However, the complexity, the cost and the effect are not high. Furthermore, there is shortage in optimal parameters of design and operation [1-5]. Derived from the above fact, the author has calculated and modeled a Site Router equipment using extruded blast heat exchanger with a large heat exchanger structure which withstands pressure when falling, combining airflow from fans to speed up the dissipation of heat. In this paper, the author presents the optimal calculation and control process of the size of the heat sink and the contact plate under the influence of actual operation conditions at the specified velocity of the air flow from which the model is built directly to determine the number and the size of the heat sink’s plate fins.

Chronic electrical vagal nerve stimulation (VNS) has emerged as a new tool to treat human diseases including obesity. Indeed, chronic VNS has been shown to cause weight loss in humans and in experimental animal models. However, the mechanisms for VNS-induced weight loss are largely unknown. We hypothesized that an increase in metabolic rate together with reduced caloric intake and reduced feeding efficiency (body weight gain per calories consumed) contribute to chronic VNS-induced weight loss or reduced weight gain. To test this hypothesis, we developed a miniaturized microprocessor-operated nerve stimulator for chronic use in conscious mice. Effectiveness of the stimulator was verified by bradycardia at stimulation frequencies above 5 Hz (3V, 1mA, 1ms pulses). Male C57Bl/6 mice (16 weeks old, standard mouse chow diet) were instrumented with nerve stimulators (3V, 1mA, 1ms pulses at 5 Hz) on the right cervical vagal nerve and body weight, food intake and metabolic rate (indirect calorimetry) were determined at baseline and weekly thereafter. After the initial post-surgical weight loss, sham animals (n=9, stimulators off) regained pre-surgical body weight within 16 days (100.0±2.7%). In contrast, mice with chronic VNS (n=12) never reestablished pre-surgical body weight (94.5±0.9% on day 16, P<0.05 vs. sham). Caloric intake was significantly reduced in mice with chronic VNS compared to sham animals (74.7±2.4 vs. 84.6±4.2 kcal/week, P<0.05). Likewise, mice with chronic VNS showed significantly reduced feeding efficiency compared to sham mice (2.6±2.0 vs. 10.6±2.4 mg body weight gain per kcal consumed). Oxygen consumption tended to be elevated (2734±152 vs. 2490±124 mL/kg/h, P=0.23) during the first week, but not thereafter. In conclusion reduced food intake and lower feeding efficiency contribute to reduced weight gain in mice with chronic VNS. We speculate that an initial increase in metabolic rate (assessed by oxygen consumption) may be antagonized by compensatory mechanisms in response to chronic VNS.

The soft error rates per single-bit due to alpha particles in sub-micron technology is expectedly reducedas the feature size is shrinking. On the other hand, the complexity and density of integrated systems are accelerating which demand ecient soft error protection mechanisms, especially for on-chip communication. Using soft error protection method has to satisfy tight requirements for the area and energy consumption, therefore a low complexity and low redundancy coding method is necessary. In this work, we propose a method to enhance Parity Product Code (PPC) and provide adaptation methods for this code. First, PPC is improved as forward error correcting using transposable retransmissions. Then, to adapt with dierent error rates, an augmented algorithm for configuring PPC is introduced. The evaluation results show that the proposed mechanism has coding rates similar to Parity check’s and outperforms the original PPC.Keywords Error Correction Code, Fault-Tolerance, Network-on-Chip. References [1] R. Baumann, Radiation-induced soft errors in advanced semiconductor technologies, IEEETransactions on Device and materials reliability. 5-3 (2005) 305–316. https://doi.org/10.1109/tdmr.2005.853449.[2] N. Seifert, B. Gill, K. Foley, P. Relangi, Multi-cell upset probabilities of 45nm high-k + metal gateSRAM devices in terrestrial and space environments, in: IEEE International Reliability Physics Symposium 2008, IEEE, AZ, USA, 2008, pp. 181–186.[3] S. Lee, I. Kim, S. Ha, C.-s. Yu, J. Noh, S. Pae, J. Park, Radiation-induced soft error rate analyses for 14 nmFinFET SRAM devices, in: 2015 IEEE International Reliability Physics Symposium (IRPS), IEEE, CA, USA, 2015, pp. 4B–1.[4] R. Hamming, Error detecting and error correcting codes, Bell Labs Tech. J. 29-2 (1950) 147–160. https://www.doi.org/10.1002/j.1538-7305.1950.tb00463.x.[5] M. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBMJ. Res. Dev. 14-4 (1970) 395–401. https://www.doi.org/10.1147/rd.144.0395.[6] S. Mittal, M. Inukonda, A survey of techniques for improving error-resilience of dram, Journal ofSystems Architecture. 91-1 (2018) 11–40. https://www.doi.org/10.1016/j.sysarc.2018.09.004.[7] D. Bertozzi, et al., Error control schemes for on-chip communication links: the energy-reliabilitytradeo, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24-6 (2005) 818–831. https://doi.org/10.1109/tcad.2005. 847907.[8] F. Chiaraluce, R. Garello, Extended Hamming product codes analytical performance evaluation for low errorrate applications, IEEE Transactions on Wireless Communications. 3-6 (2004) 2353–2361. https://doi. org/10.1109/twc.2004.837405.[9] R. Pyndiah, Near-optimum decoding of product codes: Block turbo codes, IEEE Transactions onCommunications. 46-8 (1998) 1003–1010. https://www.doi.org/10.1109/26.705396.[10] N. Magen, A. Kolodny, U. Weiser, N. Shamir, Interconnect-power dissipation in a microprocessor,in: Proceedings of the 2004 international workshop on System level interconnect prediction, ACM, Paris,France, 2004, pp. 7–13.[11] K. Dang, X. Tran, Parity-based ECC and Mechanism for Detecting and Correcting Soft Errors in On-ChipCommunication, in: Proceeding of 2018 IEEE 11th International Symposium on EmbeddedMulticore/Many-core Systems-on-Chip, IEEE, Hanoi, Vietnam, 2018, pp. 1–6.[12] L. Saiz-Adalid, et al., MCU tolerance in SRAMs through low-redundancy triple adjacent error correction, IEEE Transactions on VLSI Systems. 23-10 (2015) 2332–2336. https://www.doi.org/10.1109/tvlsi.2014.2357476.[13] W. Peterson, D. Brown, Cyclic codes for error detection, Proceedings of the IRE 49-1 (1961)228–235. https://www.doi.org/10.1109/jrproc.1961.287814.[14] S. Wicker, V. Bhargava, Reed-Solomon Codes and Their Applications, first ed., JohnWiley and Sons, NJ,USA, 1999.[15] I. Reed, X. Chen, Error-control coding for data networks, first ed., Springer Science and BusinessMedia, New York, 2012.[16] L. Peterson, B. Davie, Computer networks: a systems approach, fifth ed., Elsevier, New York, 2011.[17] K. Dang, et al., Soft-error resilient 3D Network-on-Chip router, in: 2015 IEEE 7thInternational Conference on Awareness Science and Technology (iCAST), China, 2015, pp. 84–90.[18] K. Dang, et al., A low-overhead soft–hard fault-tolerant architecture, design and managementscheme for reliable high-performance many-core 3D-NoC systems, The Journal of Supercomputing.73-6 (2017) 2705–2729. https://www.doi.org/10.1007/s11227-016-1951-0.[19] D. Ernst, et al., Razor: A low-power pipeline based on circuit-level timing speculation, in: The36th annual IEEE/ACM International Symposium on Microarchitecture, IEEE, CA, USA, 2003, pp. 10–20.[20] H. Mohammed, W. Flayyih, F. Rokhani, Tolerating permanent faults in the input port of the network onchip router, Journal of Low Power Electronics and Applications. 9-1 (2019) 1–11. https://www.doi.org/10.3390/jlpea9010011.[21] G. Hubert, L. Artola, D. Regis, Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFETtechnologies due to atmospheric radiation, Integration, the VLSI journal. 50 (2015) 39–47. https://www.doi.org/10.1016/j.vlsi.2015.01.003.[22] J.-s. Seo, et al., A 45nm cmos neuromorphic chip with a scalable architecture for learning in networks of spiking neurons, in: 2011 IEEE Custom Integrated Circuits Conference (CICC), IEEE, CA, USA, 2011, pp. 1–4.[23] NanGate Inc., Nangate Open Cell Library 45 nm. http://www.nangate.com, (accessed 16.06.16) (2016).

碩士
國立交通大學
資訊工程學系
85
Originally, Intel x86 processor is a scalar CISC processor, i.e. it can finish one x86 instruction per cycle at the most. Due to the inhibitive cost and the limitation of semiconductor process technology and electrical property, we cannot lift up the clock speed of x86 processor unendingly to gain much more performance improvement. It seems straightforward that we can build a 2-way issue superscalar x86 processor just by adding another one integer pipeline to he original scalar x86 architecture. But the inherent characteristics of x86 instruction set constrain the overall improvement.One way to approach the superscalar x86 processor design is to start with a pure microcoded scalar implementation, without hardwired control and special techniques employed in the Intel x86 processor. The goal in this case would be to archive parallel execution of microinstructions in a superscalar pipeline. The advantages of this approach is that it converts complex x86 instructions into sequences of microinstructions that are much easier to deal with.Although we can design a superscalar CISC processor with RISC execution core to improve overall performance. In this design, the other advantage is that we can save a lot of money and time by using existed technique or implementation for RISC processor to build the RISC execution core [7]. But the thing is not so good, we need to adapt the existed RISC design to fit the CISC architecture. We will address theses issues and advise possible solutions.