Dissertations / Theses on the topic 'Class-E switching'

Thesis (Ph. D.)--University of Missouri-Columbia, 2007.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on February 14, 2008) Vita. Includes bibliographical references.

The Class-E topology was presented as a single-switch power amplifier with high efficiency at the optimum condition, where the switch enjoys zero-voltage switching (ZVS) and zero-voltage-derivative switching (ZDS). It is also used in MHz dc-dc converters, and in inverters for wireless power transfer, induction heating, and plasma pulsing. The load current in these applications usually varies over a range. Efficiency of a conventional Class-E design degrades dramatically due to the hard switching beyond the optimum conditions. Keeping ZVS with load change in a Class-E topology is preferred within the load range. Soft switching with load variation is realized by duty cycle modulation with additional transformer, matching network, or resistance compression network. Since two ZVS requirements need to be satisfied in a conventional Class-E design, at least two parameters are tuned under load variation. Thus, changing switching frequency, duty cycle, and component values were used. Impressively, a load-independent Class-E inverter design was presented in 1990 for maintaining ZVS and output voltage under a given load change without tuning any parameters, and it was validated with experimental results recently. The operating principle of this special design (inconsistent with the conventional design) is not elucidated in the published literatures. Load-independency illucidation by a Thevenin Model – A Thevenin model is then established (although Class-E is a nonliear circuit) to explain the load-independency with fixed switching frequency and duty cycle. The input block of a Class-E inverter (Vin, Lin, Cin, and S) behaves as a fixed voltage source vth1 and a fixed capacitive impedance Xth1 in series at switching frequency. When the output block (Lo and Co) is designed to compensate Xth1, the output current phase is always equal to the phase of vth1 with resistive load (satisfies the ZVS requirement of a load-independent design). Thus, soft switching is maintained within load variation. Output voltage is equal to vth1 since Xth1 is canceled, so that the output voltage is constant regardless of output resistance. Load-independency is achieved without adding any components or tuning any parameters. Sequential design and tuning of a load-independent ZVS Class-E inverter with constant voltage based on Thevenin Model - Based on the model, it's found that each circuit parameter is linked to only one of the targeted performance (ZVS, fixed voltage gain, and load range). Thus, the sequential design equations and steps are derived and presented. In each step, the desired performance (e.g. ZVS) now could be used to check and tune component values so that ZVS and fixed voltage gain in the desired load range is guaranteed in the final Class-E inverter, even when component values vary from the expectations. The Thevenin model and the load-independent design is then extended to any duty cycles. A prototype switched at 6.78 MHz with 10-V input, 11.3-V output, and 22.5-W maximum output power was fabricated and tested to validate the theory. Soft switching is maintained with 3% output voltage variation while the output power is reduced tenfold. A load-independent ZVS Class-E inverter with constant current by combining constant voltage design and a trans-susceptance network - A load-independent ZVS Class-E inverter with constant current under load variation is then presented, by combining the presented design (generating a constant voltage) and a trans-susceptance network (transferring the voltage to current). The impact of different types and the positions of the networks are discussed, and LCL network is selected so that both constant current and soft switching are maintained within the load variation. The operation principle, design, and tuning procedures are illustrated. The trade-off between input current ripple, output current amplitude, and the working load range is discussed. The expectations were validated by a design switched at 6.78 MHz with 10-V input, 1.4-A output, and 12.6-W maximum output power. Soft switching is maintained with 16% output current varying over a 10:1 output power range. A "ZVS" Class-E dc-dc converter by adding a diode rectifier bridge and compensate the induced varying capacitance at full-load condition - The load-independent Class-E design is extended to dc-dc converter by adding a diode rectifier bridge followed by the Class-E inverter. The equivalent impedance seen by the inverter consists of a varying capacitance and a varying resistance when the output changes. As illustrated before, ZVS and constant output can only be maintained with resistive load. Since the varying capacitance cannot be compensated for the whole load range, performance with using different compensation is discussed. With the selected full-load compensation, ZVS is achieved at full load condition and slight non-ZVS occurs for the other load conditions. The expectation was validated by a dc-dc converter switched at 6.78 MHz with 11 V input, 12 V output, and 22 W maximum output power. ZVS (including slight non-ZVS) is maintained with 16% output voltage variation over 20:1 output power range. Design of variable Capacitor by connecting two voltage-sensitive capacitors in series and controlling the bias voltage of them - The equivalent varying capacitance in the Class-E dc-dc converter can be compensated in the whole load range only with variable component. The sensitivity of a Class-E power conversion can also be improved by using variable capacitors. Thus, a Voltage Controlled Capacitor (VCC) is presented, based on the intrinsic property of Class II dielectric materials that permittivity changing much with electric field. Its equivalent circuit consists of two identical Class II capacitors in series. By changing the voltage of the common point of the two capacitors (named as control voltage), the two capacitance and the total capacitance are both changed. Its operation principle, measured characteristic, and the SPICE model are illustrated. The capacitance changes from 1 μF to 0.2 μF with a control voltage from 0 V to 25 V, resulting a 440% capacitance range. Since the voltage across the two capacitors (named as output voltage) also affects one of the capacitance when control voltage is applied, the capacitance range drops to only 40% with higher bias in the output voltage. Thus, a Linear Variable Capacitor (LVC) is presented. The equivalent circuit is the same as VCC, while one of the capacitance is designed much higher to mitigate the effect of output voltage. The structure, operational principle, required specifications, design procedures, and component selection were validated by a design example, with 380% maximum capacitance range and less than 20% drop in the designed capacitor voltage range. This work contributes to • Analytical analysis and Thevenin Model in load-independent Class-E power conversion • Variable capacitance with wide range
Doctor of Philosophy
The Class-E topology was presented as a single-switch power amplifier with high efficiency at the optimum condition. Efficiency of a conventional Class-E design degrades with load variation dramatically due to the hard switching beyond the optimum conditions. Since two requirements need to be satisfied for soft switching in a conventional Class-E design, at least two parameters are tuned under load variation. Impressively, a load-independent Class-E inverter design was presented for maintaining Zero-Voltage-Switching (ZVS) and output voltage under a given load change without tuning any parameters, and it was validated with experimental results recently. A Thevenin model is established in this work to explain the realization of load-independency with fixed switching frequency and duty cycle. Based on that, a sequential design and tuning process is presented. A prototype switched at 6.78 MHz with 10-V input, 11.3-V output, and 22.5-W maximum output power was fabricated and tested to validate the theory. Soft switching is maintained with 3% output voltage variation while the output power is reduced tenfold. A load-independent ZVS Class-E inverter with constant current under load variation is then presented, by combining the presented design and a trans-susceptance network. The expectations were validated by a design switched at 6.78 MHz with 10-V input, 1.4-A output, and 12.6-W maximum output power. Soft switching is maintained with 16% output current varying over a 10:1 output power range. The load-independent Class-E design is extended to dc-dc converter by adding a diode rectifier bridge, inducing a varying capacitance. With the selected full-load compensation, ZVS is achieved at full load condition and slight non-ZVS occurs for the other load conditions. The expectation was validated by a dc-dc converter switched at 6.78 MHz with 11 V input, 12 V output, and 22 W maximum output power. ZVS (including slight non-ZVS) is maintained with 16% output voltage variation over 20:1 output power range. The varying capacitance in the Class-E dc-dc converter needs variable component to compensate. Thus, a Voltage Controlled Capacitor (VCC) is presented. The capacitance changes from 1 μF to 0.2 μF with a control voltage from 0 V to 25 V, resulting a 440% capacitance range. The capacitance range drops to only 40% with higher bias in the output voltage. Thus, a Linear Variable Capacitor (LVC) is presented, with 380% maximum capacitance range and less than 20% drop in the designed capacitor voltage range.

Thesis (M.S.)--University of Missouri-Columbia, 2008.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on August 14, 2009) Includes bibliographical references.

While a lot of time and resources have been placed into transceiver design, due to the pace of a conventional engineering design process, the design of a power amplifier is often completed using scattered resources; and not always in a methodological manner, and frequently even by an iterative trial and error process. In this thesis, a research question is posed which enables for the investigation of the possibility of streamlining the design flow for power amplifiers. After thorough theoretical investigation of existing power amplifier design methods and modelling, inductors inevitably used in power amplifier design were identified as a major drawback to efficient design, even when examples of inductors are packaged in design HIT-Kits. The main contribution of this research is engineering of an inductor design process, which in-effect contributes towards enhancing conventional power amplifiers. This inductance search algorithm finds the highest quality factor configuration of a single-layer square spiral inductor within certain tolerance using formulae for inductance and inductor parasitics of traditional single-π inductor model. Further contribution of this research is a set of algorithms for the complete design of switch-mode (Class-E and Class-F) power amplifiers and their output matching networks. These algorithms make use of classic deterministic design equations so that values of parasitic components can be calculated given input parameters, including required output power, centre frequency, supply voltage, and choice of class of operation. The hypothesis was satisfied for SiGe BiCMOS S35 process from Austriamicrosystems (AMS). Several metal-3 and thick-metal inductors were designed using the abovementioned algorithm and compared with experimental results provided by AMS. Correspondence was established between designed, experimental and EM simulation results, enabling qualification of inductors other than those with experimental results available from AMS by means of EM simulations with average relative errors of 3.7% for inductors and 21% for the Q factor at its peak frequency. For a wide range of inductors, Q-factors of 10 and more were readily experienced. Furthermore, simulations were performed for number of Class-E and Class-F amplifier configurations with HBTs with ft greater than 60 GHz and total emitter area of 96 μm² as driving transistors to complete the hypothesis testing. For the complete PA system design (including inductors), simulations showed that switch-mode power amplifiers for 50 Ω load at 2.4 GHz centre frequency can be designed using the streamlined method of this research for the output power of about 6 dB less than aimed. This power loss was expected, since it can be attributed to non-ideal properties of the driving transistor and Q-factor limitations of the integrated inductors, assumptions which the computations of the routine were based on. Although these results were obtained for a single micro-process, it was further speculated that outcome of this research has a general contribution, since streamlined method can be used with a much wider range of CMOS and BiCMOS processes, when low-gigahertz operating power amplifiers are needed. This theory was confirmed by means of simulation and fabrication in 180 nm BiCMOS process from IBM, results of which were also presented. The work presented here, was combined with algorithms for SPICE netlist extraction and the spiral inductor layout extraction (CIF and GDSII formats). This secondary research outcome further contributed to the completeness of the design flow. All the above features showed that the routine developed here is substantially better than cut-and-try methods for design of power amplifiers found in the existing body of knowledge.
Thesis (PhD(Eng))--University of Pretoria, 2011.
Electrical, Electronic and Computer Engineering
unrestricted

This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.
M.S.E.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE

É apresentado um amplificador de potência (PA) com controle digital da potência de saída, operando na banda S de frequência (2,2 GHz). Este PA utiliza um transformador de entrada para reduzir as flutuações dos sinais de terra. Um estágio de excitação oferece uma impedância apropriada para a fonte de entrada e ganho para o próximo estágio. O estágio de controle é usado para melhorar a eficiência do PA, composto por quatro ramos paralelos de chaves, onde os estados (ligado ou desligado) são separadamente ativados por uma palavra de controle de 4 bits. O estágio de saída implementa um amplificador classe E, usando uma topologia cascode para minimizar o estresse de tensão sobre os transistores, permitindo sua utilização sob tensão de alimentação de 3,3 V para se atingir uma potência de saída máxima em torno de 1 W, em um processo CMOS 130 nm, cuja tensão típica de alimentação é 1,2 V. O PA proposto foi projetado em uma tecnologia CMOS 130 nm para RF, ocupa uma área de 1,900 x 0,875 mm2 e os resultados das simulações em leiaute extraído obtidos demonstram uma potência de saída máxima de 28,5 dBm (707 mW), com PAE (Power- Added Efficiency) correspondente de 49,7%, para uma tensão de alimentação de 3,3 V. O controle de 4 bits permite um ajuste dentro da faixa dinâmica da potência de saída entre 13,6 a 28,5 dBm (22,9 a 707 mW), divididos em 15 passos, com o PAE variando de 9,1% a 49,7%. O PA proposto permite redução do consumo de potência quando este não está transmitindo na potência máxima. A potência consumida atinge um mínimo de 0,21Wquando a potência de saída é de 13,6 dBm (22,9 mW) e um máximo de 1,4 W quando a potência de saída é de 28,5 dBm (707 mW), o que representa 1,19 W de economia, aumentando a vida da bateria. A linearidade obtida neste circuito mostrou-se suficiente para atender os requisitos da máscara de emissão de espúrios de um padrão de comunicação com envoltória constante largamente utilizado, apresentando desempenho adequado para atender as especificações dos sistemas de comunicações modernos.
A power amplifier with digital power control useful to S-Band (2.2 GHz) applications and with an output power around 1 W is presented. It uses an input transformer to reduce ground bounce effects. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) is separately activated by a 4-bit input. The class-E power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF CMOS process and the layout has a total area of 1.900 x 0.875 mm2, post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 49.7% under 3.3 V of supply voltage. The 4-bit control allows a total output power dynamic range adjustment of 14.9 dB, divided in 15 steps, with the PAE changing from 9.1% to 49.7%. The proposed PA allows reduce the power consumption when it isn’t transmitting at the maximum output power. Where the power consumption is only 0.21 W when the PA is at the minimum output power level of 13.6 dBm (22.9 mW), which is 1.19 W smaller than the power consumption at full mode (1.4 W), increasing the battery life. The linearity in this circuit meet the emission mask requirements for a widely used communication standard with constant envelope. Post-layout simulation results indicate an overall performance adequate to fulfill the specifications of modern wireless communication systems.

Questa tesi tratta dell’amplificatore di potenza (PA–Power Amplifier) operante in classe E. Si tratta di un convertitore DC/AC ad elevato rendimento che può trovare impiego in numerose applicazioni in cui il problema della generazione di calore o la necessità di non sprecare energia sono particolarmente stringenti (ad esempio apparati per cui non è previsto un impianto di raffreddamento e/o apparati alimentati a batteria). L’elevato rendimento di un amplificatore operante in classe E deriva dalle specifiche forme d’onda ai capi del dispositivo attivo impiegato, tali per cui la perdita di commutazione durante la fase di accensione dello switch diviene pressoché trascurabile (Zero-Voltage-Switching e Zero-Derivative-Voltage Turn-ON). Il prezzo da pagare per ottenere queste benefiche forme d’onda è quello di avere un valore di cresta della tensione sul dispositivo che commuta assai più elevato del valore medio, coincidente con la tensione di alimentazione DC. In generale si stima una tensione di picco fra le 3 e le 5 volte più elevata della tensione DC, in funzione del Duty-Cycle e dell’assorbimento di corrente sul carico. Occorre poi tenere presente che in condizioni dinamiche (ad esempio qualora si collegasse direttamente l’amplificatore all’alimentazione) potrebbero innescarsi dei transitori tali per cui la tensione di picco ecceda anche il range suddetto. Per questo motivo è bene porre un limite alla massima tensione di picco adottando dei circuiti di protezione del transistore al fine di evitare la sua distruzione per limiti legati alla tensione di breakdown. Questi circuiti sono denominati clamper: in questa tesi valuteremo le modalità con cui si può implementare tale protezione; valuteremo, inoltre, i vantaggi e gli svantaggi derivanti dall’impiego di tali circuiti. Questi clamper sono prevalentemente di tipo dissipativo (Zener); nel corso della tesi si è studiato la realizzazione di un clamper rigenerativo che utilizza un trasformatore, ma si è constatata la irrealizzabilità fisica a causa della inevitabile presenza della induttanza dispersa.

The convergence of information technology and consumer electronics towards battery powered portable devices has increased the interest in high efficiency, low dissipation amplifiers. Class D amplifiers are the state of the art in low power consumption and high performance amplification. In this thesis we explore the possibility of exploiting nonlinearities introduced by the PWM modulation, by designing an optimized modulation law which scales its carrier frequency adaptively with the input signal's average power while preserving the SNR, thus reducing power consumption. This is achieved by means of a novel analytical model of the PWM output spectrum, which shows how interfering harmonics and their bandwidth affect the spectrum. This allows for frequency scaling with negligible aliasing between the baseband spectrum and its harmonics. We performed low noise power spectrum measurements on PWM modulations generated by comparing variable bandwidth, random test signals with a variable frequency triangular wave carrier. The experimental results show that power-optimized frequency scaling is both feasible and effective. The new analytical model also suggests a new PWM architecture that can be applied to digitally encoded input signals which are predistorted and compared with a cosine carrier, which is accurately synthesized by a digital oscillator. This approach has been simulated in a realistic noisy model and tested in our measurement setup. A zero crossing search on the obtained PWM modulation law proves that this approach yields an equivalent signal quality with respect to traditional PWM schemes, while entailing the use of signals whose bandwidth is remarkably smaller due to the use of a cosine instead of a triangular carrier.

碩士
國立臺北科技大學
電腦與通訊研究所
101
The injection-locked oscillators (ILOs) have found their ways in many applications, such as frequency dividers, self-oscillating mixers (SOMs), synchronized amplifier, and spectrum sensing circuits. In the recent years, many researchers have proposed the wireless non-contact vital-sign sensors based on the microwave Doppler radar. As the wireless medical telemetry services (WMTS) are evolving rapidly, the demand for simple, low-power consumption, and small cardiopulmonary monitors are growing accordingly as well. This thesis presents a switching-mode ILO that is based on the class-E operation invented by Sokals in 1975. A switching amplifier and a feedback resonator form the closed-loop for such a circuit to oscillate at a certain desired frequency. The class-E operation benefits the oscillator with higher efficiency than conventional ones. This work is aimed to a noncontact vital-sign sensing system with higher efficiency and lower cost. The last part of this thesis shows the proposed dual tuning voltage Class-E ILO. Based on the proposed architecture, the measured phase noise is -106.71 dBc/Hz at 1-MHz offset from 2.4 GHz, the oscillation frequency can be varied from 2.37 GHz to 2.43 GHz, the measured frequency tuning range is 2.5%.

NOTE: Text or symbols not renderable in plain ASCII are indicated by [...]. Abstract is included in .pdf document. A new family of harmonic-tuned switching amplifiers is introduced having the beneficial features of the class-E tuning while allowing improved performance to be achieved through additional harmonic tuning. This E/F family may be tuned to achieve the ZVS/ZdVS switching features characteristic of the class-E amplifier and, like the class-E tuning, accounts and compensates for the effect of the switch parallel capacitance. By tuning one or more overtones to the [...] tuning, however, the switching waveforms may be improved, lowering the peak voltage and reducing the RMS current. Additionally, the tolerance to large switch parallel capacitance is generally improved so that a larger switching device may be used, allowing reduction of the on-resistance. Due to these factors, the efficiency of E/F amplifiers is expected to exceed that of class E. To demonstrate these advantages, methods of estimating the optimal efficiency of switching amplifiers using waveform properties are given. A general solution technique is then presented which allows the calculation of the ZVS tuning requirements and the resulting switching waveforms for an arbitrary harmonic tuning. Using these two tools, switching waveforms and resulting efficiency estimates are calculated for E/F amplifier tunings, which are then compared to class E. Finally, potential application areas of the E/F technique are explored, and measured results of several first-generation E/F amplifiers are presented. Aside from efficiency benefits, E/F amplifiers also may achieve load-invariance, dual- and multi-band operation, high volumetric power densities, and efficient integrated circuit implementation using the Aoki distributed active transformer power combining structure.

碩士
國立交通大學
電控工程研究所
106
Wireless power transfer system (WPT) technology in recent years gradually improves. A large number of commercial electronic equipment have great demands for high power. Thus, high power and high efficiency become an important issue. WPT system includes transmitter (TX) and receiver (RX). During the transmission, the changes of load and the relative distance affect transmission power and efficiency. Generally speaking, the most common solution is the frequency modulation technique but it contradicts the switching frequency requirement in the A4WP specifications. That is, the modulated frequency is far from the desired switching frequency which is defined as 6.78MHz ± 15kHz. Another intuitive practice is to use a number of compensation capacitors to digitally modulate and achieve the matching requirements corresponding to the variations of WPT system. Unfortunately, in order to resist wide load variation in high power demands, this modulation method must be combined with multiple high voltage switches and compensation capacitors, thereby occupying a larger footprint area and reducing control efficiency. In this thesis, a main structure with a Class-E power amplifier and a Gallium Nitride (GaN) power transistor used at the TX terminal are proposed. The control circuit causes the GaN power transistor to reach zero voltage (ZVS) switching and zero voltage derivative (ZVDS) switching. The power transmission achieves high power and high efficiency simultaneously. Moreover, compared with the state-of-the-arts, due to the voltage controlled compensation capacitor in the analogy modulation method, the control is relatively simple and area efficient.

In this thesis an RF Class-D Power Amplifier is presented. The analysis of the Class-D amplifier considering ideal components has shown that the drain efficiency of 100% can be achieved. The output power and the drain efficiency are degraded by the internal resistance of each component. A driver is used to drive the gate capacitances of the Class-D amplifier. Both driver and amplifier are implemented with CMOS inverters. The size of the inverters in the driver is scaled down by a factor of 3 relatively to the preceding stage. The first being the inverter of the Class-D amplifier. At the output a 3rd order Butterworth bandpass filter is implemented. A non-ideal analysis of the Class-D amplifier is performed to create a base model which is used to aid in the design of the circuit. The RF Class-D Power Amplifier with the operation frequency of 2.4GHz was implemented with standard 130 nm CMOS technology. Two simulations were taken into account considering ideal and pre-layout components in the output filter. The following results were obtained when using ideal components: the output power of 6.91 dBm, the drain efficiency of 40% and the overall efficiency of 23%. Using pre-layout components the results were the following: the output power of 0.317 dBm the drain and overall efficiency of 8.6% and 4.9%, respectively.

In this thesis strategies to achieve a high efficiency RF front-end are studied and presented. A high efficiency Power Amplifier is also proposed and simulated. The applications for this type of designs are vast, but the main ones are in mobile transmission devices where the only power supply source available is a battery. In order to perform this thesis several topologies of power amplifiers were studied, and the decision fell to those based on a switching behavior. The reason for this decision was the need for high efficiency (it’s one of the main objectives). The Class-D power amplifier with its ideal potential efficiency of 100% has proven the most promising for implementation. The objectives for this thesis in terms of implementation were an efficiency of 20% and an output power of 0dBm. Finally, a power-combining technique was used to explore the potential of achieving high output power without affecting the efficiency.