Relevant bibliographies by topics / CLB (Configurable logic block)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'CLB (Configurable logic block)'

Author: Grafiati
Published: 5 June 2025
Last updated: 2 August 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'CLB (Configurable logic block).'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "CLB (Configurable logic block)"

1

Zhang, Jun Bin, Jin Yan Cai, and Dan Yang Li. "A Novel Fault Orientation Technique of FPGA Configurable Logic Blocks Based on Improved Shift Register." Applied Mechanics and Materials 347-350 (August 2013): 1602–6. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1602.

Full text
Abstract:
With the development of digital integrate circuit system which is based on Field Programmable Gate Arrays (FPGA), the request on FPGA test technique is becoming higher and higher. The Boundary Scan Technique and Built-In Self-Test (BIST) technique appear in succession, however, these techniques dont implement Configurable Logic Block (CLB) fault diagnose and fault orientation. Arrays-based technique was advanced, which also have some problems about masking of faults and too many reconfiguration times. According to these problems, A Novel Shift Register-based technique for Fault Orientation of
APA, Harvard, Vancouver, ISO, and other styles
2

Zia, Razia, Muzaffar Rao, Arshad Aziz, and Pervez Akhtar. "Efficient Utilization of FPGA Using LUT-6 Architecture." Applied Mechanics and Materials 241-244 (December 2012): 2548–54. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.2548.

Full text
Abstract:
Field Programmable gate array (FPGA) technology is continuously gaining market share and becoming essential part of the today’s modern embedded systems. The most common FPGA architecture consists of an array of logic blocks called Configurable Logic Block (CLB), I/O pads, and routing channels. In general, a logic block (CLB) consists of logical cells called Slices and other dedicated resources. A typical cell consists of LUTs (Look up table). In modern FPGAs, there are 6-input LUTs instead of 4-input LUTs. In this paper we present the use of 6-input LUT architecture for some Boolean functions
APA, Harvard, Vancouver, ISO, and other styles
3

GHOSH, BAHNIMAN, J. SIVA CHANDRA, and AKSHAYKUMAR SALIMATH. "DESIGN OF A MULTI-LAYERED QCA CONFIGURABLE LOGIC BLOCK FOR FPGAs." Journal of Circuits, Systems and Computers 23, no. 06 (2014): 1450089. http://dx.doi.org/10.1142/s0218126614500893.

Full text
Abstract:
In this paper, a Multi-layered configurable logic block (CLB) unit for field programmable gate arrays (FPGAs) is proposed based on quantum-dot cellular automata (QCA) technology. The design is made in multiple layers which help to process information simultaneously, in different layers. Various components of CLB like (4 × 16) Decoder, Memory units, Multiplexers and RS-Flip flops are all designed in multiple layers using higher input majority gates to reduce the cell count and latency compared to previous designs. QCA Designer tool is used to design and simulate the model. The Coherence vector
APA, Harvard, Vancouver, ISO, and other styles
4

Kim, Kyungah, Duc M. Tran, and Joon-Young Choi. "Implementation of EnDat Interface Master Using Configurable Logic Block in MCU." Electronics 13, no. 6 (2024): 1101. http://dx.doi.org/10.3390/electronics13061101.

Full text
Abstract:
In this study, we propose an implementation method of the Encoder Data (EnDat) interface master for slave encoders using only a configurable logic block (CLB) and a serial peripheral interface (SPI) integrated into microcontroller units. By programming the CLB device to execute logic functions and finite state machines designed for the EnDat interface master operation, we realize the EnDat and SPI clocks that are required for the EnDat interface master operation. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex program
APA, Harvard, Vancouver, ISO, and other styles
5

Wang, Guo Hua, and Jing Lin Sun. "BIST-Based Method for Diagnosing Multiple Faulty CLBs in FPGAs." Applied Mechanics and Materials 643 (September 2014): 243–48. http://dx.doi.org/10.4028/www.scientific.net/amm.643.243.

Full text
Abstract:
This paper presents a new built-in self-test (BIST) method to realize the fault detection and the fault diagnosis of configurable logic blocks (CLBs) in FPGAs. The proposed BIST adopts a circular comparison structure to overcome the phenomenon of fault masking in diagnosing multiple faulty CLBs and improve the diagnostic resolution. To test the memory block in every CLB, different TPG structures are proposed to obtain maximum stuck-at fault coverage. For the LUT mode of the memory block, the TPG based on the LFSR is designed to provide Pseudo-exhaustive testing patterns, and for the distribute
APA, Harvard, Vancouver, ISO, and other styles
6

Rajesh, A., Basha SK Jameer, Xavier Francis, and Babu S. Hari. "A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 9, no. 12 (2020): 217–20. https://doi.org/10.35940/ijitee.L7985.1091220.

Full text
Abstract:
This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as com
APA, Harvard, Vancouver, ISO, and other styles
7

Yang, Wu, Milad Tanavardi Nasab, and Himanshu Thapliyal. "Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications." Electronics 13, no. 7 (2024): 1309. http://dx.doi.org/10.3390/electronics13071309.

Full text
Abstract:
Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is
APA, Harvard, Vancouver, ISO, and other styles
8

Divakara, S. S., Sudarshan Patilkulkarni, and Cyril Prasanna Raj. "High Speed Area Optimized Hybrid DA Architecture for 2D-DTCWT." International Journal of Image and Graphics 18, no. 01 (2018): 1850004. http://dx.doi.org/10.1142/s0219467818500043.

Full text
Abstract:
In this paper, hybrid architecture for DTCWT computation is designed and implemented on FPGA based on DA algorithm. The distributive arithmetic (DA) algorithm is combined with multiplexer based algorithm to optimize the resource utilization on configurable logic block (CLB). The filter coefficients of DTCWT are quantized, rounded to its nearest integer for DTCWT computation and the loss in rounding and quantization is limited to 0.5[Formula: see text]dB as compared with software implementation. The parallel architecture designed computes row elements simultaneously and pipelined architecture i
APA, Harvard, Vancouver, ISO, and other styles
9

Luo, Yukui, Shijin Duan, and Xiaolin Xu. "FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA." ACM Transactions on Design Automation of Electronic Systems 27, no. 3 (2022): 1–31. http://dx.doi.org/10.1145/3491214.

Full text
Abstract:
With the emerging cloud-computing development, FPGAs are being integrated with cloud servers for higher performance. Recently, it has been explored to enable multiple users to share the hardware resources of a remote FPGA, i.e., to execute their own applications simultaneously. Although being a promising technique, multi-tenant FPGA unfortunately brings its unique security concerns. It has been demonstrated that the capacitive crosstalk between FPGA long-wires can be a side-channel to extract secret information, giving adversaries the opportunity to implement crosstalk-based side-channel attac
APA, Harvard, Vancouver, ISO, and other styles
10

Lu, Shyue-Kung, Fu-Min Yeh, and Jen-Sheng Shih. "Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs." VLSI Design 15, no. 1 (2002): 397–406. http://dx.doi.org/10.1080/1065514021000012011.

Full text
Abstract:
In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "CLB (Configurable logic block)"

1

Erxleben, Fredo. "Graphical Support for the Design and Evaluation of Configurable Logic Blocks." Thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-175486.

Full text
Abstract:
Developing a tool supporting humans to design and evaluate CLB-based circuits requires a lot of know-how and research from different fields of computer science. In this work, the newly developed application q2d, especially its design and implementation will be introduced as a possible tool for approaching CLB circuit development with graphical UI support. Design decisions and implementation will be discussed and a workflow example will be given.
APA, Harvard, Vancouver, ISO, and other styles
2

Al-aqeeli, Abulqadir. "Reconfigurable wavelet-based architecture for pattern recognition applications using a field programmable gate array." Ohio University / OhioLINK, 1998. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1177008904.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Balijepalli, Heman. "Design, Implementation, and Test of Novel Quantum-dot Cellular Automata FPGAs for the beyond CMOS Era." University of Toledo / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1333730938.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Erxleben, Fredo. "Graphical Support for the Design and Evaluation of Configurable Logic Blocks." Thesis, 2015. https://tud.qucosa.de/id/qucosa%3A28833.

Full text
Abstract:
Developing a tool supporting humans to design and evaluate CLB-based circuits requires a lot of know-how and research from different fields of computer science. In this work, the newly developed application q2d, especially its design and implementation will be introduced as a possible tool for approaching CLB circuit development with graphical UI support. Design decisions and implementation will be discussed and a workflow example will be given.:1 Introduction 1.1 Forethoughts 1.2 Theoretical Background 1.2.1 Definitions 1.2.2 Expressing Connections between Circuit Elements 1.2.3 Global Contex
APA, Harvard, Vancouver, ISO, and other styles
5

Ghani, A., Chan H. See, Hassan S. O. Migdadi, Rameez Asif, Raed A. Abd-Alhameed, and James M. Noras. "Reconfigurable neurons - making the most of configurable logic blocks (CLBs)." 2015. http://hdl.handle.net/10454/9152.

Full text
Abstract:
No<br>An area-efficient hardware architecture is used to map fully parallel cortical columns on Field Programmable Gate Arrays (FPGA) is presented in this paper. To demonstrate the concept of this work, the proposed architecture is shown at the system level and benchmarked with image and speech recognition applications. Due to the spatio-temporal nature of spiking neurons, this has allowed such architectures to map on FPGAs in which communication can be performed through the use of spikes and signal can be represented in binary form. The process and viability of designing and implementing the
APA, Harvard, Vancouver, ISO, and other styles
6

Li, Mei-Chen, and 李梅禎. "Standard Cell Like Via-Configurable Logic Block Design for Structured ASICs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/24568116981195847583.

Full text
Abstract:
碩士<br>元智大學<br>資訊工程學系<br>95<br>The popular IC design styles, standard cell design and FPGA, are facing a big challenge: attaining a proper balance between mask cost and performance. Structured ASIC retains some properties of standard cell designs such as higher performance and smaller area and also possesses some properties of FPGA such as low non-recurring engineering cost and re-configurability. It emerges as a good solution to the above challenge. A structured ASIC consists of some prefabricated transistors, prefabricated masks for some metal layers, and a couple of un-customized masks for v
APA, Harvard, Vancouver, ISO, and other styles
7

Liu, Hsin-Hung, and 劉信宏. "SRAM Compiler for Structured ASIC with Via Configurable Logic Block and Routing Fabric." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/28398344293157622867.

Full text
Abstract:
碩士<br>元智大學<br>資訊工程學系<br>99<br>With the advances in integrated circuit(IC) process, IC design issues that need to be handled will be more difficult. Since a chip consists of numerous pattern formational layers, mask cost becomes very large for an advanced manufacturing process. To reduce the cost of IC design and manufacturing, structured ASIC emerges as a new design alternative. A structured ASIC consists of some prefabricated transistors, prefabricated masks for some metal layers, and a couple of un-customized masks for vias (sometimes metal layers). A base block for structured ASICs must pro
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "CLB (Configurable logic block)"

1

Leong, Chee Hock, T. Nandha Kumar, and Haider A. F. Almurib. "Nonvolatile configurable logic block for FPGAs." In Low Power Designs in Nanodevices and Circuits for Emerging Applications. CRC Press, 2023. http://dx.doi.org/10.1201/9781003459231-10.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Jayalakshmi, R., and M. Senthil Kumaran. "Modeling of Potentially Implementable Configurable Logic Block in Quantum Dot Cellular Automata for Nanoelectronic Device Architecture." In Springer Proceedings in Materials. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-6267-9_69.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Capmany, José, and Daniel Pérez. "Field Programmable Photonic Gate Arrays." In Programmable Integrated Photonics. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0009.

Full text
Abstract:
The field programmable photonic gate array (FPPGA) is an integrated photonic device/subsystem that operates similarly to a field programmable gate array in electronics. It is a set of programmable photonics analogue blocks (PPABs) and of reconfigurable photonic interconnects (RPIs) implemented over a photonic chip. The PPABs provide the building blocks for implementing basic optical analogue operations (reconfigurable/independent power splitting and phase shifting). Broadly they enable reconfigurable processing just like configurable logic elements (CLE) or programmable logic blocks (PLBs) car
APA, Harvard, Vancouver, ISO, and other styles
4

Chandarana, Peyton, Mohammed Elbtity, Ronald F. DeMara, and Ramtin Zand. "MRAM-Based FPGAs: A Survey." In Computer Memory and Data Storage [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.108212.

Full text
Abstract:
Over the last decade, field programmable gate arrays (FPGAs) have embraced heterogeneity in a transformative way by leveraging emerging memory devices along with conventional CMOS-based devices to realize technology-specific benefits. Memristive device technologies exhibit desirable characteristics such as non-volatility, scalability, near-zero leakage, radiation hardness, and more, making them promising alternatives for SRAM cells found in conventional SRAM-based FPGAs. In recent years, a significant amount of research has been performed to take advantage of these emerging technologies to dev
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "CLB (Configurable logic block)"

1

Wu, Jun, Yong-Bin Kim, and Minsu Choi. "Configurable logic block (CLB) design for Asynchronous Nanowire Crossbar system." In 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2012. http://dx.doi.org/10.1109/mwscas.2012.6291984.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Sunny, Abann, S. Aiswariya, A. J. Rose, Jerrin Joseph, Mangal Jolly, and Vinod Pangracious. "Design & implementation of configurable logic block (CLB) using SET based QCA technology." In 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2012. http://dx.doi.org/10.1109/icsict.2012.6467735.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Sunny, Abann, S. Aiswariya, A. J. Rose, Jerrin Joseph, Mangal Jolly, and Vinod Pangracious. "Design & implementation of configurable logic block (CLB) using SET based QCA technology." In 2012 Annual IEEE India Conference (INDICON). IEEE, 2012. http://dx.doi.org/10.1109/indcon.2012.6420603.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Ramana Kumari, J. L. V., V. Kranthi Kumar, M. Abhignya, and P. Shiva Rama Krishna. "Design and Performance Analysis of Configurable Logic Block (CLB) for FPGA using Various Circuit Topologies." In 2024 3rd International Conference for Innovation in Technology (INOCON). IEEE, 2024. http://dx.doi.org/10.1109/inocon60754.2024.10511683.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Ghani, Arfan, Chan H. See, Hassan Migdadi, Rameez Asif, Raed A. A. Abd-Alhameed, and James M. Noras. "Reconfigurable neurons - making the most of configurable logic blocks (CLBs)." In 2015 Internet Technologies and Applications (ITA). IEEE, 2015. http://dx.doi.org/10.1109/itecha.2015.7317451.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Lakys, Yahya, Weisheng Zhao, Jacques-Olivier Klein, and Claude Chappert. "MRAM crossbar based configurable logic block." In 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6271934.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Pandey, Neeta, Maneesha Gupta, and Kirti Gupta. "A PFSCL based configurable logic block." In 2015 Annual IEEE India Conference (INDICON). IEEE, 2015. http://dx.doi.org/10.1109/indicon.2015.7443260.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Mane, Pravin S., Namita Paul, Nikhilesh Behera, Madankumar Sampath, and C. K. Ramesha. "Hybrid CMOS - Memristor based configurable logic block design." In 2014 International Conference on Electronics and Communication Systems (ICECS). IEEE, 2014. http://dx.doi.org/10.1109/ecs.2014.6892532.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Basha, B. Chagun, Sebastien Pillement, and Stanislaw J. Piestrak. "Fault-aware configurable logic block for reliable reconfigurable FPGAs." In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2015. http://dx.doi.org/10.1109/iscas.2015.7169251.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Gaillardon, Pierre-Emmanuel, Xifan Tang, and Giovanni De Micheli. "Novel configurable logic block architecture exploiting controllable-polarity transistors." In 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, 2014. http://dx.doi.org/10.1109/recosoc.2014.6861338.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'CLB (Configurable logic block)' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography