Academic literature on the topic 'Clock constraint'
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Journal articles on the topic "Clock constraint"
Mallet, Frédéric. "Clock constraint specification language: specifying clock constraints with UML/MARTE." Innovations in Systems and Software Engineering 4, no. 3 (August 9, 2008): 309–14. http://dx.doi.org/10.1007/s11334-008-0055-2.
Full textDai, Xiaolei, Yidong Lou, Zhiqiang Dai, Caibo Hu, Yaquan Peng, Jing Qiao, and Chuang Shi. "Precise Orbit Determination for GNSS Maneuvering Satellite with the Constraint of a Predicted Clock." Remote Sensing 11, no. 16 (August 20, 2019): 1949. http://dx.doi.org/10.3390/rs11161949.
Full textHuang, Wei, Pascale Defraigne, Giovanna Signorile, and Ilaria Sesia. "Improved Multi-GNSS PPP Software for Upgrading the DEMETRA Project Time Monitoring Service." Sensors 19, no. 20 (October 11, 2019): 4389. http://dx.doi.org/10.3390/s19204389.
Full textWu, Xiu Long, Zhi Ting Lin, Jian Meng, and Jun Ning Chen. "Process Antenna Effect Elimination in Ultra Deep Submicron." Applied Mechanics and Materials 229-231 (November 2012): 1519–22. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1519.
Full textQin, Weijin, Yulong Ge, Pei Wei, and Xuhai Yang. "An Approach to a Clock Offsets Model for Real-Time PPP Time and Frequency Transfer During Data Discontinuity." Applied Sciences 9, no. 7 (April 3, 2019): 1405. http://dx.doi.org/10.3390/app9071405.
Full textKrabbenhoft, T. J., and T. F. Turner. "Clock Gene Evolution: Seasonal Timing, Phylogenetic Signal, or Functional Constraint?" Journal of Heredity 105, no. 3 (February 20, 2014): 407–15. http://dx.doi.org/10.1093/jhered/esu008.
Full textYONEDA, T., K. MASUDA, and H. FUJIWARA. "Test Scheduling for Multi-Clock Domain SoCs under Power Constraint." IEICE Transactions on Information and Systems E91-D, no. 3 (March 1, 2008): 747–55. http://dx.doi.org/10.1093/ietisy/e91-d.3.747.
Full textMallet, Frédéric, Julien DeAntoni, Charles André, and Robert de Simone. "The clock constraint specification language for building timed causality models." Innovations in Systems and Software Engineering 6, no. 1-2 (December 22, 2009): 99–106. http://dx.doi.org/10.1007/s11334-009-0109-0.
Full textRamanna, S., and J. F. Peters. "Explicit clock temporal logic in constraint checking for real-time systems *." IFAC Proceedings Volumes 24, no. 10 (September 1991): 47–58. http://dx.doi.org/10.1016/b978-0-08-041698-4.50013-5.
Full textKeiser, Jane M., and Diana V. Lambdin. "The Clock Is Ticking: Time Constraint Issues in Mathematics Teaching Reform." Journal of Educational Research 90, no. 1 (September 1996): 23–31. http://dx.doi.org/10.1080/00220671.1996.9944440.
Full textDissertations / Theses on the topic "Clock constraint"
Traynard, Pauline. "Model Building by Temporal Logic Constraint Solving : Investigation of the Coupling between the Cell Cycle and the Circadian Clock." Sorbonne Paris Cité, 2016. http://www.theses.fr/2016USPCC087.
Full textIn this dissertation, we explore the use of temporal logic and model checking in systems biology. Our thesis is that temporal logic provides a powerful language to formalize complex yet imprecise dynamical properties of biological systems and to partly automate model building as a constraint satisfaction problem. We take advantage of this logical paradigm for systems biology to capture properties emerging from complex regulatory networks. First, we investigate the ability of Computation Tree Logic to verify dynamical properties in asynchronous state transition graphs derived from logical models of the mammalien cell cycle. Logical modeling provides a qualitative and potentially non-deterministic description of a biological system. This feature is useful to account for a variety of dynamical properties, observed in different conditions within a generic model. We develop an approach of iterative property verification to assist the building and updating of logical models. %ln that case, model-checking is efficiently used to analyze complex attractors and infer qualitative properties of the system. Then we consider quantitative deterministic models. For such models, oscillatory properties such as pseudo-periods and pseudo-phases are formalized by quantitative constraints in First-Order Linear Time Logic. A continuous model can provide a precise description of the mechanisms governing a complex regulatory network, and a quantitative prediction of its dynamics. However, the classical difficulties associated with this approach are brought by numerous and often poorly characterized kinetic parameters. We address this challenge by implementing two complementary strategies to obtain efficient solving of dynamical constraints over a finite time horizon : the design of useful temporal logic formula patterns associated with dedicated constraint solvers, and some trace simplification rules to safely reduce the size of the traces to analyze. We show that this approach enables the calibration of high-dimensional models on quantitative single-cell data with an application to model coupling for the mammalien cell cycle and the circadian clock. Understanding the relationships between these two molecular oscillators is an important problem in the field of chronobiology. We draw several coupling hypotheses and investigate their consequences
Lamprecht, Jaren Tyler. "FPGA Floor-Planning Impact on Implementation Results." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/3380.
Full textAnderson, Cajsa Lisa. "Dating Divergence Times in Phylogenies." Doctoral thesis, Uppsala University, Department of Evolution, Genomics and Systematics, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-8155.
Full textThis thesis concerns different aspects of dating divergence times in phylogenetic trees, using molecular data and multiple fossil age constraints.
Datings of phylogenetically basal eudicots, monocots and modern birds (Neoaves) are presented. Large phylograms and multiple fossil constraints were used in all these studies. Eudicots and monocots are suggested to be part of a rapid divergence of angiosperms in the Early Cretaceous, with most families present at the Cretaceous/Tertiary boundary. Stem lineages of Neoaves were present in the Late Cretaceous, but the main divergence of extant families took place around the Cre-taceous/Tertiary boundary.
A novel method and computer software for dating large phylogenetic trees, PATHd8, is presented. PATHd8 is a nonparametric smoothing method that smoothes one pair of sister groups at a time, by taking the mean of the added branch lengths from a terminal taxon to a node. Because of the local smoothing, the algorithm is simple, hence providing stable and very fast analyses, allowing for thousands of taxa and an arbitrary number of age constraints.
The importance of fossil constraints and their placement are discussed, and concluded to be the most important factor for obtaining reasonable age estimates.
Different dating methods are compared, and it is concluded that differences in age estimates are obtained from penalized likelihood, PATHd8, and the Bayesian autocorrelation method implemented in the multidivtime program. In the Bayesian method, prior assumptions about evolutionary rate at the root, rate variance and the level of rate smoothing between internal edges, are suggested to influence the results.
Doh, Yoonmee. "Voltage-clock scaling and scheduling for energy-constrained real-time systems." [Gainesville, Fla.] : University of Florida, 2003. http://purl.fcla.edu/fcla/etd/UFE0000675.
Full textSuryadevara, Jagadish. "Model Based Development of Embedded Systems using Logical Clock Constraints and Timed Automata." Doctoral thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-22328.
Full textARROWS
Selbst, Andrew D. (Andrew David). "Clock division as a power saving strategy in a system constrained by high transmission frequency and low data rate." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33360.
Full textIncludes bibliographical references (p. 63).
Systems are often restricted to have higher transmission frequency than required by their data rates. Possible constraints include channel attenuation, power requirements, and backward compatibility. As a result these systems have unused band- width, leading to inefficient use of power. In this thesis, I propose to slow the internal operating frequency of a cochlear implant receiver in order to reduce the internal power consumption by more than a factor of ten. I have created a new data encoding scheme, called "N-[pi] Shift Encoding", which makes clock division a viable solution. This clock division technique can be applied to other similarly constrained systems.
by Andrew D. Selbst.
M.Eng.
Zussa, Loic. "Étude des techniques d'injection de fautes par violation de contraintes temporelles permettant la cryptanalyse physique de circuits sécurisés." Thesis, Saint-Etienne, EMSE, 2014. http://www.theses.fr/2014EMSE0757/document.
Full textEven if a cryptographic algortihm could be mathematically secure, its physical implementation could be targeted by several attacks. This thesis focus on time-based fault injection mechanisms used for physical cryptanalysis of secure circuits.First, practical fault injections have been performed on a hardware AES implementation using non-invasive attacks : static and dynamic variations of the power supply voltage, frequency, temperature and electromagnetic environement. Then a comparison of these obtained faults led us to conclude that these different injection means share a common injection mecanism : timing constraints violations.An on-chip voltmeter has been designed and implemented to observe internal disturbences due to voltage glitchs. These observations led to a better understanding of the fault injection mecanism and to a better temporal accuracy.Then, a contermeasure has been designed and its effectiveness against electromagnetic attacks has been studied. Because of the electromagnetic pulses local effects, the aera effectively protected by the countermeasure is limited. The implementation of several countermeasures has been considered in order to extend the protected aera.Finally, a new attack path using the countermeasure detection threshold variations has been proposed and experimentaly validated. This attack exploit the electrical coupling between the AES and the coutnermeasure. Because of this coupling the countermeasure sensitivity variations are related to data handled by the AES
Exurville, Ingrid. "Détection non destructive de modification malveillante de circuits intégrés." Thesis, Saint-Etienne, EMSE, 2015. http://www.theses.fr/2015EMSE0800/document.
Full textThe globalization of integrated circuits fabrication involves several questions about the integrity of the fabricated circuits. Malicious modifications called Hardware Trojans (HT) can be introduced during the circuit production process. Due to the complexity of an integrated circuit, it is really difficult to find this kind of alterations.This work focuses on a non-destructive method of HT detection. We use the paths delays of the studied design as a channel to detect HT. A model to describe paths delays is defined. It takes into account two important parameters which are the experimental conditions and the process variations.Faults attacks by clock glitches based on timing constraints violations have been performed to measure data paths delays. Reliable circuits are used for reference. After validating the relevance of this channel to get information on the internal behavior of the targeted design, experimental detections of HT inserted on two different abstraction levels (RTL and after place and route) were achieved. Process variations are taken into consideration in the studies to detect if the tested circuits are infected
Kao, Chih-Cheng, and 高志承. "KDL: Clustering-Based Structure ASIC Placer Considering Clock-Domain Constraint." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/42650807287737264719.
Full text國立交通大學
資訊科學與工程研究所
98
Structure ASIC has emerged to fill the gap between ASIC and FPGA in recent years. To share more mask for amortizing the mask cost, the clock scheme is intrinsic and it makes placement stage more complicated by considering clock constraint. This work presents an algorithm to handle the placement problem of structure ASIC. First, our approach utilizes any existing standard-cell placer to generate an initial placement solution, and then we legalize this initial solution with simultaneously satisfying site type matching and clock constraint. The proposed clustering technique and clock pre-assignment algorithm consider node displacement and netlist distribution in clustering cells or assigning clock to complete legalization. After that, we apply an iterative block level wirelength improvement technique to further improve wirelenth. Experimental results indicate that our placer achieves 6% and 8% better wirelength than RegPlace [17] on average with mPL6 and Capo respectively; and incorporating with our algorithm, any existing standard-cell placer can complete structure ASIC placement with only small expense of CPU time.
CHANG, CHUN-CHIANG, and 張鈞強. "Timing-Constrained Register Reassignment for Clock Skew Minimization." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/52574729278913537335.
Full text中華大學
資訊工程學系碩士班
102
As technology scale down, process variation impacts on clock skew. In general, tree-based clock network cannot satisfy the skew requirement. Hence, routing redundancy in a mesh-based clock network must be applied to improve the tolerance and reliability for process variation. Besides that, clock skew can be further reduced in a mesh-based clock network. In a mesh-based clock network, the skew reduction can be estimated by using the skew reduction of the stub lengths on registers. In this paper, given a placement of connecting registers in a circuit inside a clock mesh and the setup and hold timing constrains of registers, a two-phase iterative reassignment algorithm is proposed to reassign the locations of all the registers under timing constrains for skew reduction in a mesh-based clock network. In the reassignment approach, based on the extraction of a safe timing-constrained region under setup and hold constrains, the registers with longer stub length are firstly reassigned to decrease the stub lengths on registers. Furthermore, the registers with shorter stub length are reassigned to increase the stub lengths on registers. After running two-phase iterative register reassignment, the skew of the stub lengths on register can be reduced. The experimental results show that our proposed algorithm can reassignment the locations of some registers to reduce 9.98% of the clock skew for the tested examples on the average.
Books on the topic "Clock constraint"
Reinecke, Juliane, Roy Suddaby, Ann Langley, and Haridimos Tsoukas, eds. Time, Temporality, and History in Process Organization Studies. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198870715.001.0001.
Full textChuriwala, Sanjay, and Sridhar Gangadharan. Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints. Springer, 2013.
Find full textChuriwala, Sanjay, and Sridhar Gangadharan. Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints. Springer, 2015.
Find full textBook chapters on the topic "Clock constraint"
Henz, Martin, Edgar Tan, and Roland Yap. "One Flip per Clock Cycle." In Principles and Practice of Constraint Programming — CP 2001, 509–23. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-45578-7_35.
Full textZholtkevych, Grygoriy, Frédéric Mallet, Iryna Zaretska, and Galyna Zholtkevych. "Two Semantic Models for Clock Relations in the Clock Constraint Specification Language." In Information and Communication Technologies in Education, Research, and Industrial Applications, 190–209. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-03998-5_10.
Full textMallet, Frédéric, and Grygoriy Zholtkevych. "Coalgebraic Semantic Model for the Clock Constraint Specification Language." In Communications in Computer and Information Science, 174–88. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17581-2_12.
Full textMontin, Mathieu, and Marc Pantel. "Mechanizing the Denotational Semantics of the Clock Constraint Specification Language." In Model and Data Engineering, 385–400. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-00856-7_26.
Full textZhang, Min, and Frédéric Mallet. "An Executable Semantics of Clock Constraint Specification Language and Its Applications." In Communications in Computer and Information Science, 37–51. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29510-7_2.
Full textZhang, Min, Fu Song, Frédéric Mallet, and Xiaohong Chen. "SMT-Based Bounded Schedulability Analysis of the Clock Constraint Specification Language." In Fundamental Approaches to Software Engineering, 61–78. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-16722-6_4.
Full textLiu, Shuai, Rui Guo, Xiaojie Li, and Qian Chen. "Evaluation and Analysis of Orbit Determination Accuracy of BDS Satellite Under Clock Offset Constraint." In Lecture Notes in Electrical Engineering, 83–96. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-3711-0_8.
Full textZhu, Qing K. "Overview to Timing Constraints." In High-Speed Clock Network Design, 23–40. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_2.
Full textGray, C. Thomas, Wentai Liu, and Ralph K. Cavin. "Clock Period Constraints: Single Stage Systems." In The Kluwer International Series in Engineering and Computer Science, 13–44. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-3206-4_2.
Full textGray, C. Thomas, Wentai Liu, and Ralph K. Cavin. "Clock Period Constraints: Multiple Stage Systems." In The Kluwer International Series in Engineering and Computer Science, 45–60. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-3206-4_3.
Full textConference papers on the topic "Clock constraint"
Andre, Charles, Frederic Mallet, and Julien DeAntoni. "VHDL observers for clock constraint checking." In 2010 International Symposium on Industrial Embedded Systems (SIES). IEEE, 2010. http://dx.doi.org/10.1109/sies.2010.5551372.
Full textHaghbayan, M. H., S. Safari, and Z. Navabi. "Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST." In 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2012. http://dx.doi.org/10.1109/ddecs.2012.6219022.
Full textLei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, and Jason Govig. "Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains." In 2007 IEEE/ACM International Conference on Computer-Aided Design. IEEE, 2007. http://dx.doi.org/10.1109/iccad.2007.4397292.
Full textUysal, Necati, Wen-Hao Liu, and Rickard Ewetz. "Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew." In ASPDAC '19: 24th Asia and South Pacific Design Automation Conference. New York, NY, USA: ACM, 2019. http://dx.doi.org/10.1145/3287624.3287681.
Full textZhang, Min, and Yunhui Ying. "Towards SMT-based LTL model checking of clock constraint specification language for real-time and embedded systems." In LCTES '17: SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2017. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3078633.3081035.
Full textStarling, Alex C., and Kristina Shea. "A Clock Grammar: The Use of a Parallel Grammar in Performance-Based Mechanical Synthesis." In ASME 2002 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2002. http://dx.doi.org/10.1115/detc2002/dtm-34026.
Full textSuryakumar, Mahadevan, Lu-Vong T. Phan, Mathew Ma, and Wajahat Ahmed. "Dual Die Package Design Strategy and Performance." In ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/ipack2005-73391.
Full text"Clock Period Constrained Minimal Buffer Insertion In Clock Trees." In IEEE/ACM International Conference on Computer-Aided Design. IEEE, 1994. http://dx.doi.org/10.1109/iccad.1994.629769.
Full textAng, Chin Hai. "Single Test Clock with Programmable Clock Enable Constraints for Multi-clock Domain SoC ATPG Testing." In 2013 22nd Asian Test Symposium (ATS). IEEE, 2013. http://dx.doi.org/10.1109/ats.2013.44.
Full textYang, Shun-Cheng, and Shih-Hsu Huang. "Non-uniform clock mesh synthesis under temperature constraints." In 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2017. http://dx.doi.org/10.1109/edssc.2017.8126499.
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