Relevant bibliographies by topics / Clock divider

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Clock divider'

Author: Grafiati
Published: 4 June 2021
Last updated: 7 February 2022

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Journal articles on the topic "Clock divider"

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ZACKRIYA, V. MOHAMMED, JOHN REUBEN, ASHIM HARSH, and HARISH M. KITTUR. "LOW POWER FRACTIONAL-N FREQUENCY DIVIDER WITH IMPROVED RESOLUTION." Journal of Circuits, Systems and Computers 23, no. 08 (June 18, 2014): 1450112. http://dx.doi.org/10.1142/s0218126614501126.

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Multiple clock domain (MCD) systems have different blocks/IP cores operating at different frequencies. These different clocks are generated from a high frequency clock usually by integer division. Fractional-N frequency dividers (FFDs) are needed when the clock required by a block in MCD system is not possible to be derived by simple integer division. In this paper, we present such a FFD with an improved resolution of (1/8). Post layout simulation results after parasitic RC extraction in the 90-nm technology node show that our FFD is able to fractionally divide signals upto 2 GHz frequency with an average error of 0.11% in division ratio even with 2.5° phase error at the input. Our FFD consumes 754 μW when fractionally dividing a 2 GHz signal with a resolution of (1/8).
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Zhou Zhuya, 周竹雅, 江阳 Jiang Yang, 白光富 Bai Guangfu, 徐静 Xu Jing, 王顺艳 Wang Shunyan, and 李恒文 Li Hengwen. "Optoelectronic Hybrid Optical Clock Frequency Divider/Multiplier." Acta Optica Sinica 33, no. 3 (2013): 0306002. http://dx.doi.org/10.3788/aos201333.0306002.

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Zhang, Song Wei, and Cheng Zhao. "Design for Realizing Arbitrary Fractional Divider Based on FPGA which Duty Cycle is up to 50%." Applied Mechanics and Materials 347-350 (August 2013): 1653–57. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1653.

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This paper proposes a novel method for realizing arbitrary fractional divider based on FPGA. Analyzing the limitations of the existing frequency-divided methods, a new model which consists of two-level dividers is put forward. An arbitrary frequency-divided clock output can be obtained by this method approaching 50% of duty cycle. When the division factor is greater than 128, the duty cycle can be very close to 50% of the clock output. This method is proved to be feasible on the FPGA chip of ALTERA.
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Anand, G., N. Vidhyalakshmi, and R. Kavitha. "An Efficient Architecture for Flexible Divider Using Multi Modulo Prescaler." Applied Mechanics and Materials 626 (August 2014): 72–78. http://dx.doi.org/10.4028/www.scientific.net/amm.626.72.

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In this paper, Based on the Pulse swallow topology a low power single phase clock multiband flexible divider is designed for frequency synthesizer.The modified divider has wideband multimodulus 32/33/47/48 and 64/65/79/80 prescalar and improved bit cell for swallow counter, it divide frequencies in three band ranges.
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Yao, Yuan, Yanyi Jiang, Hongfu Yu, Zhiyi Bi, and Longsheng Ma. "Optical frequency divider with division uncertainty at the 10−21 level." National Science Review 3, no. 4 (September 26, 2016): 463–69. http://dx.doi.org/10.1093/nsr/nww063.

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Abstract Optical clocks with unprecedented accuracy of 10−18 promise innovations in many research areas. Their applications rely to a large extent on the ability of precisely converting the frequency from one optical clock to another, or particularly to the frequencies in the fiber telecom band for long-distance transmission. This report demonstrates a low-noise, high-precision optical frequency divider, which realizes accurate optical frequency conversion and enables precise measurement of optical frequency ratios. By measuring against the frequency ratio between the fundamental and the second harmonic of a 1064-nm laser instead of a second copy of the same system, we demonstrate that the optical frequency divider has a fractional frequency division instability of 6 × 10−19 at 1 s and a fractional frequency division uncertainty of 1.4 × 10−21. The remarkable numbers can support frequency division of the best optical clocks in the world without frequency-conversion-caused degradation of their performance.
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Manthena, Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, and Kiat Seng Yeo. "A Low-Power Single-Phase Clock Multiband Flexible Divider." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 2 (February 2012): 376–80. http://dx.doi.org/10.1109/tvlsi.2010.2100052.

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Park, Sungkyung, and Chester Sungchung Park. "High-Speed CMOS Frequency Dividers with Symmetric In-Phase and Quadrature Waveforms." Journal of Circuits, Systems and Computers 25, no. 10 (July 22, 2016): 1630006. http://dx.doi.org/10.1142/s0218126616300063.

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Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.
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SWARTZ, ROBERT G. "ULTRA-HIGH SPEED MULTIPLEXER/DEMULTIPLEXER ARCHITECTURES." International Journal of High Speed Electronics and Systems 01, no. 01 (March 1990): 73–99. http://dx.doi.org/10.1142/s0129156490000058.

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This paper describes two circuit architectures for ultra-high speed digital multiplexers and demultiplexers. The first, Type-I, is fully synchronous and uses a system clock that matches the maximum data rate. Circuits of this type can operate at a data rate equal to the maximum operating speed of a simple digital divider. A simpler and much more powerful architecture is proposed, Type-II, that operates using a half-frequency system clock at data rates up to twice the maximum clock speed of a simple digital divider. Basic building blocks and high speed design techniques are reviewed.
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Chang, Chih-Wei, and Yi-Jan Emery Chen. "A CMOS True Single-Phase-Clock Divider With Differential Outputs." IEEE Microwave and Wireless Components Letters 19, no. 12 (December 2009): 813–15. http://dx.doi.org/10.1109/lmwc.2009.2033523.

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Lin, Jun Jie, Chun Yang Wang, and Da Sen Wang. "Arbitrary Integer Frequency Divider Based on Single Chip Microcomputer." Applied Mechanics and Materials 441 (December 2013): 141–45. http://dx.doi.org/10.4028/www.scientific.net/amm.441.141.

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Arbitrary integer frequency divider based on single chip microcomputer proposed an arbitrary integer frequency divider design scheme within 100 for digital clock signals. Microcontroller detected the parity of the points frequency which was inputted by the external keyboard, and then controlled the switching controller switched the point frequency circuit between odd points frequency circuit and even. Therefore, a circuit design could solve problem along with the changing of the circuit and the heavy labor for changing the frequency num that existed in traditional divider .So it greatly reduced the cost.
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Dissertations / Theses on the topic "Clock divider"

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Preußer, Thomas B. "Background of the Analysis of a Fully-Scalable Digital Fractional Clock Divider." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-98662.

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It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm. It draws out the limits encountered by the existing implementation for both FPGA and VLSI realizations. A rather unconventional adoption of the carry-save representation combined with a soft-threshold comparison is proposed to circumvent these limitations. The resulting design is described and evaluated. Mathematically appealing results on the quality of the approximation achieved by this approach are presented. The underlying proofs and technical details are provided in the appendix.
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Preußer, Thomas B. "Background of the Analysis of a Fully-Scalable Digital Fractional Clock Divider." Technische Universität Dresden, 2006. https://tud.qucosa.de/id/qucosa%3A26194.

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It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm. It draws out the limits encountered by the existing implementation for both FPGA and VLSI realizations. A rather unconventional adoption of the carry-save representation combined with a soft-threshold comparison is proposed to circumvent these limitations. The resulting design is described and evaluated. Mathematically appealing results on the quality of the approximation achieved by this approach are presented. The underlying proofs and technical details are provided in the appendix.
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Omar, Omar Jaber. "An On-Chip Memory for Testing of High-Speed Mixed-Signal Circuits." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103800.

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Mixed-signal processing systems especially data converters can be reliably tested at high frequencies using on-chip testing schemes based on memory. In this thesis, an on-chip testing strategy based on shift registers/memory (2 k bits) has been proposed for digital-to-analog converters (DACs) operating at 5 GHz. The proposed design uses word length of 8 bits in order to test DAC at high speed of 5 GHz. The proposed testing strategy has been designed in standard 65 nm CMOS technology with additional requirement of 1-V supply. This design has been implemented using Cadence IC design environment. The additional advantage of the proposed testing strategy is that it requires lower number of I/O pins and avoids the large number of high speed I/O pads. It therefore also solves the problem of the bandwidth limitation that is associated with I/O transmission paths. The design of the on-chip tester based on memory contains no analog block and is implemented entirely in digital domain. In the proposed design, low frequency of 1 MHz has been used outside the chip to load the data into the memory during the write mode. During the read mode, the frequency of 625 MHz is used to read the data from the memory. A multiplexing system is used to reuse the stored data during read mode to test the intended functionality and performance. In order to convert the parallel data into serial data at high frequency at the memory output, serializer has been used. By using the frequencies of 1.25 GHz and 2.5 GHz, the serializer speeds up the data from the lower frequency of 625 MHz to the highest frequency of 5 GHz in order to test DAC at 5 GHz.
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Barale, Francesco. "Design of integrated frequency synthesizers and clock-data recovery for 60 GHz wireless communications." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37216.

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In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply. The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a 1 V power supply. The worst case phase noise is measured to be -80.1 dBc/Hz at 1 MHz offset from the highest frequency carrier (56.16 GHz). The output spectrum shows a reference spur attenuation of -32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming 30 mW of power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.
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Souza, Daniel Cardoso de. "Projeto de um circuito integrado divisor de frequencias/contador de decada em tecnologia GaAs-familia DCFL - para operação com clock na faixa de 1 GHz." [s.n.], 1998. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259498.

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Orientador: Luiz Carlos Kretly
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-07-24T00:05:19Z (GMT). No. of bitstreams: 1 Souza_DanielCardosode_M.pdf: 24727698 bytes, checksum: 802ba54b2fef69d2a43dfbabc8b9f7c4 (MD5) Previous issue date: 1998
Resumo: A crescente ênfase sobre a operação portátil de computadores e sistemas de telecomunicação prioriza circuitos de baixa potência, ainda que de alta velocidade. As opções tecnológicas existentes para aplicações digitais na faixa de 100MHz até 1 GHz são as famílias ECL em silício, DCFL em arseneto de gálio (GaAs), bem como ASICs CMOS realizados em processos avançados de Si, e somente as duas últimas podem proporcionar baixos consumos de potência. Em GaAs, DCFL é a principal opção de famíliadigital de baixa potência. Neste trabalho, descreve-se o projeto full-custom de um CI divisor de freqüências de módulo variável e contador de década, realizado na família DCFL de GaAs. A topologia deste CI é inteiramente baseada na arquitetura clássica do TTL 7490, que foi escolhida por causa de sua versatilidade, e toda a sua funcionalidade lógica é mantida: o CI proposto pode operar tanto como um contador BCD quanto como um divisor de frequências por N, com N na faixa de 2 até 10. A razão da divisão, N, pode ser configurada unicamente através de conexões diretas entre pinos do CI. Por isso, o CI projetado neste trabalho será referido como o 7490-like. Suas aplicações são em síntese/divisão de frequências, contagem, instrumentação de alta frequência e na composição de circuitos digitais de alta velocidade, podendo-se usá-lo na entrada de outros blocos. ... Observação: O resumo, na íntegra, poderá ser visualizado no texto completo da tese digital
Abstract: The increasing emphasis on the portable operation of computers and communication systems has placed a priority on low-power, yet high-speed, circuits. The existing viable technologies for digital applications in the range fTom100 l Hz up to 1 GHz are Si ECL and GaAs DCFL families, as well as high-speed CMOS ASICs implemented in advanced Si processes, and only the last two options offer low power consumption. In GaAs technology, DCFL is the main choice for a low-power digital family. In this work, a variable modulus frequency divider and decade counter IC was designed in the GaAs DCFL family. This work describes the full-custom design procedures for this IC, starting from its logic design, until the completion of the final layout version. This DCFL counter circuit topology is entirely based upon the classical TTL 7490 architecture, which was chosen because of its versatility, and all its functionality is retained: this IC can operate either as a decade (BCD) counter, or as a frequency divider by N, being N any integer in the range from 2 to 10. The frequency division modulus N can be set solely by means of direct connections between certain IC pins. Therefore, the IC designed in this work will be referred to as the 7490-like. This circuit's usual applications are: frequency synthesis or division, counting, high frequency instrumentation and as a block in the composition of high speed digital circuits; the IC can also be used before the input to other blocks. ... Note: The complete abstract is available with the full electronic digital thesis or dissertations
Mestrado
Mestre em Engenharia Elétrica
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Yen-Chuan, Huang. "A Miller Divider Based Clock Generator for MBOA-UWB Application." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2507200515123200.

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Huang, Yen-Chuan, and 黃彥筌. "A Miller Divider Based Clock Generator for MBOA-UWB Application." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/55023388488364977500.

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碩士
國立臺灣大學
電子工程學研究所
93
Although it began as a military application dating from the 1960s, UWB has been redefined as a high data rate, short-range technology that specifically addresses emerging applications in the consumer electronics, personal computing and mobile device markets. Under the auspices of the MultiBand OFDM Alliance (MBOA), personal computers and mobile devices have endorsed an approach called MultiBand Orthogonal Frequency Division Multiplexing (MB-OFDM) as the UWB solution. The MBOA UWB mode-1 system divides the 3.1-to-4.7-GHz spectrum into three sub-bands. The system requires band-switching time to be less than 9.5 ns. The traditional solution to synthesize the three carrier frequencies are employing single-sideband (SSB) mixing architecture. However, SSB mixing suffers from large carrier leakage and unwanted sideband due to the circuit mismatches. In this thesis, a Miller divider based clock generator is proposed to generate the three carrier frequencies of the MBOA-UWB mode-1 system while achieving less than 9.5-ns frequency settling time. The proposed approach adds a feedback mixer in the traditional Miller divider structure and the desired output frequency is determined by the band-pass filter. A simple method is also introduced to estimate the frequency-switching time by transforming the circuit into a frequency-domain equivalent model. For saving chip area, active inductors are used in the circuit design and an optimization technique is also presented to optimize the proposed active inductor with minimum power consumption. The proposed concepts are demonstrated in a 0.18-μm CMOS technology.
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Chen, Sheng-Tzung, and 陳聖宗. "Divider-Less Clock and Data Recovery Circuit and Multiplying Delay-Locked Loop." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/11382775109644451100.

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碩士
國立臺灣大學
電子工程學研究所
102
As the development and advancement of modern technology, portable device plays a more and more important role in the communication system. Due to the finite battery capacity, low power consumption becomes an important target to evaluate the performance of circuits. It is our desire to design the circuits featuring outstanding performances. This thesis is consisted of two parts. In chapter 2, we propose a multiplying delay-locked loop which uses its low-speed reference clock and input buffers to generate the selection signal. The selection signal even provides the divide function to MDLL feedback clock, and the divided clock output compares the phase error with reference clock. In this method, this MDLL can turn off the divider to save 30% power consumption. Its power consumption is 2.26mW from a 1.0V supply. The active area is 0.032mm2. In chapter 3, an injection-locked clock and data recovery circuit is presented with power detection technique to calibrate the frequency of digital control oscillator and generate the recovered clock. These power detection circuits take the place of reference PLL or other high-speed circuits in conventional CDR circuits, saving great power and area of inductors. The measured BER (bit error rate) is less than 10-12 for a 25 Gb/s PRBS of 27-1. Its power consumption is 24.9mW from a 1.1V supply. The total area is 0.23mm2.
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Book chapters on the topic "Clock divider"

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Arora, Mohit. "Clock Dividers." In The Art of Hardware Architecture, 87–93. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0397-5_4.

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Rawlins, Michael W. "Clock Dividers." In Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms, 29–32. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-70729-3_4.

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Christensen, Bryce. "Turning Back the Clock: Should America Try to Recover Lost Family Strengths?" In Divided We Fall, 165–81. Routledge, 2017. http://dx.doi.org/10.4324/9780203793077-10.

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"8. The Robbers of Divine Power." In The Cloak of Dreams, 104–8. Princeton University Press, 2010. http://dx.doi.org/10.1515/9781400836031.104.

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Muzafar, Saira, and N. Z. Jhanjhi. "Success Stories of ICT Implementation in Saudi Arabia." In Advances in Electronic Government, Digital Divide, and Regional Development, 151–63. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1851-9.ch008.

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Information and communication technology (ICT) has a great role in the development, growth, and economy of the country. ICT refers to any system, device, or product that can store, manipulate, and receive and transmit digital data effectively. ICT brings clear differences in the economy of countries wherever it is successfully implemented. It becomes a reason of timely, accurate, and efficient operations and becomes a source of user satisfaction by providing them fast, better, easy service around the clock. As timely access of information and communication plays a vital role in the success of any organization either public or private, many developed countries are already competing in digitalization. It is not only convenience, but it is the prime ingredient of good governance and an indispensable part of modern life. This chapter discusses the successful implementation of ICT infrastructures in the context of good governance and builds a vibrant society, the main agenda of Vision 2030 of KSA.
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"Agent-Based Modeling." In Advances in Electronic Government, Digital Divide, and Regional Development, 36–51. IGI Global, 2017. http://dx.doi.org/10.4018/978-1-5225-1782-5.ch003.

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Agent based modeling is one of many tools, from the complexity sciences, available to investigate complex policy problems. Complexity science investigates the non-linear behavior of complex adaptive systems. Complex adaptive systems can be found across a broad spectrum of the natural and human created world. Examples of complex adaptive systems include various ecosystems, economic markets, immune response, and most importantly for this research, human social organization and competition / cooperation. The common thread among these types of systems is that they do not behave in a mechanistic way which has led to problems in utilizing traditional methods for studying them. Complex adaptive systems do not follow the Newtonian paradigm of systems that behave like a clock works whereby understanding the workings of each of the parts provides an understanding of the whole. By understanding the workings of the parts and a few external rules, predictions can be made about the behavior of the system as a whole under varying circumstances. Such systems are labeled deterministic (Zimmerman, Lindberg, & Plsek, 1998).
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Lysack, Krista. "The Christian Year and the Consolations of Synchronized Time." In Chronometres, 29–54. Oxford University Press, 2019. http://dx.doi.org/10.1093/oso/9780198836162.003.0001.

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This chapter shows how the material arrangements and the chronometrics of Keble’s bestselling devotional volume are parallel features. The consolations of The Christian Year were such that they calibrated readers not only to the long time of the liturgical year but also synchronized them to clock time. While many contemporary readers lauded The Christian Year for its soothing properties, its long Victorian print afterlife is indicative of how devotion was being redefined as that century went on as a set of reading practices premised upon distraction and divided time. The eventual work of The Christian Year, in other words, was to console its readers according to a new realization of the replicable, interval time of modernity.
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Conover, Adam J. "A Simulation of Temporally Variant Agent Interaction via Passive Inquiry." In Machine Learning, 898–912. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60960-818-7.ch410.

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This chapter presents a description of ongoing experimental research into the emergent properties of multi-agent communication in “temporally asynchronous” environments. Many traditional agent and swarm simulation environments divide time into discrete “ticks” where all entity behavior is synchronized to a master “world clock”. In other words, all agent behavior is governed by a single timer where all agents act and interact within deterministic time intervals. This discrete timing mechanism produces a somewhat restricted and artificial model of autonomous agent interaction. In addition to the behavioral autonomy normally associated with agents, simulated agents should also have “temporal autonomy” in order to interact realistically. Part I of this two-part series focuses on an exploration of the effects of incremental migration of John Conway’s “Game of Life” form a simple cellular automata simulation to a framework for the exploration of spatially embedded agents.
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Conover, Adam J. "A Simulation of Temporally Variant Agent Interaction via Passive Inquiry." In Handbook of Research on Agent-Based Societies, 69–83. IGI Global, 2009. http://dx.doi.org/10.4018/978-1-60566-236-7.ch006.

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This chapter presents a description of ongoing experimental research into the emergent properties of multi-agent communication in “temporally asynchronous” environments. Many traditional agent and swarm simulation environments divide time into discrete “ticks” where all entity behavior is synchronized to a master “world clock”. In other words, all agent behavior is governed by a single timer where all agents act and interact within deterministic time intervals. This discrete timing mechanism produces a somewhat restricted and artificial model of autonomous agent interaction. In addition to the behavioral autonomy normally associated with agents, simulated agents should also have “temporal autonomy” in order to interact realistically. Part I of this two-part series focuses on an exploration of the effects of incremental migration of John Conway’s “Game of Life” form a simple cellular automata simulation to a framework for the exploration of spatially embedded agents.
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Conover, Adam J. "A Simulation of Temporally Variant Agent Interaction via Belief Promulgation." In Machine Learning, 913–27. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60960-818-7.ch411.

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This chapter concludes a two part series which examines the emergent properties of multi-agent communication in “temporally asynchronous” environments. Many traditional agent and swarm simulation environments divide time into discrete “ticks” where all entity behavior is synchronized to a master “world clock”. In other words, all agent behavior is governed by a single timer where all agents act and interact within deterministic time intervals. This discrete timing mechanism produces a somewhat restricted and artificial model of autonomous agent interaction. In addition to the behavioral autonomy normally associated with agents, simulated agents should also have “temporal autonomy” in order to interact realistically. This chapter focuses on the exploration of a grid of specially embedded, message-passing agents, where each message represents the communication of a core “belief”. Here, we focus our attention on the how the temporal variance of belief propagation from individual agents induces emergent and dynamic effects on a global population.
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Conference papers on the topic "Clock divider"

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Jin, Woojin, Moon-su Kim, Chan-min Jo, Hyosig Won, and Kyu-Myung Choi. "Automatic clock jitter analysis considering clock divider." In 2009 International SoC Design Conference (ISOCC). IEEE, 2009. http://dx.doi.org/10.1109/socdc.2009.5423857.

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Reuben, John, Zackriya V. Mohammed, and Harish M. Kittur. "Low power, high speed hybrid clock divider circuit." In 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT). IEEE, 2013. http://dx.doi.org/10.1109/iccpct.2013.6528876.

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Preuber, Thomas, and Rainer Spallek. "Analysis of a Fully-Scalable Digital Fractional Clock Divider." In IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06). IEEE, 2006. http://dx.doi.org/10.1109/asap.2006.14.

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Wang, Haochi, Xuewu Li, Lei Chen, Yanlong Zhang, Miao Chen, Zhiping Wen, Yanjun Lin, Xiankun Deng, and Lei Zhou. "A programmable DCO-based digital clock multiplier and divider." In 2013 2nd International Symposium on Instrumentation & Measurement, Sensor Network and Automation (IMSNA). IEEE, 2013. http://dx.doi.org/10.1109/imsna.2013.6743324.

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Priya, G., and M. Dinesh. "A low power double phase clock multiband flexible divider." In 2014 International Conference on Computer Communication and Informatics (ICCCI). IEEE, 2014. http://dx.doi.org/10.1109/iccci.2014.6921814.

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Wang, Yisheng, Kaixue Ma, and Kiat Seng Yeo. "A hybrid CMOS clock divider for PLL of 60GHz transceiver." In 2014 XXXIth URSI General Assembly and Scientific Symposium (URSI GASS). IEEE, 2014. http://dx.doi.org/10.1109/ursigass.2014.6929463.

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P, Srividya. "Finfet based Frequency Divider Design Using True Single Phase Clock Technique." In 2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE). IEEE, 2018. http://dx.doi.org/10.1109/icrieece44171.2018.9008856.

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Stuenkel, M., and M. Feng. "An InP VCO with Static Frequency Divider for Millimeter Wave Clock Generation." In 2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS). IEEE, 2010. http://dx.doi.org/10.1109/csics.2010.5619658.

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Du, Qingjin, Jingcheng Zhuang, and Tad Kwasniewski. "A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider." In 2006 Canadian Conference on Electrical and Computer Engineering. IEEE, 2006. http://dx.doi.org/10.1109/ccece.2006.277703.

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Wang, Lei, Yong-Zhong Xiong, San-Ming Hu, and Teck-Guan Lim. "Design of a true single-phase-clock divider in 0.13µm CMOS." In 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS). IEEE, 2010. http://dx.doi.org/10.1109/edaps.2010.5683039.

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