Log in

Relevant bibliographies by topics / Clock divider / Journal articles

To see the other types of publications on this topic, follow the link: Clock divider.

Journal articles on the topic 'Clock divider'

Author: Grafiati

Published: 4 June 2021

Last updated: 7 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Clock divider.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

ZACKRIYA, V. MOHAMMED, JOHN REUBEN, ASHIM HARSH, and HARISH M. KITTUR. "LOW POWER FRACTIONAL-N FREQUENCY DIVIDER WITH IMPROVED RESOLUTION." Journal of Circuits, Systems and Computers 23, no. 08 (June 18, 2014): 1450112. http://dx.doi.org/10.1142/s0218126614501126.

Full text

Abstract:

Multiple clock domain (MCD) systems have different blocks/IP cores operating at different frequencies. These different clocks are generated from a high frequency clock usually by integer division. Fractional-N frequency dividers (FFDs) are needed when the clock required by a block in MCD system is not possible to be derived by simple integer division. In this paper, we present such a FFD with an improved resolution of (1/8). Post layout simulation results after parasitic RC extraction in the 90-nm technology node show that our FFD is able to fractionally divide signals upto 2 GHz frequency with an average error of 0.11% in division ratio even with 2.5° phase error at the input. Our FFD consumes 754 μW when fractionally dividing a 2 GHz signal with a resolution of (1/8).

APA, Harvard, Vancouver, ISO, and other styles

2

Zhou Zhuya, 周竹雅, 江阳 Jiang Yang, 白光富 Bai Guangfu, 徐静 Xu Jing, 王顺艳 Wang Shunyan, and 李恒文 Li Hengwen. "Optoelectronic Hybrid Optical Clock Frequency Divider/Multiplier." Acta Optica Sinica 33, no. 3 (2013): 0306002. http://dx.doi.org/10.3788/aos201333.0306002.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Zhang, Song Wei, and Cheng Zhao. "Design for Realizing Arbitrary Fractional Divider Based on FPGA which Duty Cycle is up to 50%." Applied Mechanics and Materials 347-350 (August 2013): 1653–57. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1653.

Full text

Abstract:

This paper proposes a novel method for realizing arbitrary fractional divider based on FPGA. Analyzing the limitations of the existing frequency-divided methods, a new model which consists of two-level dividers is put forward. An arbitrary frequency-divided clock output can be obtained by this method approaching 50% of duty cycle. When the division factor is greater than 128, the duty cycle can be very close to 50% of the clock output. This method is proved to be feasible on the FPGA chip of ALTERA.

APA, Harvard, Vancouver, ISO, and other styles

4

Anand, G., N. Vidhyalakshmi, and R. Kavitha. "An Efficient Architecture for Flexible Divider Using Multi Modulo Prescaler." Applied Mechanics and Materials 626 (August 2014): 72–78. http://dx.doi.org/10.4028/www.scientific.net/amm.626.72.

Full text

Abstract:

In this paper, Based on the Pulse swallow topology a low power single phase clock multiband flexible divider is designed for frequency synthesizer.The modified divider has wideband multimodulus 32/33/47/48 and 64/65/79/80 prescalar and improved bit cell for swallow counter, it divide frequencies in three band ranges.

APA, Harvard, Vancouver, ISO, and other styles

5

Yao, Yuan, Yanyi Jiang, Hongfu Yu, Zhiyi Bi, and Longsheng Ma. "Optical frequency divider with division uncertainty at the 10−21 level." National Science Review 3, no. 4 (September 26, 2016): 463–69. http://dx.doi.org/10.1093/nsr/nww063.

Full text

Abstract:

Abstract Optical clocks with unprecedented accuracy of 10−18 promise innovations in many research areas. Their applications rely to a large extent on the ability of precisely converting the frequency from one optical clock to another, or particularly to the frequencies in the fiber telecom band for long-distance transmission. This report demonstrates a low-noise, high-precision optical frequency divider, which realizes accurate optical frequency conversion and enables precise measurement of optical frequency ratios. By measuring against the frequency ratio between the fundamental and the second harmonic of a 1064-nm laser instead of a second copy of the same system, we demonstrate that the optical frequency divider has a fractional frequency division instability of 6 × 10−19 at 1 s and a fractional frequency division uncertainty of 1.4 × 10−21. The remarkable numbers can support frequency division of the best optical clocks in the world without frequency-conversion-caused degradation of their performance.

APA, Harvard, Vancouver, ISO, and other styles

6

Manthena, Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, and Kiat Seng Yeo. "A Low-Power Single-Phase Clock Multiband Flexible Divider." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 2 (February 2012): 376–80. http://dx.doi.org/10.1109/tvlsi.2010.2100052.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Park, Sungkyung, and Chester Sungchung Park. "High-Speed CMOS Frequency Dividers with Symmetric In-Phase and Quadrature Waveforms." Journal of Circuits, Systems and Computers 25, no. 10 (July 22, 2016): 1630006. http://dx.doi.org/10.1142/s0218126616300063.

Full text

Abstract:

Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.

APA, Harvard, Vancouver, ISO, and other styles

8

SWARTZ, ROBERT G. "ULTRA-HIGH SPEED MULTIPLEXER/DEMULTIPLEXER ARCHITECTURES." International Journal of High Speed Electronics and Systems 01, no. 01 (March 1990): 73–99. http://dx.doi.org/10.1142/s0129156490000058.

Full text

Abstract:

This paper describes two circuit architectures for ultra-high speed digital multiplexers and demultiplexers. The first, Type-I, is fully synchronous and uses a system clock that matches the maximum data rate. Circuits of this type can operate at a data rate equal to the maximum operating speed of a simple digital divider. A simpler and much more powerful architecture is proposed, Type-II, that operates using a half-frequency system clock at data rates up to twice the maximum clock speed of a simple digital divider. Basic building blocks and high speed design techniques are reviewed.

APA, Harvard, Vancouver, ISO, and other styles

9

Chang, Chih-Wei, and Yi-Jan Emery Chen. "A CMOS True Single-Phase-Clock Divider With Differential Outputs." IEEE Microwave and Wireless Components Letters 19, no. 12 (December 2009): 813–15. http://dx.doi.org/10.1109/lmwc.2009.2033523.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Lin, Jun Jie, Chun Yang Wang, and Da Sen Wang. "Arbitrary Integer Frequency Divider Based on Single Chip Microcomputer." Applied Mechanics and Materials 441 (December 2013): 141–45. http://dx.doi.org/10.4028/www.scientific.net/amm.441.141.

Full text

Abstract:

Arbitrary integer frequency divider based on single chip microcomputer proposed an arbitrary integer frequency divider design scheme within 100 for digital clock signals. Microcontroller detected the parity of the points frequency which was inputted by the external keyboard, and then controlled the switching controller switched the point frequency circuit between odd points frequency circuit and even. Therefore, a circuit design could solve problem along with the changing of the circuit and the heavy labor for changing the frequency num that existed in traditional divider .So it greatly reduced the cost.

APA, Harvard, Vancouver, ISO, and other styles

11

Shen, Tianchen, Jiabing Liu, Chunyi Song, and Zhiwei Xu. "A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs." Electronics 8, no. 5 (May 27, 2019): 589. http://dx.doi.org/10.3390/electronics8050589.

Full text

Abstract:

A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual modulus frequency divider. The designed divide-by-3/4 achieved higher speed and lower power operation with mode control compared with the conventional ones. The prescaler was comprised of sixteen transistors and integrates an inverter in the second DFF to provide output directly. The power consumption was minimized due to the reduced number of stages and transistors. In addition, the prescaler operating speed was also improved due to a reduced critical path. We compared the simulation results with conventional E-TSPC based divide-by-3/4 dividers in the same process, where the figure-of-merit (FoM) of the proposed divider was 17.4–75.5% better than conventional ones. We have also fabricated the prescaler in a 40 nm complementary metal oxide semiconductor (CMOS) process. The measured highest operating frequency was 9 GHz with 0.303 mW power consumption under 1.35 V power supply, which agrees with the simulation well. The measurement results demonstrate that the proposed divider achieves high-speed and low-power operation.

APA, Harvard, Vancouver, ISO, and other styles

12

Wu, Li Fan. "A 36 GHz CIFF-TFF Dynamic Frequency Divider Using GaAs HBTs." Applied Mechanics and Materials 441 (December 2013): 125–28. http://dx.doi.org/10.4028/www.scientific.net/amm.441.125.

Full text

Abstract:

A clock-inverter feed-forward toggle flip-flop (CIFF-TFF) based ultra-high-speed 2:1 dynamic frequency divider is designed in a GaAs heterojunction bipolar transistor (HBT) technology with fT of 60 GHz from Win Semiconductors corporation. The co-simulation methodology of electromagnetic field and schematic diagram is utilized in the design. Through tuning the currents in the core and the other parts of the divider separately, the dynamic frequency divider approaches an operating speed of 36 GHz with a power consumption of 162 mW in the core part from a single 6 V supply. The design is currently taped out.

APA, Harvard, Vancouver, ISO, and other styles

13

Zhao, Yunrui, Zhiming Chen, Zicheng Liu, Xiaoran Li, and Xinghua Wang. "A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer." Electronics 9, no. 11 (October 26, 2020): 1773. http://dx.doi.org/10.3390/electronics9111773.

Full text

Abstract:

High speed divider is highly desired in the millimeter wave (mmW) frequency synthesizer design. A high operating frequency, low power consumption 90-nm CMOS programmable pulse swallow multi-modulus-divider is presented in this paper. High speed true-single-phase-clock D-flip-flop (TSPC DFF) is used in the counter in order to obtain a high operating frequency. It can operate at a frequency range from 4.1 GHz to 9.2 GHz, with a division ratio of 101–164. It has a power efficiency of 3.1 GHz/mW, and it can be used to provide a high quality reference frequency in the mmW phase-locked loop.

APA, Harvard, Vancouver, ISO, and other styles

14

Jurgo, Marijan, and Romualdas Navickas. "Design of Gigahertz Tuning Range 5 GHz LC Digitally Controlled Oscillator in 0.18 μm CMOS." Journal of Electrical Engineering 67, no. 2 (April 1, 2016): 143–48. http://dx.doi.org/10.1515/jee-2016-0020.

Full text

Abstract:

Abstract In this paper design and simulation of a 4.3 - 5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18 μm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fine frequency tuning. Coarse and fine tuning switched capacitor arrays are controlled using 6-bit and 3-bit binary words. To increase available frequency values, frequency divider is used. Structure of frequency divider is based on extended-true-single-phase-clock flip-flops. Divider is made of eight divide-by-2 cells connected in daisy chain, thus division values from 2 to 256 are available. Wide tuning range and high division values allows using such DCO with frequency divider in multi-standart transceivers. Whole device is supplied from a single 1.8 V voltage source. At highest frequency proposed device draws 90 mA current including all buffers. Phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier. Designed dual DCO and frequency divider occupies about 0.4mm×0.5mm of chip space and whole chip, including pads, occupies 1.5mm × 1.5mm area of silicon.

APA, Harvard, Vancouver, ISO, and other styles

15

Fujimoto, Kuniaki, Mitsutoshi Yahara, and Hirofumi Sasaki. "A Dividing Ratio Changeable Digital PLL with Low Jitter Using a Multiphase Clock Divider." IEEJ Transactions on Electronics, Information and Systems 129, no. 3 (2009): 399–405. http://dx.doi.org/10.1541/ieejeiss.129.399.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Fujimoto, Kuniaki, Mitsutoshi Yahara, and Hirofumi Sasaki. "A dividing ratio changeable digital PLL with low jitter using a multiphase clock divider." Electronics and Communications in Japan 94, no. 11 (October 21, 2011): 55–62. http://dx.doi.org/10.1002/ecj.10340.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Lee, T. C., and Y. C. Huang. "The Design and Analysis of a Miller-Divider-Based Clock Generator for MBOA-UWB Application." IEEE Journal of Solid-State Circuits 41, no. 6 (June 2006): 1253–61. http://dx.doi.org/10.1109/jssc.2006.874279.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Yahara, Mitsutoshi, Kuniaki Fujimoto, and Hideo Kiyota. "Multiple-frequency digital phase-locked loop based on multiphase clock divider with constant pulse interval." Electronics and Communications in Japan 101, no. 7 (May 17, 2018): 40–47. http://dx.doi.org/10.1002/ecj.12085.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

WURZER, MARTIN, THOMAS F. MEISTER, JOSEF BÖCK, HERBERT SCHÄFER, KLAUS AUFINGER, SABINE BOGUTH, HERBERT KNAPP, MIRJANA REST, RENATE SCHREITER, and LUDWIG TREITINGER. "HIGH-PERFORMANCE Si and SiGe BIPOLAR TECHNOLOGIES AND CIRCUITS." International Journal of High Speed Electronics and Systems 11, no. 01 (March 2001): 35–76. http://dx.doi.org/10.1142/s0129156401000782.

Full text

Abstract:

In this paper we present Si and SiGe bipolar technologies and circuits suited for present and future high-performance communication systems. The silicon bipolar technology described has an implanted base and, without increase in process complexity in comparison to current production technologies, transit frequencies of 52 GHz and maximum oscillation frequencies of 65 GHz are achieved. The transistors of the described epitaxial SiGe-base technologies exhibit transit frequencies of 81 GHz and maximum oscillation frequencies of 95 GHz. Measurement results of circuits realized in these technologies for low power and high-speed applications are presented: a 43 GHz low power dynamic frequency divider, a 23 GHz monolithically integrated oscillator, a 40 Gb/s clock and data (CDR) recovery realized in the pure silicon bipolar technology, and a 53 GHz static frequency divider, a 79 GHz dynamic frequency divider and a 20 GHz/27 mW dual-modulus prescaler in the SiGe technology.

APA, Harvard, Vancouver, ISO, and other styles

20

Yahara, Mitsutoshi, Kuniaki Fujimoto, and Hideo Kiyota. "Multiple Frequency Digital Phase-Locked Loop Based on Multi-Phase Clock Divider with Constant Pulse Interval." IEEJ Transactions on Electronics, Information and Systems 138, no. 4 (2018): 387–94. http://dx.doi.org/10.1541/ieejeiss.138.387.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Gupta, Mangal D., and Rajeev K. Chauhan. "Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA." IET Computers & Digital Techniques 15, no. 5 (April 4, 2021): 349–61. http://dx.doi.org/10.1049/cdt2.12027.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Shakir, Muhammad, Shuo Ben Hou, and Carl Mikael Zetterling. "A Monolithic 500°C D-Flip Flop Realized in Bipolar 4H-SiC TTL Technology." Materials Science Forum 963 (July 2019): 818–22. http://dx.doi.org/10.4028/www.scientific.net/msf.963.818.

Full text

Abstract:

This work presents the design, in-house fabrication, and electrical characterization of a monolithic medium scale integrated (MSI) D-type flip-flop (DFF). It consists of 65 n-p-n bipolar transistors and 49 integrated resistors. The monolithic bipolar DFF is realized using basic gates by employing the structured way of implementation, whereas the basic gates are implemented by employing the conventional transistor-transistor logic (TTL). The positive-edge-triggered DFF, with synchronous active-low reset is characterized in the temperature range of 25-500 °C. The circuit has been tested in two modes of operation; data input mode and clock divider. Non-monotonous temperature dependence is observed for the flip-flop propagation-delay clock-to-output (tPCQ), rise-time and fall-time; decreases with the temperature in the range 25 °C to 300 °C, while it increases in the range 300 °C to 500 °C. The transient response has also been measured at a clock frequency of 100 kHz. At T = 400 °C and VCC = 15 V, the DFF consumes minimum energy ≈ 234 nJ.

APA, Harvard, Vancouver, ISO, and other styles

23

Yuan, Hengzhou, Yang Guo, Jianjun Chen, Yaqing Chi, Xi Chen, and Bin Liang. "28nm Fault-Tolerant Hardening-by-Design Frequency Divider for Reducing Soft Errors in Clock and Data Recovery." IEEE Access 7 (2019): 47955–61. http://dx.doi.org/10.1109/access.2019.2906884.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Zhang, Mingjiang, Tiegen Liu, Anbang Wang, Jianzhong Zhang, and Yuncai Wang. "All-optical clock frequency divider using Fabry–Perot laser diode based on the dynamical period-one oscillation." Optics Communications 284, no. 5 (March 2011): 1289–94. http://dx.doi.org/10.1016/j.optcom.2010.10.071.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Yahara, Mitsutoshi, Kuniaki Fujimoto, and Hideo Kiyota. "A Study of 1+n/k Frequency Divider Based on Multi-Phase Clock." IEEJ Transactions on Electronics, Information and Systems 138, no. 8 (August 1, 2018): 1060–61. http://dx.doi.org/10.1541/ieejeiss.138.1060.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Macaitis, Vytautas, and Romualdas Navickas. "Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems." Electronics 8, no. 1 (January 8, 2019): 72. http://dx.doi.org/10.3390/electronics8010072.

Full text

Abstract:

This paper presents the design, simulation, and measurements of a low power, low phase noise 10.25–11.78 GHz LC digitally controlled oscillator (LC DCO) with extended true single phase clock (E-TSPC) frequency divider in 130 nm complementary metal–oxide–semiconductor (CMOS) technology for 5G intelligent transport systems. The main goal of this work was to design the LC DCO using a mature and low-cost 130 nm CMOS technology. The designed integrated circuit (IC) consisted of two parts: the LC DCO frequency generation and division circuit and an independent frequency divider testing circuit. The proposed LC DCO consisted of the following main blocks: the high Q-factor inductor, switched-capacitors block, cross-coupled transistors, and the current control block. Inductors with switched-capacitors block formed an LC tank. The designed E-TSPC frequency divider consisted of eight blocks connected in a series; each block increased the division ratio by a factor of two. The frequency of the input signal was divided in the region from two to 256 times using the designed divider. The main parameters of the designed E-TSPC divider and the LC DCO measurements were given as follows: LC DCO achieved a wide tuning range from 10.25 GHz to 11.78 GHz (1.53 GHz, 15.28% bandwidth); phase noise at 1 MHz offset frequency from LC DCO lowest carrier frequency was −113.42 dBc/Hz; phase noise at 1 MHz offset frequency from LC DCO highest carrier frequency was −110.51 dBc/Hz; The average power consumption of the designed LC DCO core and E-TSPC divider were 10.02 mW and 97.52 mW, respectively; the figure of merit (FOM) and the extended FOMT values of the proposed LC DCO were −183.52 dBc/Hz and −187.20 dBc/Hz, respectively. These FOM and FOMT results were achieved due to very low phase noise (−113.52 dBc/Hz) and a wide frequency tuning range (15.28%). The total layout area including the pads was 1.5 mm × 1.5 mm, with the largest part of the layout occupied by the proposed LC DCO (193 µm × 311 µm). The largest part of the LC DCO was occupied by the inductor 184 µm × 184 µm. The manufactured chip was packed into a quad flat no-leads (QFN) 20 pads package.

APA, Harvard, Vancouver, ISO, and other styles

27

Yahara, Mitsutoshi, and Kuniaki Fujimoto. "A 1+n/k Frequency Divider Unrelated to Duty Ratio of Multi-Phase Clock." IEEJ Transactions on Electronics, Information and Systems 139, no. 7 (July 1, 2019): 843–44. http://dx.doi.org/10.1541/ieejeiss.139.843.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Wu, Xiushan, Yanzhi Wang, Siguang An, Jianqiang Han, and Ling Sun. "A Four Quadrature Signals’ Generator with Precise Phase Adjustment." Journal of Electrical and Computer Engineering 2016 (2016): 1–6. http://dx.doi.org/10.1155/2016/2138794.

Full text

Abstract:

A four-way quadrature signals generator with precise phase modulation is presented. It consists of a phase precision regulator and a frequency divider. The phase precision regulator generates two programmable currents by controlling the conduction of the tail current sources and then changes the currents into two bias voltages which are superimposed on the clock signals to adjust the phase difference of the four quadrature signals generated by the frequency divider, making the phase difference of 90 degrees. The four quadrature signals’ generator with precise phase modulation has been implemented in a 0.18 μm mixed-signal and RF 1P6M CMOS technology. The size of the chip including the pads is675 μm⁎690 μm. The circuit uses a supply voltage of 1.8 V, a bias current of 7.2 μA, and the bits of phase-setting input leveln=6in the design. The measured results of the four orthogonal signals’ phase error can reach ±0.1°, and the phase modulation range can reach ±3.6°.

APA, Harvard, Vancouver, ISO, and other styles

29

A.M. Alias, M. N., S. N. Mohyar, M. N. Isa, A. Harun, A. B. Jambek, and S. A. Z. Murad. "Design and analysis of dedicated real-time clock for customized microcontroller unit." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (May 1, 2019): 796. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp796-801.

Full text

Abstract:

<span>In this paper, a Real Time Clock (RTC) system for a dedicated microcontroller is proposed to provide the customized microcontroller its own time and date system. The RTC is developed using Verilog Hardware Description Language (HDL) and simulated using Synopsys software. This RTC is developed with standard Advance Peripheral Bus (APB) to be interfacing with the microcontroller through Advanced Microcontroller Bus Architecture (AMBA). This RTC will be used as an on-chip RTC in the microcontroller system to provide precise time and date which can be used for various applications. The basic architecture of RTC, APB standard for interfacing the RTC with AMBA bus, and the result in term of RTL, waveform, and layout will be discussed in this documentation. For this research, the part covered is on the logic part of the RTC that is bus interface, register, frequency divider and counter.</span>

APA, Harvard, Vancouver, ISO, and other styles

30

Rea, Richard. "Configurable Digital Logic for Extreme Environments." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (May 1, 2018): 000098–102. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000098.

Full text

Abstract:

Abstract This paper presents a multiple-configuration IC that implements a number of sequential or combinatorial logic functions for extreme environment electronics. Operating temperature is −55°C to +300°C. Combinatorial functions include AND, OR, XOR, muxes, bi-directional transceiver, priority-encoder, magnitude comparator, etc. Sequential functions include 8-bit DFF, counter, latch, programmable clock-divider, etc. The majority of 7400 logic parts are covered by this part. Special test circuitry is included for in-situ monitoring of the part during production. Endurance testing and monitoring of part lifetime at elevated stress temperature (+350°C) is also built-in.

APA, Harvard, Vancouver, ISO, and other styles

31

GUTIERREZ-AITKEN, AUGUSTO L., ERIC N. KANESHIRO, JAMES H. MATSUI, DONALD J. SAWDAI, JOHANNES K. NOTTHOFF, PATRICK T. CHIN, and AARON K. OKI. "CANTILEVERED BASE InP DHBT FOR HIGH SPEED DIGITAL APPLICATIONS." International Journal of High Speed Electronics and Systems 11, no. 01 (March 2001): 245–56. http://dx.doi.org/10.1142/s0129156401000848.

Full text

Abstract:

High speed digital logic is essential in diverse applications such as optical communication, frequency synthesizers, and analog-digital conversion. Current research efforts indicate that technologies utilizing heterojunction bipolar transistors (HBT) are the preferred approach for systems operating at clock frequencies of 40 GHz and above (1-6). In this paper we report a novel InAIAs/InGaAs/InP double-HBT (DHBT) with a cantilevered base layer and undercut collector. We fabricated and demonstrated an 80 GHz 2:1 digital frequency divider, and a 5 GHz 8-bit phase/7-bit magnitude Direct Digital Synthesizer (DDS) chip with approximately 3000 transistors using this technology.

APA, Harvard, Vancouver, ISO, and other styles

32

Yao, Fang Fang, Xiao Jing Zhang, Zhi Qiang Gao, and Xiao Wei Liu. "Design of Charge Pump for Inertial Sensor Drive Circuit." Key Engineering Materials 609-610 (April 2014): 942–51. http://dx.doi.org/10.4028/www.scientific.net/kem.609-610.942.

Full text

Abstract:

A transistor-level circuit design of charge pump is introduced to drive the inertial device. The design is made of several big modules, including main charge pump module, band gap reference module, comparator module, oscillating module, control module, temperature protection module. A three-stage charge pump is applied to achieve 5 V to 18 V DC/DC conversion, and each stage uses the cross coupled charge pump circuit, taking body effect, threshold voltage drop and efficiency into account. Considering efficiency and power consumption, the band gap reference module adopts a self-biased op amp. To make the comparator transient response fast, the op amp cascades two inverters. The temperature protection module sets a maximum temperature to protect the charge pump. The control module is composed of a data selector, a two-phase non-overlap clock circuit and a frequency divider to optimize clock signal. Then simulations are given and the charge pump is analyzed, finally the efficiency of charge pump is calculated. Designed in CSMC 0.5um process, the charge pump has an efficiency of 87.63 percent, a 19.85V output voltage, a 100 mA output current, and 6.05mV ripple.

APA, Harvard, Vancouver, ISO, and other styles

33

Pankratov, E. L. "On Approach to Optimize Manufacturing of a Frequency Divider Using True Single-Phase Clock to Increase Integration Rate of Their Elements." Advanced Science, Engineering and Medicine 9, no. 7 (July 1, 2017): 552–67. http://dx.doi.org/10.1166/asem.2017.2030.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Yahara, Mitsutoshi, Kuniaki Fujimoto, and Hideo Kiyota. "A Study of 1+n/k Frequency Divider Based on Multi-Phase Clock with Extended Division Ratio." IEEJ Transactions on Electronics, Information and Systems 138, no. 11 (November 1, 2018): 1451–52. http://dx.doi.org/10.1541/ieejeiss.138.1451.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Widmann, Daniel, Markus Grözing, and Manfred Berroth. "High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology." Advances in Radio Science 16 (September 4, 2018): 99–108. http://dx.doi.org/10.5194/ars-16-99-2018.

Full text

Abstract:

Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 bit 64 GS s−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 ps at the output of one MUX channel with a total average power consumption of approximately 1.15 W of the whole MUX and clock network.

APA, Harvard, Vancouver, ISO, and other styles

36

Wang, Kai Yu, Zhe Nan Tang, and Tao Ge. "The Design and Simulation of a CMOS Digital PLL." Applied Mechanics and Materials 48-49 (February 2011): 1227–30. http://dx.doi.org/10.4028/www.scientific.net/amm.48-49.1227.

Full text

Abstract:

In this paper, the charge-pump PLL structure is well analyzed. By using top-down method, the digital PLL is designed from frequency phase detector, charge pump, loop filter, VCO to frequency divider. Based on 0.5μm CMOS mixed signal process, the schematic and layout design is finished on Cadence IC 5.1.4.1, and Hspice is used for the simulation. The layout verification and parasitic extraction is completed on industry mainstream Calibre software. Simulation results show that the digital PLL is with a 100MHz center frequency, the locking range is between 20MHz~60MHz, the locking time is less than 1.5μs, and phase noise is -105dBc/Hz. The design has implemented the digital signal lock function and it can be used as an IP hard core in the clock recovery of communication systems and frequency synthesis of digital systems.

APA, Harvard, Vancouver, ISO, and other styles

37

LAO, Z., M. LANG, V. HURM, Z. WANG, A. THIEDE, M. SCHLECHTWEG, W. BRONNER, et al. "20–40 Gbit/s GaAs-HEMT CHIP SET FOR OPTICAL DATA RECEIVER." International Journal of High Speed Electronics and Systems 09, no. 02 (June 1998): 437–72. http://dx.doi.org/10.1142/s0129156498000208.

Full text

Abstract:

Using our 0.2 and 0.3 μm AlGaAs/GaAs/AlGaAs quantum well HEMT technology, we have developed a chip set for 20–40 Gbit/s fiber-optical digital transmission systems. In this paper we describe nine analog and digital receiver ICs: a 22 GHz high-gain transimpedance amplifier, a 20 Gbit/s OEIC front-end optical receiver, a 25 Gbit/s automatic-gain-control amplifier, a limiting amplifier with a differential gain of 26 dB and a bandwidth of 27.7 GHz, a 20–40 Gbit/s clock recovery, a 20 Gbit/s low-power Master-Slave-D-Flipflop with 24 mW power dissipation, a parallel data decision and a 1:4 demultiplexer, both for bit rates of 40 Gbit/s, and a 30 GHz static frequency divider, respectively. All chips were characterized on wafers with 50 Ω coplanar test probes.

APA, Harvard, Vancouver, ISO, and other styles

38

Chen, Chao, Shengwei Meng, Zhenghuan Xia, Guangyou Fang, and Hejun Yin. "An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement." Journal of Electrical and Computer Engineering 2014 (2014): 1–5. http://dx.doi.org/10.1155/2014/230803.

Full text

Abstract:

We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL). The configuration, which consists of a ring oscillator, a frequency divider (FD), and a period measurement circuit (PMC), is implemented in a field programmable gate array (FPGA) device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT) generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

APA, Harvard, Vancouver, ISO, and other styles

39

Wang, Z. G., M. Berroth, A. Thiede, M. Rieger-Motzer, P. Hofmann, A. Hülsmann, K. Köhler, B. Raynor, and J. Schneider. "40 and 20 Gbit/s monolithic integrated clock recovery using a fully-balanced narrowband regenerative frequency divider with 0.2 [micro sign]m AlGaAs/GaAs HEMTs." Electronics Letters 32, no. 22 (1996): 2081. http://dx.doi.org/10.1049/el:19961363.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Wan, Meilin, Zhenzhen Zhang, Wang Liao, Kui Dai, and Xuecheng Zou. "A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks." Journal of Circuits, Systems and Computers 24, no. 07 (June 17, 2015): 1550109. http://dx.doi.org/10.1142/s0218126615501091.

Full text

Abstract:

A dual-modulus prescaler (divide-by-2/3) using complementary clocking NMOS-like blocks is presented in this paper. The prescaler can work properly for both differential and single phase input clocks. For differential input clocks, the prescaler achieves not only high operating frequency but also low power consumption since it consists of only five NMOS-like blocks. For single phase input clock, the operating frequency range is further expanded by utilizing a complementary clocks generator. Simulation results show that, in 180-nm standard CMOS technology, the proposed prescaler achieves operating frequency range of 1.7–9.0 GHz for differential input clocks and 0.5–10.2 GHz for single phase input clock. And the maximum power consumption from 1.8 V power supply is 0.92 mW and 1.32 mW for differential and single phase input clocks respectively.

APA, Harvard, Vancouver, ISO, and other styles

41

Huynh, Hai Au, Hak-Tae Lee, Wansoo Nah, and SoYoung Kim. "Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods." International Journal of Antennas and Propagation 2015 (2015): 1–11. http://dx.doi.org/10.1155/2015/497647.

Full text

Abstract:

Direct power injection (DPI) and bulk current injection (BCI) methods are defined in IEC 62132-3 and IEC 62132-4 as the electromagnetic immunity test method of integrated circuits (IC). The forward power measured at the RF noise generator when the IC malfunctions is used as the measure of immunity level of the IC. However, the actual power that causes failure in ICs is different from forward power measured at the noise source. Power transfer efficiency is used as a measure of power loss of the noise injection path. In this paper, the power transfer efficiencies of DPI and BCI methods are derived and validated experimentally with immunity test setup of a clock divider IC. Power transfer efficiency varies significantly over the frequency range as a function of the test method used and the IC input impedance. For the frequency range of 15 kHz to 1 GHz, power transfer efficiency of the BCI test was constantly higher than that of the DPI test. In the DPI test, power transfer efficiency is particularly low in the lower test frequency range up to 10 MHz. When performing the IC immunity tests following the standards, these characteristics of the test methods need to be considered.

APA, Harvard, Vancouver, ISO, and other styles

42

Ren, Guanshen. "Delving Deeper: One Cut, Two Halves, Three Questions." Mathematics Teacher 103, no. 4 (November 2009): 305–9. http://dx.doi.org/10.5951/mt.103.4.0305.

Full text

Abstract:

The popular radio show Car Talk, hosted by Click and Clack, the Tappet brothers, features a weekly puzzler. One week the puzzler asked how to divide a rectangular brownie into two equal halves with one cut. Audience members familiar with basic geometry knew that a cut along a diagonal of a rectangle will divide the rectangle into two equal parts. Click and Clack suggested that any cut through the center of the rectangle, the intersection point of two diagonals, would also work. Why?

APA, Harvard, Vancouver, ISO, and other styles

43

Ren, Guanshen. "Delving Deeper: One Cut, Two Halves, Three Questions." Mathematics Teacher 103, no. 4 (November 2009): 305–9. http://dx.doi.org/10.5951/mt.103.4.0305.

Full text

Abstract:

The popular radio show Car Talk, hosted by Click and Clack, the Tappet brothers, features a weekly puzzler. One week the puzzler asked how to divide a rectangular brownie into two equal halves with one cut. Audience members familiar with basic geometry knew that a cut along a diagonal of a rectangle will divide the rectangle into two equal parts. Click and Clack suggested that any cut through the center of the rectangle, the intersection point of two diagonals, would also work. Why?

APA, Harvard, Vancouver, ISO, and other styles

44

Bondarescu, Ruxandra, Andreas Schärer, Andrew Lundgren, György Hetényi, Nicolas Houlié, Philippe Jetzer, and Mihai Bondarescu. "Ground-based optical atomic clocks as a tool to monitor vertical surface motion." Geophysical Journal International 202, no. 3 (July 16, 2015): 1770–74. http://dx.doi.org/10.1093/gji/ggv246.

Full text

Abstract:

Abstract According to general relativity, a clock experiencing a shift in the gravitational potential ΔU will measure a frequency change given by Δf/f ≈ ΔU/c2. The best clocks are optical clocks. After about 7 hr of integration they reach stabilities of Δf/f ∼ 10−18 and can be used to detect changes in the gravitational potential that correspond to vertical displacements of the centimetre level. At this level of performance, ground-based atomic clock networks emerge as a tool that is complementary to existing technology for monitoring a wide range of geophysical processes by directly measuring changes in the gravitational potential. Vertical changes of the clock's position due to magmatic, post-seismic or tidal deformations can result in measurable variations in the clock tick rate. We illustrate the geopotential change arising due to an inflating magma chamber using the Mogi model and apply it to the Etna volcano. Its effect on an observer on the Earth's surface can be divided into two different terms: one purely due to uplift (free-air gradient) and one due to the redistribution of matter. Thus, with the centimetre-level precision of current clocks it is already possible to monitor volcanoes. The matter redistribution term is estimated to be 3 orders of magnitude smaller than the uplift term. Additionally, clocks can be compared over distances of thousands of kilometres over short periods of time, which improves our ability to monitor periodic effects with long wavelength like the solid Earth tide.

APA, Harvard, Vancouver, ISO, and other styles

45

Ben Issa, Dalenda, and Mounir Samet. "Design and Optimization of Dual-Band Energy-Efficient OOK UWB Transmitter Via PSO Algorithm." Journal of Circuits, Systems and Computers 29, no. 11 (January 15, 2020): 2030009. http://dx.doi.org/10.1142/s0218126620300093.

Full text

Abstract:

A CMOS ON–OFF-keying 3–10.6-GHz transmitter with low power consumption and low complexity used to Impulse Radio Ultra-Wide Band (IR-UWB) communication system is presented in this work. This architecture is designed and optimized via particle swarm optimization (PSO) algorithm. The IR-UWB transmitter is adapted to generate a high bandwidth frequency and it has a band switching capability. It consists of a switching inductance–capacitance voltage-controlled oscillator (LC_VCO), a pulse generator circuit, an injection-locked frequency divider (ILFD) circuit, a buffer and an antenna. The VCO is switched ON/OFF by the pulse signal produced by a generator circuit which is realized through synchronizing the received data by a clock signal. The used technique for transmitting a discontinuous signal is based on a complementary switch-mode ON–OFF LC_VCO, whose main advantage is to reduce power consumption. In this work, a best agreement between the results of the optimization technique and those of the simulation is obtained. The simulated results illustrate a signal of pulse width of 2.5 ns and a pulse repetition rate (PRR) of 200 MHz. The output spectra are centered at 4-GHz and 8-GHz frequencies with 1,332-MHz and 1,350-MHz bandwidths, respectively. The peak-to-peak amplitude of a UWB signal output is 154[Formula: see text]mV. The IR-UWB transmitter power consumption is 11.4[Formula: see text]mW which corresponds to the consumption energy of 28.5 pJ/pulse @ 200[Formula: see text]MHz. The power spectral densities (PSDs) of the output signals of both circuits viz. ON–OFF LC_VCO and ILFD are less than [Formula: see text][Formula: see text]dBm/MHz, which agreed well with the Federal Communication Commission (FCC) regulation. The transmitter design is well implemented using a TSMC 0.18-[Formula: see text]m CMOS process technology in an Advanced Design System (ADS).

APA, Harvard, Vancouver, ISO, and other styles

46

Miranda, Jonatan, María P. Portillo, Juan Antonio Madrid, Noemí Arias, M. Terasa Macarulla, and Marta Garaulet. "Effects of resveratrol on changes induced by high-fat feeding on clock genes in rats." British Journal of Nutrition 110, no. 8 (March 28, 2013): 1421–28. http://dx.doi.org/10.1017/s0007114513000755.

Full text

Abstract:

In mammals, the main component of the circadian system is the suprachiasmatic nucleus in the hypothalamus. However, circadian clocks are also present in most peripheral tissues, such as adipose tissue. The aim of the present study was to analyse the potential effects of resveratrol on changes induced by high-fat feeding in the expression of clock genes and clock-controlled genes in the white adipose tissue from rats. For this purpose, rats were divided into three groups: a control group, fed a standard diet, and two other groups, either fed a high-fat diet supplemented with resveratrol (RSV) or no resveratrol (HF). The expression of clock genes and clock-controlled genes was analysed by RT-PCR. Protein expression and fatty acid synthase (FAS) activity were also analysed. When comparing the controls, the RSV group showed similar patterns of response to the HF group, except for reverse erythroblastosis virus α (Rev-Erbα), which was down-regulated. The expression of this gene reached the same levels as in control rats. The response pattern of protein expression forRev-Erbαwas similar to that found for gene expression. High-fat feeding up-regulated all adipogenic genes and resveratrol did not modify them. In the HF group, the activity of FAS tended to increase, while resveratrol decreased. In conclusion, resveratrol reverses the change induced by high-fat feeding in the expression ofRev-Erbαin adipose tissue, which means that clock machinery is a target for this polyphenol. This change seems to be related to reduced lipogenesis, which might be involved in the body fat-lowering effect of this molecule.

APA, Harvard, Vancouver, ISO, and other styles

47

Gabryelska, A., M. Sochal, and P. Bialasiewicz. "0059 Disruption of Circadian Clock Proteins in Obstructive Sleep Apnea Patients." Sleep 43, Supplement_1 (April 2020): A23—A24. http://dx.doi.org/10.1093/sleep/zsaa056.057.

Full text

Abstract:

Abstract Introduction Circadian clocks are endogenous coordinators of 24-hour rhythm of behavioral and molecular processes in living organism. They are composed of set of genes, which function as activators - CLOCK and BMAL1, which through binding to regulatory elements containing E-boxes activate transcription of repressor proteins Period (PER1) and cryptochrome (CRY1). The aim of the study was to assess: CLOCK, BMAL1, PER1 and CRY1 in obstructive sleep apnea (OSA) patients. Methods The study included 20 individuals, who underwent PSG and based on apnea-hypopnea index (AHI) were divided into severe OSA group (n=10; AHI30; 90% male) and healthy control (n=10; AHI<5; 70% male). All participants had their peripheral blood collected in the evening (9:00-10:00 pm) before and in the morning (6:00-7:00 am) after the PSG. CLOCK, BMAL1, CRY1 and PER1 protein concertation measurements were performed using ELISA. Results Increased level of following proteins was observed in OSA group: evening CLOCK (p=0.037), morning CLOCK (p=0.019), morning BMAL1 (p=0.0.16), evening PER1 (p=0.004), morning PER1 (p=0.029) and evening CRY1 (p=0.035). Yet, no significant difference was found between morning and evening level of any of the proteins in OSA and control group. Additionally, morning level of activator proteins CLOCK and BMAL1 had positive correlation with AHI (p=0.022, R=0.510 and p=0.010, R=0.560, respectively) and desaturation index (p=0.209, R=0.487 and p=0.009, R=0.570, respectively), while for repressor proteins PER1 and CRY1 significant correlations were found with desaturation index in the evening (p=0.025, R=0.500 and p=0.048, R=0.448, respectively), AHI in REM stage (p=0.009, R=0.569 and p=0.027, R=0.495, respectively) and AHI (for PER1 only p=0.014, R=0.540). Conclusion OSA patients have increased level of circadian clock proteins that corelates with severity of the disease. Further research is needed into the disruption of circadian clock should in OSA patients and possible effect of OSA treatment on concentrations of these proteins should be investigated. Support The study was financed by Polish National Centre Grant no. 2018/31/N/NZ5/03931.

APA, Harvard, Vancouver, ISO, and other styles

48

Harinarayan, Gautham S., and Avireni Srinivasulu. "Three Microwave Frequency Dividers Using Current Source/Sink and Modified Current Source Inverters." Active and Passive Electronic Components 2013 (2013): 1–11. http://dx.doi.org/10.1155/2013/762706.

Full text

Abstract:

In a preceding paper Carlos E. Saavedra, 2005, established that frequency division can be achieved with the use of inverter rings and transmission gates. In this paper, we suggest three modified circuits which obtain the similar function, namely, using Current Sink Inverter, Current Source Inverter, and Modified Current Source Inverter. The performances of the proposed circuits are examined using Cadence and the model parameters of a 45 nm CMOS process. The simulation results of the three circuits are presented and are compared. We also present the results of a simple but effective novel technique to reduce clock skew between real and complementary clock signals and the corresponding improvement achieved in maximum frequency of operation. One of the proposed circuits can operate at up to 8.2 GHz input while performing a divide-by-4 operation.

APA, Harvard, Vancouver, ISO, and other styles

49

Bourke, Timothy, Paul Jeanmaire, Basile Pesin, and Marc Pouzet. "Verified Lustre Normalization with Node Subsampling." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–25. http://dx.doi.org/10.1145/3477041.

Full text

Abstract:

Dataflow languages allow the specification of reactive systems by mutually recursive stream equations, functions, and boolean activation conditions called clocks. Lustre and Scade are dataflow languages for programming embedded systems. Dataflow programs are compiled by a succession of passes. This article focuses on the normalization pass which rewrites programs into the simpler form required for code generation. Vélus is a compiler from a normalized form of Lustre to CompCert’s Clight language. Its specification in the Coq interactive theorem prover includes an end-to-end correctness proof that the values prescribed by the dataflow semantics of source programs are produced by executions of generated assembly code. We describe how to extend Vélus with a normalization pass and to allow subsampled node inputs and outputs. We propose semantic definitions for the unrestricted language, divide normalization into three steps to facilitate proofs, adapt the clock type system to handle richer node definitions, and extend the end-to-end correctness theorem to incorporate the new features. The proofs require reasoning about the relation between static clock annotations and the presence and absence of values in the dynamic semantics. The generalization of node inputs requires adding a compiler pass to ensure the initialization of variables passed in function calls.

APA, Harvard, Vancouver, ISO, and other styles

50

Hughes, Barry D. "Watching the Internal Clock of Cells while They Move and Divide." Biophysical Journal 114, no. 5 (March 2018): 1007–8. http://dx.doi.org/10.1016/j.bpj.2018.02.001.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!