Relevant bibliographies by topics / Clock network design

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Clock network design'

Author: Grafiati
Published: 4 June 2021
Last updated: 3 February 2022

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Journal articles on the topic "Clock network design"

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Vaisband, Inna, Eby G. Friedman, Ran Ginosar, and Avinoam Kolodny. "Low Power Clock Network Design." Journal of Low Power Electronics and Applications 1, no. 1 (May 19, 2011): 219–46. http://dx.doi.org/10.3390/jlpea1010219.

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Wu, P. B. "High-Speed Clock Network Design." IEEE Circuits and Devices Magazine 20, no. 5 (September 2004): 36. http://dx.doi.org/10.1109/mcd.2004.1343250.

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KAO, CHI-CHOU. "A HIGH FLEXIBILITY DESIGN FOR CLOCK DISTRIBUTION NETWORK IN SYSTEM ON CHIP." Journal of Circuits, Systems and Computers 16, no. 01 (February 2007): 51–63. http://dx.doi.org/10.1142/s0218126607003484.

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The idea of combining high-speed digital cores, memory arrays, analog blocks, and communication circuitry onto a single chip has led to a whole new design era of System on Chips (SoCs). The clock distribution network is one of the important issues in SoCs that consumes a significant portion of the total performance. In this paper, a flexible capacitance is used to make the clock distribution network more flexible for designing the clock distribution network. Therefore, if some IP (intellectual property) cores are changed in the system, we do not need to redesign the overall clock distribution network. This new approach facilitates the clock timing and synchronization of IPs so that IPs can be inserted or removed from the distribution network without affecting the whole performance of a SoC. This design uses efficiently the available resources and maintains clock signal integrity. The experimental results confirm the efficiency of the proposed design.
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Rand, D. A., B. V. Shulgin, D. Salazar, and A. J. Millar. "Design principles underlying circadian clocks." Journal of The Royal Society Interface 1, no. 1 (November 22, 2004): 119–30. http://dx.doi.org/10.1098/rsif.2004.0014.

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A fundamental problem for regulatory networks is to understand the relation between form and function: to uncover the underlying design principles of the network. Circadian clocks present a particularly interesting instance, as recent work has shown that they have complex structures involving multiple interconnected feedback loops with both positive and negative feedback. While several authors have speculated on the reasons for this, a convincing explanation is still lacking.We analyse both the flexibility of clock networks and the relationships between various desirable properties such as robust entrainment, temperature compensation, and stability to environmental variations and parameter fluctuations. We use this to argue that the complexity provides the flexibility necessary to simultaneously attain multiple key properties of circadian clocks. As part of our analysis we show how to quantify the key evolutionary aims using infinitesimal response curves, a tool that we believe will be of general utility in the analysis of regulatory networks. Our results suggest that regulatory and signalling networks might be much less flexible and of lower dimension than their apparent complexity would suggest.
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Ouyang, Yiming, Qi Chen, Xiumin Wang, Xiaoye Ouyang, Huaguo Liang, and Gaoming Du. "AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip." Journal of Circuits, Systems and Computers 25, no. 06 (March 31, 2016): 1650050. http://dx.doi.org/10.1142/s021812661650050x.

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Large scale synchronous network-on-chip (NoC) requires complex clock tree design, which leads to a large area overhead and power consumption. Based on handshaking protocols, asynchronous NoC does not have global clock tree distribution, which results in a natural power saving mode without any explicit clock gating. However, the faults occurring in such asynchronous networks will seriously affect their performances. In this paper, we propose AFTER, an Asynchronous Fault-TolErant Router, which uses the quasi delay insensitive (QDI) logic. The proposed router is able to detect the faults of ports and links. Then, a fault-tolerant routing mechanism, based on the port priority in different quadrants, is proposed to maximize the number of packets that can be transmitted via the shortest paths. In this way, the fault-tolerance of asynchronous routers can be achieved. Besides that, AFTER could also achieve high scalability, and is suitable for the large scale globally asynchronous locally synchronous (GALS) system. The experimental results show that, when faults occur in the network, AFTER has a better fault-tolerance performance than the reference.
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Schmidt, Albrecht. "Network alarm clock (The 3AD International Design Competition)." Personal and Ubiquitous Computing 10, no. 2-3 (December 13, 2005): 191–92. http://dx.doi.org/10.1007/s00779-005-0022-y.

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Neves, José Luis, and Eby G. Friedman. "Automated Synthesis of Skew-Based Clock Distribution Networks." VLSI Design 7, no. 1 (January 1, 1998): 31–57. http://dx.doi.org/10.1155/1998/72951.

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In this paper a top-down methodology is presented for synthesizing clock distribution networks based on application-dependent localized clock skew. The methodology is divided into four phases: 1) determination of an optimal clock skew schedule for improving circuit performance and reliability; 2) design of the topology of the clock tree based on the circuit hierarchy and minimum clock path delays; 3) design of circuit structures to implement the delay values associated with the branches of the clock tree; and 4) design of the geometric layout of the clock distribution network. Algorithms to determine an optimal clock skew schedule, the optimal clock delay to each register, the network topology, and the buffer circuit dimensions are presented.The clock distribution network is implemented at the circuit level in CMOS technology and a design strategy based on this technology is presented to implement the individual branch delays. The minimum number of inverters required to implement the branch delays is determined, while preserving the polarity of the clock signal. The clock lines are transformed from distributed resistive-capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. The inverters are specified by the geometric size of the transistors, the slope of the ramp shaped input/output waveform, and the output load capacitance. The branch delay model integrates an inverter delay model with an interconnect delay model. Maximum errors of less than 2.5% for the delay of the clock paths and 4% for the clock skew between any two registers belonging to the same global data path are obtained as compared with SPICE Level-3.
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Zhai, Yawei, Jaymin Patel, Xingqun Zhan, Mathieu Joerger, and Boris Pervan. "An Advanced Receiver Autonomous Integrity Monitoring (ARAIM) Ground Monitor Design to Estimate Satellite Orbits and Clocks." Journal of Navigation 73, no. 5 (April 28, 2020): 1087–105. http://dx.doi.org/10.1017/s0373463320000181.

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This paper describes a method to determine global navigation satellite systems (GNSS) satellite orbits and clocks for advanced receiver autonomous integrity monitoring (ARAIM). The orbit and clock estimates will be used as a reference truth to monitor signal-in-space integrity parameters of the ARAIM integrity support message (ISM). Unlike publicly available orbit and clock products, which aim to maximise estimation accuracy, a straightforward and transparent approach is employed to facilitate integrity evaluation. The proposed monitor is comprised of a worldwide network of sparsely distributed reference stations and will employ parametric satellite orbit models. Two separate analyses, covariance analysis and model fidelity evaluation, are carried out to assess the impact of measurement errors and orbit model uncertainty on the estimated orbits and clocks, respectively. The results indicate that a standard deviation of 30 cm can be achieved for the estimated orbit/clock error, which is adequate for ISM validation.
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Ravi, S., Suprovab Mandal, and Harish M. Kittur. "Design and Verification of High Performance Standard Cells for Clock Network Applications." Advanced Science Letters 24, no. 8 (August 1, 2018): 5877–83. http://dx.doi.org/10.1166/asl.2018.12213.

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Standard cell libraries are required by all CAD tools for chip planning. Standard cell libraries contain primitive cells required for advanced configuration. Be that as it may, more crucial cells that have been infrequently upgraded can likewise be incorporated. The principle reason for the CAD tools is to actualize the alleged RTL- to-GDS stream. Design and verification of standard cells (clock path) the advanced clock buffers and inverters present superior performance compared to the existed clock buffers and inverters. The RTL synthesis report shows that timing slack, numbers of inverters and power consumption have been reduced by 65.9%, 80.5% and 5.1% respectively.
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Li, Lei, and Jinmei Lai. "Design and implementation of clock network for nanometer FPGA." IEICE Electronics Express 12, no. 5 (2015): 20141180. http://dx.doi.org/10.1587/elex.12.20141180.

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Dissertations / Theses on the topic "Clock network design"

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Zhao, Xin. "Reliable clock and power delivery network design for three-dimensional integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45881.

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The main objective of this thesis is to design reliable clock-distribution networks and power-delivery networks for three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs). This dissertation supports this goal by addressing six research topics. The first four works focus on 3D clock tree synthesis for low power, pre-bond testability, TSV-induced obstacle avoidance, and TSV utilization. The last two works develop modeling approaches for reliability analysis on 3D power-delivery networks. In the first work, a clock synthesis algorithm is developed for low-power and low-slew 3D clock network design. The impact of various design parameters on clock performance, including the wirelength, clock power, clock slew, and skew, is investigated. These parameters cover the TSV count, TSV parasitics, the maximum loading capacitance of the clock buffers, and the supply voltage. In the second work, a clock synthesis algorithm is developed to construct 3D clock networks for both pre-bond testability and post-bond operability. Pre-bond testing of 3D stacked ICs involves testing each individual die before bonding, which can improve the overall yield of 3D ICs by avoiding stacking defective dies with good ones. Two key techniques including TSV-buffer insertion and redundant tree generation are implemented to minimize clock skew and ensure pre-bond testing. The impact of TSV utilization and TSV parasitics on clock power is also investigated. In the third work, an obstacle-aware clock tree synthesis method is presented for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground, and clock TSVs. These TSVs may occupy silicon area or routing layers. The generated clock tree does not sacrifice wirelength or clock power too much and avoids TSV-induced obstacles. In the fourth work, a decision-tree-based clock synthesis (DTCS) method is developed for low-power 3D clock network design, where TSVs form a regular 2D array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. The DTCS method explores the entire solution space for the best TSV array utilization in terms of low power. Close-to-optimal solutions can be found for power efficiency with skew minimization in short runtime. In the fifth work, current crowding and its impact on 3D power grid integrity is investigated. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. The current density distribution within a TSV and its connections to the global power grid is explored. A simple TSV model is implemented to obtain current density distributions within a TSV and its local environment. This model is checked for accuracy by comparing with identical models simulated using finite element modeling methods. The simple TSV models are integrated with the global power wires for detailed chip-scale power analysis. In the sixth work, a comprehensive multi-physics modeling approach is developed to analyze electromigration (EM) in TSV-based 3D connections. Since a TSV has regions of high current density, grain boundaries play a significant role in EM dominating atomic transport. The transient analysis is performed on atomic transport including grain and grain boundary structures. The evolution of atomic depletion and accumulation is simulated due to current crowding. And the TSV resistance change is modeled.
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Natu, Nitish Umesh. "Design and prototyping of temperature resilient clock distribution networks." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51812.

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Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of CDNs in terms of varying skew and propagation delay. This thesis presents two compensation techniques, Adaptive Voltage and Controllable Delay, to overcome these problems. The compensation methods are validated using a FPGA-based test vehicle. Modification in traditional buffer design are also presented and the performance as well as the area and power overhead of both the implementations is compared.
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Stieber, Marcel Colman Eric. "Radio Direction Finding Network Receiver Design for Low-cost Public Service Applications." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/889.

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A low-cost radio direction finding (RDF) VHF receiver has been investigated for development into a radio direction finding network (RDFN) with a particular focus towards public service and commercial asset tracking applications. The primary design criteria were reproducibility, low-cost, and simplicity such that public service and volunteer organizations can benefit from the technology. Two receiver designs were built and tested to allow for comparison of practicality, cost, and accuracy. A pseudo-Doppler RDF and a time difference of arrival (TDOA) receiver were built as proof-of-concept for a system design based on commercial off-the-shelf (COTS) components. The pseudo-Doppler system is a less practical implementation due to the necessity for custom hardware, a large antenna system, and an increased directional error due to multipath and weak signals. The TDOA system has potential as a very simple and low-cost RDFN implementation, but requires extremely accurate time synchronization that is difficult to achieve using COTS GPS receiver modules. The final proposed solution takes advantage of the simple TDOA hardware and multiple detection techniques (including signal strength) to produce improved locational data and ultimately provide a more accurate estimate of position. Further development and improvements to this receiver design have the potential for implementation as a low-cost radio direction finding network.
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Alimadadi, Mehdi. "Recycling clock network energy in high-performance digital designs using on-chip DC-DC converters." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/1447.

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Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.
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Li, Alan. "Design of a broadband PLL solution for burst-mode Clock and Data Recovery in all-optical networks." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=82612.

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All-Optical networks have been proposed as a solution to meet growing demand for broadband access. An essential component in these networks will be new Clock and Data Recovery devices which can recover burst-mode traffic. This a significantly different challenge from conventional, continuous-mode CDR. Burst-mode data originates at various sources and arrives at the receiver with different phases, potentially changing by +/-pi Rads. Therefore, new CDR designs are required to adapt to large steps in phase upon each new burst to maintain BER integrity. This must be accomplished on the order of ns if All-Optical networks are to be viable. While several such designs have been proposed, a clear solution has yet to emerge. This thesis proposes broadband PLLs as a new solution for burst-mode Clock and Data Recovery. The design of a completed broadband Phase-locked CDR ASIC is presented, from original device modeling to implementation and testing.
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Piluso, Susanna. "Design of biopolymer-based networks with defined molecular architecture." Phd thesis, Universität Potsdam, 2012. http://opus.kobv.de/ubp/volltexte/2012/5986/.

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In this work, the synthesis of biopolymer-based hydrogel networks with defined architecture is presented. In order to obtain materials with defined properties, the chemoselective copper-catalyzed azide-alkyne cycloaddition (or Click Chemistry) was used for the synthesis of gelatin-based hydrogels. Alkyne-functionalized gelatin was reacted with four different diazide crosslinkers above its sol-gel transition to suppress the formation of triple helices. By variation of the crosslinking density and the crosslinker flexibility, the swelling (Q: 150-470 vol.-%;) and the Young’s and shear moduli (E: 50 kPa - 635 kPa, G’: 0.1 kPa - 16 kPa) could be tuned in the kPa range. In order to understand the network structure, a method based on the labelling of free functional groups within the hydrogel was developed. Gelatin-based hydrogels were incubated with alkyne-functionalized fluorescein to detect the free azide groups, resulting from the formation of dangling chains. Gelatin hydrogels were also incubated with azido-functionalized fluorescein to check the presence of alkyne groups available for the attachment of bioactive molecules. By using confocal laser scanning microscopy and fluorescence spectroscopy, the amount of crosslinking, grafting and free alkyne groups could be determined. Dangling chains were observed in samples prepared by using an excess of crosslinker and also when using equimolar amounts of alkyne:azide. In the latter case the amount of dangling chains was affected by the crosslinker structure. Specifically, 0.1% of dangling chains were found using 4,4’-diazido-2,2’-stilbene-disulfonic acid as cosslinker, 0.06% with 1,8-diazidooctane, 0.05% with 1,12-diazidododecane and 0.022 % with PEG-diazide. This observation could be explained considering the structure of the crosslinkers. During network formation, the movements of the gelatin chains are restricted due to the formation of covalent netpoints. A further crosslinking will be possible only in the case of crosslinker that are flexible and long enough to reach another chain. The method used to obtain defined gelatin-based hydrogels enabled also the synthesis of hyaluronic acid-based hydrogels with tailorable properties. Alkyne-functionalized hyaluronic acid was crosslinked with three different linkers having two terminal azide functionalities. By variation of the crosslinking density and crosslinker type, hydrogels with elastic moduli in the range of 0.5-3 kPa have been prepared. The variation of the crosslinking density and crosslinker type had furthermore an influence also on the hydrolytic and enzymatic degradation of gelatin-based hydrogels. Hydrogels with a low crosslinker amount experienced a faster decrease in mass loss and elastic modulus compared to hydrogels with higher crosslinker content. Moreover, the structure of the crosslinker had a strong influence on the enzymatic degradation. Hydrogels containing a crosslinker with a rigid structure were much more resistant to enzymatic degradation than hydrogels containing a flexible crosslinker. During hydrolytic degradation, the hydrogel became softer while maintaining the same outer dimensions. These observations are in agreement with a bulk degradation mechanism, while the decrease in size of the hydrogels during enzymatic degradation suggested a surface erosion mechanism. Because of the use of small amount of crosslinker (0.002 mol.% 0.02 mol.%) the networks synthesized can still be defined as biopolymer-based hydrogels. However, they contain a small percentage of synthetic residues. Alternatively, a possible method to obtain biopolymer-based telechelics, which could be used as crosslinkers, was investigated. Gelatin-based fragments with defined molecular weight were obtained by controlled degradation of gelatin with hydroxylamine, due to its specific action on asparaginyl-glycine bonds. The reaction of gelatin with hydroxylamine resulted in fragments with molecular weights of 15, 25, 37, and 50 kDa (determined by SDS-PAGE) independently of the reaction time and conditions. Each of these fragments could be potentially used for the synthesis of hydrogels in which all components are biopolymer-based materials.
In dieser Arbeit wird die Synthese Biopolymer-basierter Hydrogelnetzwerke mit definierter Architektur beschrieben. Um Materialien mit definierten und einstellbaren Eigenschaften zu erhalten, wurde die chemoselektive Kupferkatalysierte Azid-Alkin-Cycloadditionsreaktion (auch als Click-Chemie bezeichnet) für die Synthese Gelatine-basierter Netzwerke eingesetzt. Alkin-funktionalisierte Gelatine wurde mit vier verschiedenen Diazid-Quervernetzern oberhalb der Gel-Sol-Übergangstemperatur umgesetzt, um die Formierung tripelhelikaler Bereiche durch Gelatineketten zu unterdrücken. Durch Variation der Menge an Quervernetzer (und damit der Netzdichte) sowie der Länge und Flexibilität der Quervernetzer konnten u.a. die Quellung (Q: 150-470 vol.-%) sowie der Young’s - und Schermodul im kPa Bereich eingestellt werden (E: 50 kPa - 635 kPa, G’: 0.1 kPa - 16 kPa). Um die Netzwerkarchitektur zu verstehen, wurde eine Methode basierend auf dem Labeln unreagierter Azid- und Alkingruppen im Hydrogel entwickelt. Die Gelatine-basierten Hydrogele wurden mit Alkin-funktionalisiertem Fluorescein umgesetzt, um freie Azidgruppen zu detektieren, die bei einem Grafting entstehen. Darüber hinaus wurden die Hydrogele mit Azid-funktionalisiertem Fluorescein reagiert, um die Menge an freien Alkingruppen zu bestimmen, die zudem potentiell für die Anbindung bioaktiver Moleküle geeignet sind. Quervernetzung, Grafting, und die Anzahl freier Alkingruppen konnten dann mit Hilfe der konfokalen Laser Scanning Mikroskopie und der Fluoreszenzmikroskopie qualitativ und quantitativ nachgewiesen werden. Gegraftete Ketten wurden in Systemen nachgewiesen, die mit einem Überschuss an Quervernetzer hergestellt wurden, entstanden aber auch beim Einsatz äquimolarer Mengen Alkin- und Azidgruppen. Im letzteren Fall wurde in Abhängigkeit von der Struktur des Diazids unterschiedliche Anteile gegrafteter Ketten festgestellt. 0.1 mol-% von gegrafteten Ketten wurden für 4,4’-Diazido-2,2’-stilbendisulfonsäure gefunden, 0.06 mol-% für 1,8-Diazidooktan, 0.05 mol% für 1,12-diazidododecan und 0.022 mol-% für PEG-Diazid. Diese Beobachtung kann durch die unterschiedliche Flexibilität der Vernetzer erklärt werden. Während der Netzwerkbildung werden die Bewegungen der Gelatineketten eingeschränkt, so dass kovalente Netzpunkte nur erhalten werden können, wenn der Vernetzer lang und flexibel genug ist, um eine andere Alkingruppe zu erreichen. Die Strategie zur Synthese von Biopolymer-basierten Hydrogelen mit einstellbaren Eigenschaften wurde von Gelatine- auf Hyaluronsäure-basierte Gele übertragen. Alkin-funktionalisierte Hyaluronäure wurde mit drei verschiedenen Diaziden quervernetzt, wobei Menge, Länge, und Flexibilität des Quervernetzers variiert wurden. In dieser Weise wurden sehr weiche Hydrogele mit E-Moduli im Bereich von 0.5-3 kPa hergestellt. Die Variation der Vernetzungsdichte und des Vernetzertyps beeinflusste weiterhin den hydrolytischen und enzymatischen Abbau der Hydrogele. Hydrogele mit einem geringerem Anteil an Quervernetzer wurden schneller abgebaut als solche mit einem höheren Quervernetzeranteil. Darüber hinaus konnte gezeigt werden, dass Hydrogele mit Quervernetzern mit einer rigiden Struktur deutlich langsamer degradierten als Hydrogele mit flexibleren Quervernetzern. Während des hydrolytischen Abbau wurden die Materialien weicher, behielten aber ihre Form bei, was mit einem Bulk-Abbau-Modell übereinstimmt. Während des enzymatischen Abbaus hingegen änderten sich die Materialeigenschaften kaum, jedoch wurden die Proben kleiner. Diese Beobachtung stimmt mit einem Oberflächenabbaumechanismus überein. Da in allen vorgestellten Systemen nur eine kleine Menge synthetischer Vernetzer eingesetzt wurde (0.002 – 0.02 mol%), können die Materialien noch als Biopolymer-basierte Materialien klassifiziert werden. Jedoch enthalten die Materialien synthetische Abschnitte. In Zukunft könnte es interessant sein, einen Zugang zu Materialien zu haben, die ausschließlich aus Biopolymeren aufgebaut sind. Daher wurde der Zugang zu Biopolymer basierten Telechelen untersucht, die potentiell als Vernetzer dienen können. Dazu wurden durch die kontrollierte Spaltung von Gelatine mit Hydroxylamin Gelatinefragmente mit definiertem Molekulargewicht hergestellt. Hydroxalamin reagiert unter Spaltung mit der Amidbindung zwischen Asparagin und Glycin, wobei Aspartylhydroxamate und Aminoendgruppen entstehen. Die Reaktion von Gelatine mit Hydroxylamin ergab Fragmente mit Molekulargewichten von 15, 25, 37, und 50 kDa (bestimmt mit SDS-PAGE), und die Formierung dieser Fragmente war unabhängig von den weiteren Reaktionsbedingungen und der Reaktionszeit. Jedes dieser Fragmente kann potentiell für die Synthese von Hydrogelen eingesetzt werden, die ausschließlich aus Biopolymeren bestehen.
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Korniienko, Anton. "Réseau de PLLs distribuées pour synthèse automatique d'horloge de MPSOCs synchrones." Phd thesis, Ecole Centrale de Lyon, 2011. http://tel.archives-ouvertes.fr/tel-00676933.

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Les arbres classiques de distribution du signal d'horloge au sein des microprocesseurs synchrones présentent un certain nombre de limitations : skew, jitter, limitation de la fréquence, influence de perturbations et de dispersions quelles que soient leurs natures. Ces facteurs, critiques pour les microprocesseurs modernes complexes, sont devenus la raison principale qui a poussé à la recherche d'autres types d'architecture de génération et de distribution du signal d'horloge. Un exemple d'un tel système alternatif est le réseau de PLLs couplées, où les PLLs sont géographiquement distribuées sur la puce, et génèrent des signaux d'horloge locaux qui sont ensuite synchronisés, en temps réel, par un échange d'information entre les PLLs voisines et une rétroaction locale réalisé par leur correcteurs. La nature active du réseau de PLLs de génération et de distribution du signal d'horloge, qui peut permettre de surpasser les limitations mentionnées plus tôt, oblige à sortir du cadre classique des outils et des méthodes de la Microélectronique habituellement appliqués à l'étude et à la conception de ce type de systèmes. En effet, les aspects dynamiques de bouclage et de transformation de signaux au sein de tels systèmes complexes rendent leur conception extrêmement difficile voire parfois impossible. La difficulté principale consiste en un changement des propriétés d'un sous-système local indépendant par rapport aux propriétés du même sous-système faisant partie du réseau. Effectivement, il existe beaucoup de méthodes et d'outils de conception d'une PLL isolée garantissant un comportement et des propriétés locales désirés. Néanmoins, ces propriétés désirées locales, selon la topologie d'interconnexion considérée, ne sont pas forcément conservées quand il s'agit d'un réseau de PLLs interconnectées et de son comportement global. Le but principal de cette thèse est ainsi de développer une méthode de synthèse de la loi de commande décentralisée réalisée au sein de chaque sous-système (tel qu'une PLL) assurant le comportement désiré pour le réseau global. Une méthode de transformation du problème de synthèse globale en un problème équivalent de synthèse d'une loi de commande locale est proposée en se basant sur l'hypothèse des sous-systèmes identiques interconnectés en réseau. Le lien entre les propriétés locales et globales est établi grâce aux approches d'Automatique avancée telles que les approches entrée-sortie et la dissipativité. Ce choix de méthode permet non seulement de réduire considérablement la complexité du problème initial mais aussi de ramener le problème de synthèse à une forme proche des méthodes de conception locale utilisées en Microélectronique, ce qui garantit une continuité logique de leur évolution. Ensuite la méthode proposée est combinée avec la commande H∞ et l'optimisation sous contraintes LMIs conduisant au développement d'algorithmes efficaces de résolution du problème posé. Elles sont à la fois particulièrement bien adaptées à l'application considérée, c'est-à-dire à la synchronisation d'un réseau de PLLs, et sont facilement généralisables aux autres types de problèmes de commande de systèmes de grande dimension. Le premier aspect permet une intégration naturelle et aisée de la méthode dans le flux de conception existant en Microélectronique, très riche et mature à ce jour, alors que le deuxième offre une solution à d'autres problèmes de commande de systèmes interconnectés en réseau, un champ d'application aujourd'hui en plein essor.
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Saint-Laurent, Martin. "Modeling and Analysis of High-Frequency Microprocessor Clocking Networks." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7271.

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Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.
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Zarrabi, Houman. "On the design and synthesis of differential clock distribution network." Thesis, 2006. http://spectrum.library.concordia.ca/8795/1/MR14288.pdf.

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This research work focuses mainly on the design and synthesis of Differential Clock Distribution Networks (DCDNs). The Clock Distribution Network (CDN) plays an important role in synchronous systems. The network is spread all over the chip to synchronize its sub-systems. The system performance is influenced by the performance of its clock network. As technology advances and the complexity increases, a drastic growth in the chip complexity in the near future is expected. Thus designing a reliable CDN is becoming a must, and therefore all the design efforts should be utilized to efficiently design clock distribution networks. Of importance in chip design are low power and low noise concepts. Differential signaling scheme offers high noise immunity and since it is associated with signal amplitudes lower than the usual, it may contribute to reduce power consumption as well. Due to these potentials, the design and analysis of DCDN has been the focus of this research work. First, a line equivalent delay model based on the decoupling method is proposed to be able to route DCDNs with minimum skew. This part refers to the routing and synthesis of DCDNS. Later, new configurations for differential buffers based on body-biased transistors are proposed, which show better performance for future low voltage applications. Finally, a circuit and system design method that reduces the power consumption of DCDNs is proposed. This is accomplished in two steps: First circuit configurations that reduce the differential voltage swing giving less power consumption are introduced. Later, by reducing the supply voltage, a DCDN is designed which has the same power consumption as single-node CDNs, but has less skew variation in the presence of external noises such as power supply fluctuations.
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Huang, Chi-Han, and 黃啟翰. "Design of Buffer Clock-Gating Architecture for Network-on-Chip." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/42mm58.

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碩士
國立臺北科技大學
電腦與通訊研究所
99
The multicore system is more popular architecture in recently. The NoC (Network-on-Chip) architecture is proposed to solve the problem of high performance and throughput in a multicore system but it derived some problems such as of power consumption, area and deadlock, etc. This paper proposes a buffer clock-gating (BCG) architecture to improve the power consumption and area of buffers in Network-on-Chip. When buffer content is full or empty, the BCG uses clock-gating technology to gating buffer period to reduce power consumption. When data packet length is 10 bits: comparison with IntelliBuffer [2], the proposed method reduced 16.8% on power consumption, 45.9% on area and 2.7% on time delay and comparison with [3], the proposed method reduced 38% on power consumption and 15.2% on area. When data packet length is 18 bits: comparison with IntelliBuffer [2], the proposed method reduced 22.4% on power consumption, 40.9% on area and 2% on time delay and comparison with [3], the proposed method reduced 32.9% on power consumption, 13% on area and 2% on time delay.
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Books on the topic "Clock network design"

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Zhu, Qing K. High-Speed Clock Network Design. Boston, MA: Springer US, 2003.

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Zhu, Qing K. High-Speed Clock Network Design. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9.

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Zhu, Qing K. High-speed clock network design. Boston: Kluwer Academic Publishers, 2003.

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Friedman, Eby G. High Performance Clock Distribution Networks. Boston, MA: Springer US, 1997.

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Inc, Entrepreneur Media, ed. Click start: Design and launch an online networking business in a week. Irvine, Calif: Entrepreneur Media, 2009.

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Zhu, Qing K. High-Speed Clock Network Design. Springer, 2002.

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High Performance Clock Distribution Networks. Springer, 2012.

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G, Friedman Eby, ed. High performance clock distribution networks. Boston: Kluwer Academic Publishers, 1997.

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Clock distribution networks in VLSI circuits and systems. Piscataway, NJ: IEEE Press, 1995.

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A hardware implementation of a probably correct design of a fault-tolerant clock synchronization circuit. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1993.

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Book chapters on the topic "Clock network design"

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Zhu, Qing K. "Clock Network Simulation Methods." In High-Speed Clock Network Design, 109–24. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_7.

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Zhu, Qing K. "Balanced Clock Routing Algorithms." In High-Speed Clock Network Design, 147–61. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_10.

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Zhu, Qing K. "Microprocessor Clock Distribution Examples." In High-Speed Clock Network Design, 89–107. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_6.

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Zhu, Qing K. "Routing Clock On Package." In High-Speed Clock Network Design, 135–46. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_9.

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Zhu, Qing K. "Clock Generation and De-skewing." In High-Speed Clock Network Design, 75–88. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_5.

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Zhu, Qing K. "Low-Voltage Swing Clock Distribution." In High-Speed Clock Network Design, 125–34. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_8.

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Zhu, Qing K. "Design Methodology for Domino Circuits." In High-Speed Clock Network Design, 57–73. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_4.

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Zhu, Qing K. "Clock Tree Design Flow in ASIC." In High-Speed Clock Network Design, 163–70. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_11.

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Zhu, Qing K. "Overview to Timing Constraints." In High-Speed Clock Network Design, 23–40. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_2.

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Zhu, Qing K. "Sequential Clocked Elements." In High-Speed Clock Network Design, 41–56. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_3.

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Conference papers on the topic "Clock network design"

1

Bueno, Átila Madureira, Angelo Marcelo Tusset, Diego Paolo Ferruzzo Correa, José Roberto Castilho Piqueira, and José Manoel Balthazar. "Comparing LQG/LTR and the SDRE Techniques for Hybrid Fully-Connected PLL Network Control." In ASME 2013 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/detc2013-12649.

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Synchronization plays an important role in telecommunication systems and integrated circuits. The Master-Slave is a commonly used strategy for clock signal distribution. However, due to the wireless networks development and the higher operation frequency of integrated circuits, the Mutually-Connected clock distribution strategies are becoming important, and the Fully-Connected strategy appears as a convenient engineering solution. The main drawback of the Fully-Connected architecture is the definition of control algorithms that assure the stability of the network sinchronization. In hybrid synchronization techniques groups of nodes synchronized by the Fully-Connected architecture are synchronized with network master clocks by using the Master-Slave tecnique. In this arrangement, if a route of clock signal distribution becomes inoperative, the group of Fully-Connected nodes retain for some time the original phase and frequency received from the network. The Fully-Connected architecture complexity imposes difficulties to satisfy both stability and performance requirements in the control system design. For that reason the multi-variable LQG/LTR and the SDRE control techniques are applied in order to fulfill both stability and performance requirements. The performance of both techniques are compared, and the results seems to confirm the improvement in the transient response and in the precision of the clock distribution process.
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Lung, Chiao-Ling, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, and Shih-Chieh Chang. "Fault-tolerant 3D clock network." In the 48th Design Automation Conference. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/2024724.2024872.

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Sze, Cliff. "The future of clock network synthesis." In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2011. http://dx.doi.org/10.1109/iccad.2011.6105339.

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Yan Luo, Jia Yu, Jun Yang, and Laxmi Bhuyan. "Low power network processor design using clock gating." In 2005 42nd Design Automation Conference. IEEE, 2005. http://dx.doi.org/10.1109/dac.2005.193904.

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Yongqiang Lu, C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, and Jiang Hu. "Navigating registers in placement for clock network minimization." In 2005 42nd Design Automation Conference. IEEE, 2005. http://dx.doi.org/10.1109/dac.2005.193796.

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Xiao, Linfu, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, and Evangeline F. Y. Young. "Local clock skew minimization using blockage-aware mixed tree-mesh clock network." In 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2010. http://dx.doi.org/10.1109/iccad.2010.5653732.

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Liu, Bao, Andrew B. Kahng, Xu Xu, Jiang Hu, and Ganesh Venkataraman. "A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield." In 2007 Asia and South Pacific Design Automation Conference. IEEE, 2007. http://dx.doi.org/10.1109/aspdac.2007.357787.

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Kim, Tak-Yung, and Taewhan Kim. "Clock network design techniques for 3D ICs." In 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2011. http://dx.doi.org/10.1109/mwscas.2011.6026427.

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Ahn, Yongsoo, Donkyu Baek, Dongsoo Lee, and Youngsoo Shin. "Pulsed-Vdd: Synchronous circuit design without clock network." In 2013 International Soc Design Conference (ISOCC). IEEE, 2013. http://dx.doi.org/10.1109/isocc.2013.6863969.

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MohammadZadeh, N., M. Mirsaeedi, A. Jahanian, and M. S. Zamani. "Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network." In 2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09). IEEE, 2009. http://dx.doi.org/10.1109/date.2009.5090778.

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