Relevant bibliographies by topics / CMOS comparator

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'CMOS comparator'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "CMOS comparator"

1

Liu, Yuchuan. "An Review of Dynamic CMOS Comparators." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 113–20. http://dx.doi.org/10.54097/hset.v44i.7273.

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CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.
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Gajawada, Varun sai, and Mohana J. "Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator." ECS Transactions 107, no. 1 (2022): 13873–85. http://dx.doi.org/10.1149/10701.13873ecst.

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The aim of the study is to construct and analyze innovative CMOS based double tail comparators and compare them with a dynamic comparator using VLSI technology. Materials and methods: The comparator is designed by using the tanner tool for simulation and verification. By varying the length of a transistors the power values were obtained. There are two groups in the study. CMOS double tail comparator is the experimental group and dynamic tail comparator is the control group. This experiment is performed for 20 different values of length. Results: The power consumption of a CMOS logic double tai
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G., Naveen Balaji, Karthikeyan S., and Merlin Asha M. "0.18µm CMOS Comparator for High Speed Applications." International Journal of Trend in Scientific Research and Development 1, no. 5 (2017): 671–74. https://doi.org/10.31142/ijtsrd2356.

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In the electronics industry the Low Power Comparator using High Speed in Analog to Digital Converters. In electronic device Comparator are mostly used in Analog to Digital converter ADC . In ADC are used for the delay produced and power consumed by an ADC. I design a 0.18µm CMOS Comparator for High Speed Application. The advantage of programmable hysteresis to the comparators are also discussed. Tanner EDA is used for the design and simulation for the comparator circuits The difference between the proposed comparator to the existing double tail comparator result are produced. G. Naveen B
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Fan, Jiangfeng. "Performance Analysis of Low-Power CMOS Dynamic Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 62–71. http://dx.doi.org/10.54097/hset.v27i.3722.

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This paper studies four structures of CMOS dynamic comparators introduced in recent years. Based on conventional double-tail comparator, a comparator with a tail capacitor prevents output nodes of preamplifier from completely discharging to reduce energy consumption. Another comparator with a cross-coupled pairs achieves the same purpose of the first design. A comparator adds a floating inverter amplifier (FIA) to realize both dynamic bias and current reuse, achieve low energy consumption and be insensitive to the VCM. The triple-latch feed-forward (TLFF) comparator decreases delay conspicuous
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Sharmila Vallem. "Design of a High speed Low Low-Power Latched Comparator for Medical Implants." Communications on Applied Nonlinear Analysis 32, no. 8s (2025): 87–104. https://doi.org/10.52783/cana.v32.3610.

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The latched dynamic comparator is a fundamental component in all ADC architectures. Thermal effects, kickback, and offset voltage influence it. The kickback noise of the latched comparator in medical implant ADCs can impact the resolution, precision, and settling period. The current study examines a latching comparator that aims to reduce kickback noise. This research presents a low-power latched comparator for medical implants functioning at 1 V. This investigation implements a comparator utilising the sampling switching approach. This method successfully minimises kick-back noise and clockin
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Dharmireddy, Ajay Kumar, D. Sowjanya, D. Aravind, G. Sowmya, A. Chandu, and Rao G. Venkateswara. "Low Kickback Noise and High-Speed MultiStage Comparator for High-Speed SAR ADC's." International Journal of Microsystems and IoT 2, no. 2 (2024): 614–21. https://doi.org/10.5281/zenodo.10809165.

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In this paper, proposes the design of a high-speed, low-kickback, three-stage comparator built on CMOS technology. This 1.2V supply-operated comparator circuit develops for use in high-speed ADCs. There are three parts to the proposed comparator circuit: a preamplifier, a latch, and a regeneration stage. The input signal amplifies in the preamplifier stage, producing a differential output signal. Once the movement from the preamplifier (PA) stage strengthens, it is stored in the latch stage until the regeneration stage is ready to utilize—simulations in CMOS technology to test the sugges
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Sathishkumar, Arumugam, and Siddhan Saravanan. "A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture." Journal of Circuits, Systems and Computers 28, no. 02 (2018): 1950022. http://dx.doi.org/10.1142/s0218126619500221.

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A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-r
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Mikkola, E., B. Vermeire, H. J. Barnaby, H. G. Parks, and K. Borhani. "SET tolerant CMOS comparator." IEEE Transactions on Nuclear Science 51, no. 6 (2004): 3609–14. http://dx.doi.org/10.1109/tns.2004.839161.

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Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (2022): 716. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when
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Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (2022): 716–23. https://doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm complementary metal-oxide semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when
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Dissertations / Theses on the topic "CMOS comparator"

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Shar, Ahmad. "Design of a High-Speed CMOS Comparator." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10446.

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<p>This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.</p><p>The comparator is designed for time-interleaved bandpass sigma-delta ADC.</p><p>Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less
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Wang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

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Dowlatabadi, Ahmad Baghai. "A high speed, high resolution, self-clocked voltage comparator in a standard digital CMOS process." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/14794.

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Matěj, Jan. "Návrh a optimalizace spínaného komparátoru v 250 nm CMOS technologii." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318180.

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This diploma thesis deals with design methods and optimization techniques of dynamic latched comparators. It compares latched and continuous comparators and describes their principle. Then it analyses three popular latched comparator structures with respect to offset, speed and kickback noise. It shows practical comparator design focused on offset precision.
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Qazi, Sara. "Study of Time-Interleaved SAR ADC andImplementation of Comparator for High DefinitionVideo ADC in 65nm CMOS Process." Thesis, Linköpings universitet, Elektroniksystem, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-63854.

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The Analog to Digital Converter (ADC) is an inevitable part of video AnalogFront Ends (AFE) found in the electronic displays today. The need to integratemore functionality on a single chip (there by shrinking area), poses great designchallenges in terms of achieving low power and desired accuracy.The thesis initially focuses upon selection of suitable Analog to Digital Converter(ADC) architecture for a high definition video analog front end. SuccessiveApproximation Register (SAR) ADC is the selected architecture as it scales downwith technology, has very less analog part and has minimal power
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Boppana, Naga Venkata Vijaya Krishna. "16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies." Wright State University / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=wright1420674477.

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Hedayati, Raheleh. "A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

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In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture.  Based on this analysis, dynamic two-stage comparator is select
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Manh, Vir Varinder. "An Integrated High Efficiency DC-DC Converter in 65 nm CMOS." Thesis, Linköpings universitet, Elektroniksystem, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-61237.

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This thesis work describes the implementation perspective of an integrated high efficiency DC-DC converter implemented in 65 nm CMOS. The implemented system employs the Buck converter topology to down-convert the input battery voltages. This converter offers its use as a power management unit in portable battery operated devices. This thesis work includes the description of a basic Buck converter along with the various key equations involved which describe the Buck operation as well as are used to deduce the requirements for the various internal building blocks of the system. A detailed descri
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Levski, Dimitrov Deyan. "A Cyclic Analog to Digital Converter for CMOS image sensors." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103193.

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The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to
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Perbet, Lucas. "Optimisation de blocs constitutifs d'un convertisseur A/N pipeline entechnologie CMOS 0.18 µm pour utilisation en environnement spatial." Thesis, Toulouse, INPT, 2017. http://www.theses.fr/2017INPT0037/document.

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L’imagerie constitue un axe majeur de l’exploration de l’univers et de la Terre depuis l’espace, que l’on se trouve dans le domaine du visible ou non. Ainsi dans le domaine spatial, les données sont le plus souvent récupérées par un capteur CCD (Charge-Coupled Device, ou Dispositif à Transfert de Charge (DTC)) qui fournit des tensions analogiques vers un convertisseur analogique-numérique (CAN), dont la sortie sera transmise à une chaîne de traitement, puis envoyée sur terre. Ainsi, les CAN sont des éléments clés dans l’imagerie par satellite. De leur précision et de leur vitesse va dépendre l
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Books on the topic "CMOS comparator"

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K, Kokula Krishna Hari, ed. An adjustable Comparator for 2-bit/step SAR ADC Configuring with multiple samples per second in 40nm CMOS. Association of Scientists, Developers and Faculties, 2016.

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Goll, Bernhard, and Horst Zimmermann. Comparators in Nanometer CMOS Technology. Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-44482-5.

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Introduction to CMOS OP-AMPs and comparators. Wiley, 1999.

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Gregorian, Roubik. Introduction to CMOS OP-AMPs and Comparators. Wiley & Sons, Incorporated, John, 2008.

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Zimmermann, Horst, and Bernhard Goll. Comparators in Nanometer CMOS Technology. Springer, 2016.

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Zimmermann, Horst, and Bernhard Goll. Comparators in Nanometer CMOS Technology. Springer, 2014.

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Zimmermann, Horst, and Bernhard Goll. Comparators in Nanometer CMOS Technology. Springer, 2014.

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Cmos Amplifiers Comparators Multipliers Filters and Oscillators. Taylor & Francis Group, 2018.

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Gregorian. Introduction to CMOS OP-AMPs and Comparators. Wiley & Sons, Incorporated, John, 1999.

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Book chapters on the topic "CMOS comparator"

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Gandhi, Priyesh P., and Niranjan M. Devashrayee. "Low-Offset High-Speed CMOS Dynamic Voltage Comparator." In Advances in Intelligent Systems and Computing. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-5903-2_23.

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Singh, Tejender, and Suman Latha Tripathi. "A Review of a Low-Power CMOS Comparator." In Electronic Devices and Circuit Design. Apple Academic Press, 2021. http://dx.doi.org/10.1201/9781003145776-6.

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Pravalika, P., P. Narendra, T. Srilakshmi, Ch Bhavani, and P. Kishore Kumar. "The Development of a CMOS Logic Double Tail Comparator that uses Less Power than a Dynamic Comparator." In Recent Developments in Microbiology, Biotechnology and Pharmaceutical Sciences. CRC Press, 2025. https://doi.org/10.1201/9781003618140-96.

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Kumar, Varun, Krishan Kumar Singh, Abhishek Pandey, and Vijay Nath. "Design of Comparator in Sigma-Delta ADC Using 45 nm CMOS Technology." In Lecture Notes in Electrical Engineering. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-2999-8_32.

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Nagore, Rahul, Pramod Kumar Jain, R. S. Gamad, and Rahul Priyadarshi. "Design of Low-Power High-Efficient Single-Tail Comparator Using 180 nm CMOS Technology." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-1906-0_14.

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Dubey, Avaneesh Kumar, Vikrant Varshney, Ankur Kumar, Pratosh Kumar Pal, and Rajendra Kumar Nagaria. "Low-Power Enhanced Speed Two-Tail Dynamically Controlled Comparator Suitable for Subthreshold CMOS Circuits." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-2761-3_97.

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Domínguez-Castro, Rafael, Manuel Delgado-Restituto, Angel Rodríguez-Vázquez, José M. de la Rosa, and Fernando Medeiro. "CMOS Comparators." In CMOS Telecom Data Converters. Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3724-0_4.

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Payyavula, Ramakrishna, and D. Gowri Sankar Reddy. "Power Optimized Domino Logic Design of a Comparator with Variable Threshold CMOS and Clock Gating." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-6855-8_35.

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Ghosh, Arpita, and Subir Kumar Sarkar. "Comparative study of single electron threshold logic based and SET-CMOS hybrid based 1 bit comparator." In Computational Science and Engineering. CRC Press, 2016. http://dx.doi.org/10.1201/9781315375021-46.

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Dubey, Avaneesh K., Vikrant Varshney, Ankur Kumar, Pratosh K. Pal, and R. K. Nagaria. "Design and Performance of High-Speed CMOS Double-Tail Dynamic Comparator Suitable for Mixed-Signal ICs." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-6840-4_7.

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Conference papers on the topic "CMOS comparator"

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Pal, Rahul, Jayanta Ghosh, and Aloke Saha. "Novel Low-PDP CMOS Double-Base Comparator." In 2024 IEEE International Conference on Smart Power Control and Renewable Energy (ICSPCRE). IEEE, 2024. http://dx.doi.org/10.1109/icspcre62303.2024.10674911.

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Aleti, Kavya, B. Ravi Kumar, Pavan Kumar Rudrapangu, and Ramesh Sonta. "Design of Self-Calibration Comparator Using CMOS Technology." In 2024 International BIT Conference (BITCON). IEEE, 2024. https://doi.org/10.1109/bitcon63716.2024.10984868.

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Agustin, Jazzmyne Rona M., Harreez M. Villaruz, Nieva M. Mapula, and Gene Fe P. Palencia. "High Speed Low Power Dynamic CMOS Comparator for SAR ADCs." In TENCON 2024 - 2024 IEEE Region 10 Conference (TENCON). IEEE, 2024. https://doi.org/10.1109/tencon61640.2024.10903011.

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Gassouma, Hajer, Thouraya Ettaghzouti, Mounira Bchir, and Néjib Hassen. "A High-Speed Low-voltage Low-power CMOS Dynamic Comparator." In 2025 IEEE 22nd International Multi-Conference on Systems, Signals & Devices (SSD). IEEE, 2025. https://doi.org/10.1109/ssd64182.2025.10989829.

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Zhang, Yafei, Kangkang Sun, Xiaoqi Peng, Xinying Su, Weijie Ge, and Jingjing Liu. "Novel Structure of Dynamic CMOS Comparator with High Energy Efficiency." In 2025 3rd International Conference on Integrated Circuits and Communication Systems (ICICACS). IEEE, 2025. https://doi.org/10.1109/icicacs65178.2025.10968119.

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Prusty, Abinasha, Rudra Narayan Dash, Birupakhya Padhy, Amit Bakshi, Rajendra Prasad, and Srinibasa Padhy. "Design of Low Power Two Bit Variable - Threshold Comparator by CMOS Technology." In 2024 IEEE 4th International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC). IEEE, 2024. https://doi.org/10.1109/aespc63931.2024.10871959.

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Pandey, Nishi, Laxmi Singh, and Abhishek Agwekar. "Implementation of High Speed Cascode Cross-Coupled Stage Comparator in CMOS Technology." In 2025 10th International Conference on Signal Processing and Communication (ICSC). IEEE, 2025. https://doi.org/10.1109/icsc64553.2025.10968717.

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Panov, Georgi Nikolov, and Angel Nikolaev Popov. "Replica biased complementary CMOS comparator." In 2017 XXVI International Scientific Conference "Electronics" (ET). IEEE, 2017. http://dx.doi.org/10.1109/et.2017.8124374.

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Gandhi, Priyesh P., and N. M. Devashrayee. "High performance CMOS voltage comparator." In 2013 Nirma University International Conference on Engineering (NUiCONE). IEEE, 2013. http://dx.doi.org/10.1109/nuicone.2013.6780141.

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Gong, Cihun-Siyong Alex, Tim K. Shia, Yung-Pin Lee, Bo-Wei Chen, Kai-Wen Yao, and Muh-Tian Shiue. "CMOS comparator for medical imaging." In 2011 4th International Conference on Biomedical Engineering and Informatics (BMEI). IEEE, 2011. http://dx.doi.org/10.1109/bmei.2011.6098465.

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