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Journal articles on the topic 'CMOS comparator'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Liu, Yuchuan. "An Review of Dynamic CMOS Comparators." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 113–20. http://dx.doi.org/10.54097/hset.v44i.7273.

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CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.

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2

Gajawada, Varun sai, and Mohana J. "Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator." ECS Transactions 107, no. 1 (2022): 13873–85. http://dx.doi.org/10.1149/10701.13873ecst.

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The aim of the study is to construct and analyze innovative CMOS based double tail comparators and compare them with a dynamic comparator using VLSI technology. Materials and methods: The comparator is designed by using the tanner tool for simulation and verification. By varying the length of a transistors the power values were obtained. There are two groups in the study. CMOS double tail comparator is the experimental group and dynamic tail comparator is the control group. This experiment is performed for 20 different values of length. Results: The power consumption of a CMOS logic double tai

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G., Naveen Balaji, Karthikeyan S., and Merlin Asha M. "0.18µm CMOS Comparator for High Speed Applications." International Journal of Trend in Scientific Research and Development 1, no. 5 (2017): 671–74. https://doi.org/10.31142/ijtsrd2356.

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In the electronics industry the Low Power Comparator using High Speed in Analog to Digital Converters. In electronic device Comparator are mostly used in Analog to Digital converter ADC . In ADC are used for the delay produced and power consumed by an ADC. I design a 0.18µm CMOS Comparator for High Speed Application. The advantage of programmable hysteresis to the comparators are also discussed. Tanner EDA is used for the design and simulation for the comparator circuits The difference between the proposed comparator to the existing double tail comparator result are produced. G. Naveen B

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4

Fan, Jiangfeng. "Performance Analysis of Low-Power CMOS Dynamic Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 62–71. http://dx.doi.org/10.54097/hset.v27i.3722.

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This paper studies four structures of CMOS dynamic comparators introduced in recent years. Based on conventional double-tail comparator, a comparator with a tail capacitor prevents output nodes of preamplifier from completely discharging to reduce energy consumption. Another comparator with a cross-coupled pairs achieves the same purpose of the first design. A comparator adds a floating inverter amplifier (FIA) to realize both dynamic bias and current reuse, achieve low energy consumption and be insensitive to the VCM. The triple-latch feed-forward (TLFF) comparator decreases delay conspicuous

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Sharmila Vallem. "Design of a High speed Low Low-Power Latched Comparator for Medical Implants." Communications on Applied Nonlinear Analysis 32, no. 8s (2025): 87–104. https://doi.org/10.52783/cana.v32.3610.

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The latched dynamic comparator is a fundamental component in all ADC architectures. Thermal effects, kickback, and offset voltage influence it. The kickback noise of the latched comparator in medical implant ADCs can impact the resolution, precision, and settling period. The current study examines a latching comparator that aims to reduce kickback noise. This research presents a low-power latched comparator for medical implants functioning at 1 V. This investigation implements a comparator utilising the sampling switching approach. This method successfully minimises kick-back noise and clockin

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Dharmireddy, Ajay Kumar, D. Sowjanya, D. Aravind, G. Sowmya, A. Chandu, and Rao G. Venkateswara. "Low Kickback Noise and High-Speed MultiStage Comparator for High-Speed SAR ADC's." International Journal of Microsystems and IoT 2, no. 2 (2024): 614–21. https://doi.org/10.5281/zenodo.10809165.

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In this paper, proposes the design of a high-speed, low-kickback, three-stage comparator built on CMOS technology. This 1.2V supply-operated comparator circuit develops for use in high-speed ADCs. There are three parts to the proposed comparator circuit: a preamplifier, a latch, and a regeneration stage. The input signal amplifies in the preamplifier stage, producing a differential output signal. Once the movement from the preamplifier (PA) stage strengthens, it is stored in the latch stage until the regeneration stage is ready to utilize—simulations in CMOS technology to test the sugges

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7

Sathishkumar, Arumugam, and Siddhan Saravanan. "A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture." Journal of Circuits, Systems and Computers 28, no. 02 (2018): 1950022. http://dx.doi.org/10.1142/s0218126619500221.

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A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-r

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8

Mikkola, E., B. Vermeire, H. J. Barnaby, H. G. Parks, and K. Borhani. "SET tolerant CMOS comparator." IEEE Transactions on Nuclear Science 51, no. 6 (2004): 3609–14. http://dx.doi.org/10.1109/tns.2004.839161.

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9

Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (2022): 716. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when

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10

Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (2022): 716–23. https://doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm complementary metal-oxide semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when

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11

Arunabala, Dr C., P. V. Sai Ranjitha, Bomminayuni Likhitha Gunturu Sravya, Bonagiri Navyasree, and Arumalla Mounika. "Design of Diversified Low Power and High-Speed Comparators using 45nm Cmos Technology." International Journal of Innovative Technology and Exploring Engineering 11, no. 5 (2022): 27–31. http://dx.doi.org/10.35940/ijitee.e9849.0411522.

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At Present, portable battery-operated devices are enhancing due to low power consumption and high-speed applications, The designed circuit with feedback are used to design novel circuits. If the comparator having feedback are without clock signal. The comparators are mainly designed to minimize the power consumption and with good accuracy because of clock signal, if the clock signal is there, it is used to drive the circuit with low current. But in the existed design the circuit is with high power and current. These drawbacks are overcome by using the projected designed comparator. The Project

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12

Dr., C. Arunabala, Ranjitha P.V.Sai, Likhitha Gunturu Sravya Bomminayuni, Navyasree Bonagiri, and Mounika Arumalla. "Design of Diversified Low Power and High-Speed Comparators using 45nm Cmos Technology." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 11, no. 5 (2022): 27–31. https://doi.org/10.35940/ijitee.E9849.0411522.

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<strong>Abstract:</strong> At Present, portable battery-operated devices are enhancing due to low power consumption and high-speed applications, The designed circuit with feedback are used to design novel circuits. If the comparator having feedback are without clock signal. The comparators are mainly designed to minimize the power consumption and with good accuracy because of clock signal, if the clock signal is there, it is used to drive the circuit with low current. But in the existed design the circuit is with high power and current. These drawbacks are overcome by using the projected desig

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13

RAMAMOORTHY, SARAVANAN, and HAIBO WANG. "ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE." Journal of Circuits, Systems and Computers 22, no. 06 (2013): 1350048. http://dx.doi.org/10.1142/s0218126613500485.

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Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impact

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14

., Vipin V. Kashti. "PERFORMANCE ANALYSIS OF CMOS COMPARATOR AND CNTFET COMPARATOR DESIGN." International Journal of Research in Engineering and Technology 03, no. 04 (2014): 862–66. http://dx.doi.org/10.15623/ijret.2014.0304152.

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15

Goswami, Shikha. "A LEAKAGE TOLERANT CMOS COMPARATOR." International Journal of Engineering Applied Sciences and Technology 5, no. 4 (2020): 480–83. http://dx.doi.org/10.33564/ijeast.2020.v05i04.076.

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16

CHONG, CHU PHOON, and KENNETH C. SMITH. "A high-resolution CMOS comparator." International Journal of Electronics 64, no. 3 (1988): 409–15. http://dx.doi.org/10.1080/00207218808962815.

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17

Steyaert, M., and V. Comino. "High-speed accurate CMOS comparator." Electronics Letters 24, no. 16 (1988): 1027. http://dx.doi.org/10.1049/el:19880699.

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18

Tang, X., and K. P. Pun. "High-performance CMOS current comparator." Electronics Letters 45, no. 20 (2009): 1007. http://dx.doi.org/10.1049/el.2009.1419.

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19

Gustat, H. "Fast CMOS multilevel current comparator." Electronics Letters 29, no. 7 (1993): 592. http://dx.doi.org/10.1049/el:19930397.

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20

Tang, A. T. K., and C. Toumazou. "High performance CMOS current comparator." Electronics Letters 30, no. 1 (1994): 5–6. http://dx.doi.org/10.1049/el:19940003.

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21

sharma*, D. Pavan kumar, and P. Sreehari Rao. "A Low Input Referred Noise Dynamic Comparator for High Speed Applications." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 4 (2019): 4768–72. http://dx.doi.org/10.35940/ijrted6881.118419.

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Comparators play a pivotal role in design of analog and mixed signal circuits. Comparators employ regenerative feedback both in input pre-amplifier stage and output stage. The designed comparator resolves 5mV with resolution of 8 bits and dissipates 11mW of power using 1.2V supply in 130nm CMOS technology while operating at clock frequency of 1.25 GHz.

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22

Mukhopadhyay, Abhijit Kumar. "A Low Power Digital Binary Magnitude Comparator Design for Very Large Scale Integration Applications." Advanced Science, Engineering and Medicine 12, no. 6 (2020): 825–30. http://dx.doi.org/10.1166/asem.2020.2655.

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This paper reports two designs of low power digital binary magnitude comparator based on static complementary CMOS logic style. The designs make use of recently reported latest XNOR gate designs. The comparator designs proposed here are easily scalable for higher order bits and thus highly suitable for VLSI applications. Mathematical equations establishing the relation between input bit width and transistor count of the magnitude comparators have also been derived in this paper. For a 64 bit magnitude comparator, the designs proposed in this paper outperform an existing design by 12.17% and 10

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23

Kulothungan, Brindha, and Manjula Jothilingam. "A low power and high speed 45 nm CMOS dynamic comparator with low offset." A low power and high speed 45nm CMOS dynamic comparator with low offset 14, no. 4 (2023): 2293–300. https://doi.org/10.11591/ijpeds.v14.i4.pp2293-2300.

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The development of efficient data converters necessitates the design of low-power and high-speed comparators with low offset. Data converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs), are critical components in applications like wireless communication, multimedia, and sensor interfaces. To enhance the performance of these data converters, improving the speed and power efficiency of comparators becomes crucial. Designing dynamic comparators with low power consumption and high-speed capabilities greatly enhances the sampling rate and accuracy of data c

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24

Balaji, G. Naveen, S. Karthikeyan, and M. Merlin Asha. "0.18µm CMOS Comparator for High-Speed Applications." International Journal of Trend in Scientific Research and Development Volume-1, Issue-5 (2017): 671–74. http://dx.doi.org/10.31142/ijtsrd2356.

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25

Brindha, Kulothungan, and Jothilingam Manjula. "A low power and high speed 45 nm CMOS dynamic comparator with low offset." International Journal of Power Electronics and Drive Systems (IJPEDS) 14, no. 4 (2023): 2293. http://dx.doi.org/10.11591/ijpeds.v14.i4.pp2293-2300.

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<p><span lang="EN-US">The development of efficient data converters necessitates the design of low-power and high-speed comparators with low offset. Data converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs), are critical components in applications like wireless communication, multimedia, and sensor interfaces. To enhance the performance of these data converters, improving the speed and power efficiency of comparators becomes crucial. Designing dynamic comparators with low power consumption and high-speed capabilities greatly enhances the sa

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26

Sasikumar, Sasikumar, and Muthaiah Muthaiah. "An Optimal Design of CMOS Two Stage Comparator Circuit using Swarm Intelligence Technique." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (2018): 125. http://dx.doi.org/10.11591/ijres.v7.i3.pp125-131.

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A swarm intelligent based optimization technique named as Flower pollination algorithm (FPA) is applied for the design of the CMOS two stage comparator circuit. The basic idea of FPA mimics the flower pollination process of flowering plants. The input control parameters of FPA improve the exploration and exploitation capabilities of optimization problem. This paper presents the design of a CMOS two-stage comparator circuit using simulation based model called swarm intelligence technique. Simulation results shows that the proposed method is capable to determine the transistor sizes and bias cur

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Sasikumar, Sasikumar, and Muthaiah Muthaiah. "An Optimal Design of CMOS Two Stage Comparator Circuit using Swarm Intelligence Technique." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (2018): 131. http://dx.doi.org/10.11591/ijres.v7.i3.pp131-137.

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A swarm intelligent based optimization technique named as Flower pollination algorithm (FPA) is applied for the design of the CMOS two stage comparator circuit. The basic idea of FPA mimics the flower pollination process of flowering plants. The input control parameters of FPA improve the exploration and exploitation capabilities of optimization problem. This paper presents the design of a CMOS two-stage comparator circuit using simulation based model called swarm intelligence technique. Simulation results shows that the proposed method is capable to determine the transistor sizes and bias cur

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Sasikumar and Muthaiah. "An Optimal Design of CMOS Two Stage Comparator Circuit Using Swarm Intelligence Technique." International Journal of Reconfigurable and Embedded Systems 7, no. 3 (2018): 131–37. https://doi.org/10.11591/ijres.v7.i3.pp131-137.

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A swarm intelligent based optimization technique named as Flower pollination algorithm (FPA) is applied for the design of the CMOS two stage comparator circuit. The basic idea of FPA mimics the flower pollination process of flowering plants. The input control parameters of FPA improve the exploration and exploitation capabilities of optimization problem. This paper presents the design of a CMOS two-stage comparator circuit using simulation based model called swarm intelligence technique. Simulation results shows that the proposed method is capable to determine the transistor sizes and bias cur

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29

Thai, Hong-Hai, Cong-Kha Pham, and Duc-Hung Le. "Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process." Sensors 23, no. 1 (2022): 76. http://dx.doi.org/10.3390/s23010076.

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This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way

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30

Jendernalik, W. "On analog comparators for CMOS digital pixel applications. A comparative study." Bulletin of the Polish Academy of Sciences Technical Sciences 64, no. 2 (2016): 271–78. http://dx.doi.org/10.1515/bpasts-2016-0030.

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Abstract Voltage comparator is the only - apart from the light-to-voltage converter - analog component in the digital CMOS pixel. In this work, the influence of the analog comparator nonidealities on the performance of the digital pixel has been investigated. In particular, two versions of the digital pixel have been designed in 0.35 μm CMOS technology, each using a different type of analog comparator. The properties of both versions have been compared. The first pixel utilizes a differential comparator with the increased size and improved electrical performance. The second structure is based

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31

Saha, Aloke, Narendra Deo Singh, and Dipankar Pal. "Efficient ternary comparator on CMOS technology." Microelectronics Journal 109 (March 2021): 105005. http://dx.doi.org/10.1016/j.mejo.2021.105005.

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32

Le, H. P., A. Zayegh, and J. Singh. "Performance analysis of optimised CMOS comparator." Electronics Letters 39, no. 11 (2003): 833. http://dx.doi.org/10.1049/el:20030546.

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33

Palmisano, G., and G. Palumbo. "High performance CMOS current comparator design." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 43, no. 12 (1996): 785–90. http://dx.doi.org/10.1109/82.553392.

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34

G., Vasudeva, Bharathi Gururaj, Mallikarjun P. Y., Nagaraj M. Lutimath, and Tripti R. Kulkarni. "CMOS Comparator Design using 90nm Technology." Engineering World 6 (December 18, 2024): 291–97. https://doi.org/10.37394/232025.2024.6.31.

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In many digital circuits the parameters gain and offset voltage are calculated. In our design of CMOS comparator with high performance using GPDK 90nm technology we optimize these parameters. The gain is calculated in AC analysis and also we measure area, delay, power dissipation, slew rate, rise time, fall time. The circuit is built by using PMOS and NMOS transistor with a body effect and we also measure mobility variation and channel length modulation based on the second order channel effects. A plot of gain and offset voltage also discussed in the paper. Finally a test schematic is built an

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35

Jieh-Tsorng Wu and B. A. Wooley. "A 100-MHz pipelined CMOS comparator." IEEE Journal of Solid-State Circuits 23, no. 6 (1988): 1379–85. http://dx.doi.org/10.1109/4.90034.

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36

Wang, Zhenhua. "Fully adjustable CMOS current window comparator." Microelectronics Journal 22, no. 5-6 (1991): 85–88. http://dx.doi.org/10.1016/0026-2692(91)90055-r.

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37

Baggini, B., F. Maloberti, and G. Palmisano. "Accurate low-power CMOS autozeroed comparator." Electronics Letters 28, no. 10 (1992): 916–18. http://dx.doi.org/10.1049/el:19920581.

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38

Ravezzi, L., D. Stoppa, and G. F. Dalla Betta. "Simple high-speed CMOS current comparator." Electronics Letters 33, no. 22 (1997): 1829. http://dx.doi.org/10.1049/el:19971250.

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39

Oktay, Aytar. "The Investigation of Auto-Zero Comparator Performance of Common Gate Differential Amplifier Based CMOS Inverter Circuit." Journal of Scientific, Technology and Engineering Research (JSTER) 1, no. 2 (2020): 25–32. https://doi.org/10.5281/zenodo.4069563.

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<strong>The Investigation of Auto-Zero Comparator Performance of Common Gate Differential Amplifier Based CMOS Inverter Circuit</strong> <em><strong>Abstract</strong> - In this study, the performance of the common gate difference amplifier cmos inverter circuit as an auto-zero comparator circuit was investigated using 0.18μm CMOS process model in the NCSU Design Kit of the Cadence IC5141 design program. The performance of the proposed structure was compared with traditional inverter circuit and darlington cmos inverter circuit. In accordance with the results of DC analysis, the voltage gain

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Priya, Nadendla Bindu, and Muralidharan Jayabhalan. "A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator." International Journal of Engineering and Advanced Technology 9, no. 1s5 (2019): 41–43. http://dx.doi.org/10.35940/ijeat.a1012.1291s519.

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Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5-bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Th

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Lu, Xiaohui. "Multisim-Based Digital Comparator Design and Performance Optimization." Applied and Computational Engineering 127, no. 1 (2025): 16–23. https://doi.org/10.54254/2755-2721/2025.20276.

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Nowadays, as many electronic products are moving towards increased portability and high reliability, higher demands are being placed on the various performance parameters of digital integrated circuits. Currently, digital integrated circuits are developing in the direction of low power consumption. Digital comparators are widely used in many areas of digital integrated circuits. Power consumption has an impact on many performance parameters of digital integrated circuits, so it is important to optimize power consumption during the design of digital integrated circuits. Therefore, a digital com

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Chen, Hao, Karlo Abnoosian, and Amin Salih Mohammed. "An Efficient Design of a Three-Layer Magnitude Comparator for Nano-Scale IoT Applications Based on QCA Technology." Journal of Nanoelectronics and Optoelectronics 19, no. 5 (2024): 459–64. http://dx.doi.org/10.1166/jno.2024.3587.

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The difficulty of further downscaling CMOS technology arises from the restriction of feature size reduction. Quantum-dot cellular automata (QCA) emerges as a paradigm-shifting successor to CMOS, heralding a new era of effective digital design at the nanoscale. It stands as an enticing frontier in nanoscale computing, with limited exploration into the realms of smaller QCA cells, elevated processing speeds, and more compact area requirements across diverse circuits. Within the intricate landscape of decoding circuits and process controllers, the binary comparator assumes a role of paramount sig

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Wei, Yuming, Xingyuan Tong, and Xin Xin. "A Fixed-Window Level-crossing ADC with a Single Comparator." Journal of Physics: Conference Series 2301, no. 1 (2022): 012026. http://dx.doi.org/10.1088/1742-6596/2301/1/012026.

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Abstract A fixed-window level-crossing analog-to-digital converter (LC-ADC) with a single comparator is proposed for the biomedical field. In this paper, a signal varying direction detection circuit is proposed to judge the trend of the input signal, instead of the low-precision comparator in the modified LC-ADC. The proposed LC-ADC utilizes only one continuous-time comparator instead of multiple comparators in traditional LC-ADC, leading to simplified implementation and significantly reducing the power consumption. The post-layout simulation results show that the power consumption of the prop

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Hari Kishore, K., K. DurgaKoteswara Rao, G. Manvith, K. Biswanth, and P. Alekhya. "Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology." International Journal of Engineering & Technology 7, no. 2.8 (2018): 222. http://dx.doi.org/10.14419/ijet.v7i2.8.10413.

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Of late, low power configuration took shape into the mostimportant concentrations in designing the latest VLSI circuits. By considering the same at the maximum priority, another outline of two-bit GDI based Magnitude or Digital Comparator are recommended and actualized with the assistance of Modified GDI transistors. Comparators are building blocks in advanced VLSI configuration circuits. In the current patterns the necessity for occupying less area in chip and low power compact devices. In this paper we introduced another Magnitude Comparator which willutilize low power, and gives a quick res

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Lakshmi N, Dr. Pavithra G, and Dr. T.C.Manjunath. "Design Of Three Stage Comparator Using 90nm Technology." international journal of engineering technology and management sciences 7, no. 6 (2023): 40–43. http://dx.doi.org/10.46647/ijetms.2023.v07i06.008.

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In this paper, the design of three stage comparator using 90nm technology is presented. The comparator is one of the block that limits the speed of the converter, its optimization is crucial and important and design of Analog-to-Digital Converter (ADC),is the speed limiting element in comparator. It describes the schematic design of a three stage CMOS comparator to achieve lower power dissipation and a lower offset voltage, with high-speed operation. Test structure of the comparator are designed using GPDK 90nm. The three-stage comparator makes it possible to use NMOS input pairs in both the r

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Zhang, Huaxia, Yuewen Sun, Zijia Chen, and Zhifang Wu. "Design of a Nanosecond Voltage Comparator with PECL Logic for a Photon-Counting Radiation Imaging System Application." Science and Technology of Nuclear Installations 2023 (July 8, 2023): 1–12. http://dx.doi.org/10.1155/2023/6810882.

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In this paper, a nanosecond voltage comparator with PECL logic for a photon-counting radiation imaging system is presented. To realize a high-speed comparison of four gamma detector channels in a limited board space, quad comparators MAX9602 with PECL logic are chosen. Each of the four channels is coupled with a PECL to CMOS converter ICS508, which exports CMOS logic data for later use in an FPGA. Simulated findings for cobalt-60 with intensities ranging from 30 Ci to 300 Ci show little count loss caused by using a comparator and indicate ideal propagation delays at all source intensities. Whi

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Lin, Chun Wei, and Sheng Feng Lin. "Balanced low input impedances CMOS current comparator." IEICE Electronics Express 9, no. 17 (2012): 1378–83. http://dx.doi.org/10.1587/elex.9.1378.

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Ng, W. T., and C. A. T. Salama. "High-speed high-resolution CMOS voltage comparator." Electronics Letters 22, no. 6 (1986): 338. http://dx.doi.org/10.1049/el:19860232.

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Lam, H. M., and C. Y. Tsui. "High-performance single clock cycle CMOS comparator." Electronics Letters 42, no. 2 (2006): 75. http://dx.doi.org/10.1049/el:20063083.

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Mukhopadhyay, Abhijit Kumar, and Subhramita Basak. "A Very Fast Modular Digital CMOS Comparator." Advanced Science, Engineering and Medicine 9, no. 4 (2017): 298–306. http://dx.doi.org/10.1166/asem.2017.2014.

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