Log in

Relevant bibliographies by topics / CMOS compatible fabrication / Journal articles

To see the other types of publications on this topic, follow the link: CMOS compatible fabrication.

Journal articles on the topic 'CMOS compatible fabrication'

Author: Grafiati

Published: 6 September 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'CMOS compatible fabrication.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Buyong, Muhamad Ramdzan, Norazreen Abd Aziz, and Burhanuddin Yeop Majlis. "Characterization and Optimization of Seals-Off for Very Low Pressure Sensors (VLPS) Fabricated by CMOS MEMS Process." Advanced Materials Research 74 (June 2009): 231–34. http://dx.doi.org/10.4028/www.scientific.net/amr.74.231.

Full text

Abstract:

In the world of MEMS processing today, fabrications of membrane are performed using bulk micromachining (BMM). However these techniques not easiest to integrate with CMOS standard process due to not compatible of the processing flow. An attractive alternative deployment of surface micromachining (SMM). There is a trend to use surface micromachining to their advantage of simplicity in design and fabrication process compatibility. This paper presents process development of thin layer membrane for very low capacitive pressure sensor application. The structure of the membrane consists of parallel

APA, Harvard, Vancouver, ISO, and other styles

2

Bi, Cheng, and Yanfei Liu. "CMOS-Compatible Optoelectronic Imagers." Coatings 12, no. 11 (2022): 1609. http://dx.doi.org/10.3390/coatings12111609.

Full text

Abstract:

Silicon-based complementary metal oxide semiconductors have revolutionized the field of imaging, especially infrared imaging. Infrared focal plane array imagers are widely applied to night vision, haze imaging, food selection, semiconductor detection, and atmospheric pollutant detection. Over the past several decades, the CMOS integrated circuits modified by traditional bulk semiconductor materials as sensitivity sensors for optoelectronic imagers have been used for infrared imaging. However, traditional bulk semiconductor material-based infrared imagers are synthesized by complicated molecula

APA, Harvard, Vancouver, ISO, and other styles

3

Yu, Le, Yaozu Guo, Haoyu Zhu, Mingcheng Luo, Ping Han, and Xiaoli Ji. "Low-Cost Microbolometer Type Infrared Detectors." Micromachines 11, no. 9 (2020): 800. http://dx.doi.org/10.3390/mi11090800.

Full text

Abstract:

The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the C

APA, Harvard, Vancouver, ISO, and other styles

4

Kempf, P., R. Hadaway, and J. Kolk. "Complementary metal oxide semiconductor compatible high-voltage transistors." Canadian Journal of Physics 65, no. 8 (1987): 1003–8. http://dx.doi.org/10.1139/p87-161.

Full text

Abstract:

The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semi

APA, Harvard, Vancouver, ISO, and other styles

5

Rasmussen, A., M. Gaitan, L. E. Locascio, and M. E. Zaghloul. "Fabrication techniques to realize CMOS-compatible microfluidic microchannels." Journal of Microelectromechanical Systems 10, no. 2 (2001): 286–97. http://dx.doi.org/10.1109/84.925785.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Lv, Hongming, Huaqiang Wu, Jinbiao Liu, et al. "Inverted process for graphene integrated circuits fabrication." Nanoscale 6, no. 11 (2014): 5826–30. http://dx.doi.org/10.1039/c3nr06904d.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Wu, Wenhao, Yu Yu, Wei Liu, and Xinliang Zhang. "Fully integrated CMOS-compatible polarization analyzer." Nanophotonics 8, no. 3 (2019): 467–74. http://dx.doi.org/10.1515/nanoph-2018-0205.

Full text

Abstract:

AbstractPolarization measurement has been widely used in material characterization, medical diagnosis and remote sensing. However, existing commercial polarization analyzers are either bulky schemes or operate in non-real time. Recently, various polarization analyzers have been reported using metal metasurface structures, which require elaborate fabrication and additional detection devices. In this paper, a compact and fully integrated silicon polarization analyzer with a photonic crystal-like metastructure for polarization manipulation and four subsequent on-chip photodetectors for light-curr

APA, Harvard, Vancouver, ISO, and other styles

8

AGARWAL, AJAY, N. BALASUBRAMANIAN, N. RANGANATHAN, and R. KUMAR. "SILICON NANOWIRES FORMATION IN CMOS COMPATIBLE MANNER." International Journal of Nanoscience 05, no. 04n05 (2006): 445–51. http://dx.doi.org/10.1142/s0219581x06004619.

Full text

Abstract:

We present CMOS compatible fabrication technique for silicon nanowire ( SiNW ) on bulk silicon wafers. Our method uses saw-tooth etch-profiles of fins followed by self-limiting oxidation to form vertically self-aligned horizontal SiNW down to 5 nm diameter. The concept of modifying the cross-section shape of SiNW from triangular to circular and the ability to achieve desired nanowire diameter are unique in this work. Nanowires formed by such technique can be utilized to realize several nanoelectronics devices like gate-all-around transistor, single-electron-transistor, etc.; NEMS and bio-medic

APA, Harvard, Vancouver, ISO, and other styles

9

Xiong, Chunle, Bryn Bell, and Benjamin J. Eggleton. "CMOS-compatible photonic devices for single-photon generation." Nanophotonics 5, no. 3 (2016): 427–39. http://dx.doi.org/10.1515/nanoph-2016-0022.

Full text

Abstract:

AbstractSources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic

APA, Harvard, Vancouver, ISO, and other styles

10

Kang, G. B., J. M. Park, S. G. Kim, et al. "Fabrication and characterisation of CMOS compatible silicon nanowire biosensor." Electronics Letters 44, no. 16 (2008): 953. http://dx.doi.org/10.1049/el:20081876.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Cuiling Gong and Tim Hogan. "CMOS Compatible Fabrication Processes for the Digital Micromirror Device." IEEE Journal of the Electron Devices Society 2, no. 3 (2014): 27–32. http://dx.doi.org/10.1109/jeds.2014.2309129.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Potts, A., G. J. Parker, J. J. Baumberg, and P. A. J. de Groot. "CMOS compatible fabrication methods for submicron Josephson junction qubits." IEE Proceedings - Science, Measurement and Technology 148, no. 5 (2001): 225–28. http://dx.doi.org/10.1049/ip-smt:20010395.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Ray, Vishva, Ramkumar Subramanian, Pradeep Bhadrachalam, Liang-Chieh Ma, Choong-Un Kim, and Seong Jin Koh. "CMOS-compatible fabrication of room-temperature single-electron devices." Nature Nanotechnology 3, no. 10 (2008): 603–8. http://dx.doi.org/10.1038/nnano.2008.267.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Bolten, Jens, Jens Hofrichter, Nikolaj Moll, et al. "CMOS compatible cost-efficient fabrication of SOI grating couplers." Microelectronic Engineering 86, no. 4-6 (2009): 1114–16. http://dx.doi.org/10.1016/j.mee.2008.11.038.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Zhou, Huajie, Yi Song, Qiuxia Xu, Yongliang Li, and Huaxiang Yin. "Fabrication of Bulk-Si FinFET using CMOS compatible process." Microelectronic Engineering 94 (June 2012): 26–28. http://dx.doi.org/10.1016/j.mee.2012.01.004.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Koczorowski, W., P. Kuświk, M. Przychodnia, et al. "CMOS- compatible fabrication method of graphene-based micro devices." Materials Science in Semiconductor Processing 67 (August 2017): 92–97. http://dx.doi.org/10.1016/j.mssp.2017.05.021.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Xie, Sheng, Xuetao Luo, Luhong Mao, and Haiou Li. "Design, Fabrication, and Modeling of CMOS-Compatible Double Photodiode." Transactions of Tianjin University 23, no. 2 (2017): 163–67. http://dx.doi.org/10.1007/s12209-017-0038-1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Zhang Chi, 张弛, та 肖淑敏 Xiao Shumin. "介质超构表面的CMOS兼容制备工艺的进展". Acta Optica Sinica 43, № 8 (2023): 0822003. http://dx.doi.org/10.3788/aos230489.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Mujeeb-U-Rahman, Muhammad, Dvin Adalian, and Axel Scherer. "Fabrication of Patterned Integrated Electrochemical Sensors." Journal of Nanotechnology 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/467190.

Full text

Abstract:

Fabrication of integrated electrochemical sensors is an important step towards realizing fully integrated and truly wireless platforms for many local, real-time sensing applications. Micro/nanoscale patterning of small area electrochemical sensor surfaces enhances the sensor performance to overcome the limitations resulting from their small surface area and thus is the key to the successful miniaturization of integrated platforms. We have demonstrated the microfabrication of electrochemical sensors utilizing top-down lithography and etching techniques on silicon and CMOS substrates. This choic

APA, Harvard, Vancouver, ISO, and other styles

20

Vaha-Heikkila, T., and M. Ylonen. "$G$-Band Distributed Microelectromechanical Components Based on CMOS Compatible Fabrication." IEEE Transactions on Microwave Theory and Techniques 56, no. 3 (2008): 720–28. http://dx.doi.org/10.1109/tmtt.2008.916885.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Li, Ying, Jun Yu, Hao Wu, and Zhenan Tang. "Design and fabrication of a CMOS-compatible MHP gas sensor." AIP Advances 4, no. 3 (2014): 031339. http://dx.doi.org/10.1063/1.4869616.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Khondaker, Saiful I. "Parallel Fabrication of CMOS Compatible Single Walled Carbon Nanotube Devices." Reviews in Nanoscience and Nanotechnology 1, no. 3 (2012): 187–99. http://dx.doi.org/10.1166/rnn.2012.1013.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Yin, Mei, Wei Yang, Yanping Li, Xingjun Wang, and Hongbin Li. "CMOS-compatible and fabrication-tolerant MMI-based polarization beam splitter." Optics Communications 335 (January 2015): 48–52. http://dx.doi.org/10.1016/j.optcom.2014.08.060.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Zhu, Huixian, Tai-Chin Lo, Ralf Lenigk, and Reinhard Renneberg. "Fabrication of a novel oxygen sensor with CMOS compatible processes." Sensors and Actuators B: Chemical 46, no. 2 (1998): 155–59. http://dx.doi.org/10.1016/s0925-4005(98)00044-6.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Pakula, L. S., H. Yang, H. T. M. Pham, P. J. French, and P. M. Sarro. "Fabrication of a CMOS compatible pressure sensor for harsh environments." Journal of Micromechanics and Microengineering 14, no. 11 (2004): 1478–83. http://dx.doi.org/10.1088/0960-1317/14/11/007.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Ng, E. J., T. Myint, N. Shen, et al. "High density vertical silicon NEM switches with CMOS-compatible fabrication." Electronics Letters 47, no. 13 (2011): 759–60. http://dx.doi.org/10.1049/el.2011.1073.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Koryazhkina, Maria N., Dmitry O. Filatov, Stanislav V. Tikhov, et al. "Electrical Characteristics of CMOS-Compatible SiOx-Based Resistive-Switching Devices." Nanomaterials 13, no. 14 (2023): 2082. http://dx.doi.org/10.3390/nano13142082.

Full text

Abstract:

The electrical characteristics and resistive switching properties of memristive devices have been studied in a wide temperature range. The insulator and electrode materials of these devices (silicon oxide and titanium nitride, respectively) are fully compatible with conventional complementary metal-oxide-semiconductor (CMOS) fabrication processes. Silicon oxide is also obtained through the low-temperature chemical vapor deposition method. It is revealed that the as-fabricated devices do not require electroforming but their resistance state cannot be stored before thermal treatment. After the t

APA, Harvard, Vancouver, ISO, and other styles

28

Erfanian, Alireza, Hamed Mehrara, Mahdi Khaje, and Ahmad Afifi. "A room temperature 2 × 128 PtSi/Si-nanostructure photodetector array compatible with CMOS process." Sensor Review 35, no. 3 (2015): 282–86. http://dx.doi.org/10.1108/sr-11-2014-0736.

Full text

Abstract:

Purpose – The purpose of this paper is to demonstrate a successful fabrication of 2 × 128 linear array of typical infrared (IR) detectors made of p-type tSi/porous Si Schottky barrier. Design/methodology/approach – Using metal-assisted chemical etching (MaCE) as a unique approach, a sample definition of a porous Si nanostructure region for fabricating of any high-density photodetectors array has been formulated. Besides, the uniformity of pixels at different position along the array has been confirmed by optical images and measurements of photocurrent in IR regime at room temperature. Findings

APA, Harvard, Vancouver, ISO, and other styles

29

Tang, Xiaoyu, Tao Hua, Yujie Liu, and Zhezhe Han. "Heterogeneous CMOS Integration of InGaAs-OI nMOSFETs and Ge pMOSFETs Based on Dual-Gate Oxide Technique." Micromachines 13, no. 11 (2022): 1806. http://dx.doi.org/10.3390/mi13111806.

Full text

Abstract:

A compatible fabrication technology for integrating InGaAs nMOSFETs and Ge pMOSFETs is developed based on the development of the two-step gate oxide fabrication strategy. The direct wafer bonding method was utilized to obtain the InGaAs-Insulator-Ge structure, providing the heterogeneous channels for CMOS integration. Superior transistor characteristics were achieved by optimizing the InGaAs gate oxide with a self-cleaning process in atomic layer deposition, and modifying the Ge gate oxide by the ozone post oxidation (OPO) technique, in the sequential two-step gate oxide fabrication process. W

APA, Harvard, Vancouver, ISO, and other styles

30

Pérez-Campos, A., G. F. Iriarte, J. Hernando-Garcia, and F. Calle. "Post-CMOS compatible high-throughput fabrication of AlN-based piezoelectric microcantilevers." Journal of Micromechanics and Microengineering 25, no. 2 (2015): 025003. http://dx.doi.org/10.1088/0960-1317/25/2/025003.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Smith, Melissa Alyson, Isaac Weaver, and Mordechai Rothschild. "Wafer-scale fabrication of CMOS-compatible, high aspect ratio encapsulated nanochannels." Journal of Vacuum Science & Technology B 36, no. 5 (2018): 051801. http://dx.doi.org/10.1116/1.5034463.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Musick, Katherine M., Joel R. Wendt, Paul J. Resnick, Michael B. Sinclair, and D. Bruce Burckel. "Assessing the manufacturing tolerances and uniformity of CMOS compatible metamaterial fabrication." Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 36, no. 1 (2018): 011208. http://dx.doi.org/10.1116/1.5009918.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Vitale, Wolfgang A., Clara F. Moldovan, Antonio Paone, Andreas Schüler, and Adrian M. Ionescu. "Fabrication of CMOS-compatible abrupt electronic switches based on vanadium dioxide." Microelectronic Engineering 145 (September 2015): 117–19. http://dx.doi.org/10.1016/j.mee.2015.03.055.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Xiao, Jing, Fuchuan Song, Kijeong Han, and Sang-Woo Seo. "Fabrication of CMOS-compatible optical filter arrays using gray-scale lithography." Journal of Micromechanics and Microengineering 22, no. 2 (2012): 025006. http://dx.doi.org/10.1088/0960-1317/22/2/025006.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Yu, Huiyang, Xuke Yu, and Yifeng Li. "Design, fabrication and optimization of a CMOS compatible capacitive pressure sensor." Journal of Micromechanics and Microengineering 29, no. 2 (2019): 025009. http://dx.doi.org/10.1088/1361-6439/aaf599.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Karam, J. M., B. Courtois, and J. M. Paret. "Collective fabrication of microsystems compatible with CMOS through the CMP service." Materials Science and Engineering: B 35, no. 1-3 (1995): 219–23. http://dx.doi.org/10.1016/0921-5107(95)01337-7.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Sugimoto, Yasuhiro, Hiroyuki Hara, Tsutomu Koyanagi, and Hiroyuki Miyakawa. "Fabrication and Evaluation of the ECL/TTL Compatible BI-CMOS Gate Array." IEEJ Transactions on Electronics, Information and Systems 108, no. 12 (1988): 981–88. http://dx.doi.org/10.1541/ieejeiss1987.108.12_981.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Roy, Avisek, Mehdi Azadmehr, Bao Q. Ta, Philipp Häfliger, and Knut E. Aasmundtveit. "Design and Fabrication of CMOS Microstructures to Locally Synthesize Carbon Nanotubes for Gas Sensing." Sensors 19, no. 19 (2019): 4340. http://dx.doi.org/10.3390/s19194340.

Full text

Abstract:

Carbon nanotubes (CNTs) can be grown locally on custom-designed CMOS microstructures to use them as a sensing material for manufacturing low-cost gas sensors, where CMOS readout circuits are directly integrated. Such a local CNT synthesis process using thermal chemical vapor deposition (CVD) requires temperatures near 900 °C, which is destructive for CMOS circuits. Therefore, it is necessary to ensure a high thermal gradient around the CNT growth structures to maintain CMOS-compatible temperature (below 300 °C) on the bulk part of the chip, where readout circuits are placed. This paper present

APA, Harvard, Vancouver, ISO, and other styles

39

Faruque, M. O., R. Al Mahmud, and R. H. Sagor. "CMOS Compatible Plasmonic Refractive Index Sensor based on Heavily Doped Silicon Waveguide." Engineering, Technology & Applied Science Research 10, no. 1 (2020): 5295–300. http://dx.doi.org/10.48084/etasr.3264.

Full text

Abstract:

In this study, a plasmonic refractive index (RI) sensor using heavily n-doped silicon waveguide is designed and numerically simulated using finite element method (FEM). The reported sensor is based on gratings inside a heavily doped silicon waveguide structure instead of a conventional metal-insulator-metal structure. This feature enables the device to overcome the limitations of conventional plasmonic devices like optical losses, polarization management, etc. Besides, it makes the device compatible with Complementary Metal Oxide Semiconductor (CMOS) technology and thus provides an easier way

APA, Harvard, Vancouver, ISO, and other styles

40

Tabassum, Natasha, Mounika Kotha, Vidya Kaushik, et al. "On-Demand CMOS-Compatible Fabrication of Ultrathin Self-Aligned SiC Nanowire Arrays." Nanomaterials 8, no. 11 (2018): 906. http://dx.doi.org/10.3390/nano8110906.

Full text

Abstract:

The field of semiconductor nanowires (NWs) has become one of the most active and mature research areas. However, progress in this field has been limited, due to the difficulty in controlling the density, orientation, and placement of the individual NWs, parameters important for mass producing nanodevices. The work presented herein describes a novel nanosynthesis strategy for ultrathin self-aligned silicon carbide (SiC) NW arrays (≤ 20 nm width, 130 nm height and 200–600 nm variable periodicity), with high quality (~2 Å surface roughness, ~2.4 eV optical bandgap) and reproducibility at predeter

APA, Harvard, Vancouver, ISO, and other styles

41

Hu, Juejun, Vladimir Tarasov, Nathan Carlie, et al. "Si-CMOS-compatible lift-off fabrication of low-loss planar chalcogenide waveguides." Optics Express 15, no. 19 (2007): 11798. http://dx.doi.org/10.1364/oe.15.011798.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Smith, A. D., Q. Li, A. Anderson, et al. "Toward CMOS compatible wafer-scale fabrication of carbon-based microsupercapacitors for IoT." Journal of Physics: Conference Series 1052 (July 2018): 012143. http://dx.doi.org/10.1088/1742-6596/1052/1/012143.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Koppinen, P. J., M. D. Stewart, and Neil M. Zimmerman. "Fabrication and Electrical Characterization of Fully CMOS-Compatible Si Single-Electron Devices." IEEE Transactions on Electron Devices 60, no. 1 (2013): 78–83. http://dx.doi.org/10.1109/ted.2012.2227322.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Li, Y., W. Parkes, L. I. Haworth, et al. "Anodic Ta2O5 for CMOS compatible low voltage electrowetting-on-dielectric device fabrication." Solid-State Electronics 52, no. 9 (2008): 1382–87. http://dx.doi.org/10.1016/j.sse.2008.04.030.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Li, Nanxi, Chong Pei Ho, Shiyang Zhu, Yuan Hsing Fu, Yao Zhu, and Lennon Yao Ting Lee. "Aluminium nitride integrated photonics: a review." Nanophotonics 10, no. 9 (2021): 2347–87. http://dx.doi.org/10.1515/nanoph-2021-0130.

Full text

Abstract:

Abstract Integrated photonics based on silicon has drawn a lot of interests, since it is able to provide compact solution for functional devices, and its fabrication process is compatible with the mature complementary metal-oxide-semiconductor (CMOS) fabrication technology. In the meanwhile, silicon material itself has a few limitations, including an indirect bandgap of 1.1 eV, transparency wavelength of >1.1 μm, and insignificant second-order nonlinear optical property. Aluminum nitride (AlN), as a CMOS-compatible material, can overcome these limitations. It has a wide bandgap of 6.2 eV, a

APA, Harvard, Vancouver, ISO, and other styles

46

González-Fernández, Alfredo A., Mariano Aceves-Mijares, Oscar Pérez-Díaz, Joaquin Hernández-Betanzos, and Carlos Domínguez. "Embedded Silicon Nanoparticles as Enabler of a Novel CMOS-Compatible Fully Integrated Silicon Photonics Platform." Crystals 11, no. 6 (2021): 630. http://dx.doi.org/10.3390/cryst11060630.

Full text

Abstract:

The historical bottleneck for truly high scale integrated photonics is the light emitter. The lack of monolithically integrable light sources increases costs and reduces scalability. Quantum phenomena found in embedded Si particles in the nanometer scale is a way of overcoming the limitations for bulk Si to emit light. Integrable light sources based in Si nanoparticles can be obtained by different CMOS (Complementary Metal Oxide Semiconductor) -compatible materials and techniques. Such materials in combination with Si3N4 photonic elements allow for integrated Si photonics, in which photodetect

APA, Harvard, Vancouver, ISO, and other styles

47

Ranacher, Christian, Cristina Consani, Andreas Tortschanoff, et al. "A CMOS Compatible Pyroelectric Mid-Infrared Detector Based on Aluminium Nitride." Sensors 19, no. 11 (2019): 2513. http://dx.doi.org/10.3390/s19112513.

Full text

Abstract:

The detection of infrared radiation is of great interest for a wide range of applications, such as absorption sensing in the infrared spectral range. In this work, we present a CMOS compatible pyroelectric detector which was devised as a mid-infrared detector, comprising aluminium nitride (AlN) as the pyroelectric material and fabricated using semiconductor mass fabrication processes. To ensure thermal decoupling of the detector, the detectors are realized on a Si3N4/SiO2 membrane. The detectors have been tested at a wavelength close to the CO2 absorption region in the mid-infrared. Devices wi

APA, Harvard, Vancouver, ISO, and other styles

48

Filipovic, Lado, and Siegfried Selberherr. "Application of Two-Dimensional Materials towards CMOS-Integrated Gas Sensors." Nanomaterials 12, no. 20 (2022): 3651. http://dx.doi.org/10.3390/nano12203651.

Full text

Abstract:

During the last few decades, the microelectronics industry has actively been investigating the potential for the functional integration of semiconductor-based devices beyond digital logic and memory, which includes RF and analog circuits, biochips, and sensors, on the same chip. In the case of gas sensor integration, it is necessary that future devices can be manufactured using a fabrication technology which is also compatible with the processes applied to digital logic transistors. This will likely involve adopting the mature complementary metal oxide semiconductor (CMOS) fabrication techniqu

APA, Harvard, Vancouver, ISO, and other styles

49

Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (1987): 982–86. http://dx.doi.org/10.1139/p87-156.

Full text

Abstract:

We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n subs

APA, Harvard, Vancouver, ISO, and other styles

50

Kuo, Yi-Shan, Shen-Yang Lee, Chia-Chin Lee, Shou-Wei Li, and Tien-Sheng Chao. "CMOS-Compatible Fabrication of Low-Power Ferroelectric Tunnel Junction for Neural Network Applications." IEEE Transactions on Electron Devices 68, no. 2 (2021): 879–84. http://dx.doi.org/10.1109/ted.2020.3045955.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!