Journal articles: 'CMOS Design'

1

ISMAIL, Z. M. A., and M. A. H. ABDUL-KARIM. "CMOS digital wattmeter design." International Journal of Electronics 63, no. 4 (1987): 631–40. http://dx.doi.org/10.1080/00207218708547349.

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Doan, C. H., S. Emami, A. M. Niknejad, and R. W. Brodersen. "Millimeter-wave CMOS design." IEEE Journal of Solid-State Circuits 40, no. 1 (2005): 144–55. http://dx.doi.org/10.1109/jssc.2004.837251.

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McGrail, J. M. "CMOS Gate Array Design." Microelectronics International 5, no. 3 (1988): 14–16. http://dx.doi.org/10.1108/eb044335.

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Filanovsky, I. M., and H. Baltes. "CMOS Schmitt trigger design." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 41, no. 1 (1994): 46–49. http://dx.doi.org/10.1109/81.260219.

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Radhakrishnan, D. "Design of CMOS circuits." IEE Proceedings G Circuits, Devices and Systems 138, no. 1 (1991): 83. http://dx.doi.org/10.1049/ip-g-2.1991.0016.

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Dieck-Assad, Graciano, José Manuel Rodríguez-Delgado, and Omar Israel González Peña. "Excel Methods to Design and Validate in Microelectronics (Complementary Metal–Oxide–Semiconductor, CMOS) for Biomedical Instrumentation Application." Sensors 21, no. 22 (2021): 7486. http://dx.doi.org/10.3390/s21227486.

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CMOS microelectronics design has evolved tremendously during the last two decades. The evolution of CMOS devices to short channel designs where the feature size is below 1000 nm brings a great deal of uncertainty in the way the microelectronics design cycle is completed. After the conceptual idea, developing a thinking model to understand the operation of the device requires a good “ballpark” evaluation of transistor sizes, decision making, and assumptions to fulfill the specifications. This design process has iterations to meet specifications that exceed in number of the available degrees of freedom to maneuver the design. Once the thinking model is developed, the simulation validation follows to test if the design has a good possibility of delivering a successful prototype. If the simulation provides a good match between specifications and results, then the layout is developed. This paper shows a useful open science strategy, using the Excel software, to develop CMOS microelectronics hand calculations to verify a design, before performing the computer simulation and layout of CMOS analog integrated circuits. The full methodology is described to develop designs of passive components, as well as CMOS amplifiers. The methods are used in teaching CMOS microelectronics to students of electronic engineering with industrial partner participation. This paper describes an exhaustive example of a low-voltage operational transconductance amplifier (OTA) design which is used to design an instrumentation amplifier. Finally, a test is performed using this instrumentation amplifier to implement a front-end signal conditioning device for CMOS-MEMS biomedical applications.

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Vidhyadharan, Abhay Sanjay, and Sanjay Vidhyadharan. "Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications." World Journal of Engineering 18, no. 5 (2021): 750–59. http://dx.doi.org/10.1108/wje-08-2020-0367.

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Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

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Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

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Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

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Wan Mohamad Sharif, Wan Mohd Hashimi, Mohd Faizul Md Idros, Syed Abdul Mutalib Al-Junid, et al. "Hybrid memristor-CMOS implementation of logic gates design using LTSpice." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 3 (2021): 2003. http://dx.doi.org/10.11591/ijece.v11i3.pp2003-2010.

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In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.

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Shigematsu, H., T. Hirose, F. Brewer, and M. Rodwell. "Millimeter-wave CMOS circuit design." IEEE Transactions on Microwave Theory and Techniques 53, no. 2 (2005): 472–77. http://dx.doi.org/10.1109/tmtt.2004.840758.

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Pedram, M., and Qing Wu. "Battery-powered digital CMOS design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10, no. 5 (2002): 601–7. http://dx.doi.org/10.1109/tvlsi.2002.801566.

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Shou, Xiaoqiang, Nader Kalantari, and Michael M. Green. "Design of CMOS Ternary Latches." IEEE Transactions on Circuits and Systems I: Regular Papers 53, no. 12 (2006): 2588–94. http://dx.doi.org/10.1109/tcsi.2006.885697.

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13

Sechler, R. F. "Interconnect design with VLSI CMOS." IBM Journal of Research and Development 39, no. 1.2 (1995): 23–31. http://dx.doi.org/10.1147/rd.391.0023.

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Niknejad, Ali M., Debopriyo Chowdhury, and Jiashu Chen. "Design of CMOS Power Amplifiers." IEEE Transactions on Microwave Theory and Techniques 60, no. 6 (2012): 1784–96. http://dx.doi.org/10.1109/tmtt.2012.2193898.

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Ren, M. Y., C. X. Zhang, and D. S. Sun. "Design of CMOS Instrumentation Amplifier." Procedia Engineering 29 (2012): 4035–39. http://dx.doi.org/10.1016/j.proeng.2012.01.615.

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Chandrakasan, A. P., S. Sheng, and R. W. Brodersen. "Low-power CMOS digital design." IEEE Journal of Solid-State Circuits 27, no. 4 (1992): 473–84. http://dx.doi.org/10.1109/4.126534.

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M. Surekha, V. HariKrishna, B. MadhuSudhan Reddy, G.Tejaswini, I.Rajasekhar, and K.Divya. "Efficient Approaches to Design Full Adder Using Domino Logic Technique." international journal of engineering technology and management sciences 7, no. 2 (2023): 283–88. http://dx.doi.org/10.46647/ijetms.2023.v07i02.033.

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Static CMOS and Domino CMOS Circuits are significantly used in high performance VLSI system. Designing a circuit with low power, high speed performance is one of the challenging aspects. In modern VLSI systems area efficient devices are utmost popular because most of the devices are becoming portable. This paper proposes One- bit full adder circuit is designed using CMOS based on mirror logic and Domino CMOS also designed based on same logic with LTSPICE at 180nm technology with 1.8V supply. This method provides better power and delay.

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Huang, Peihao. "Design and optimization of CMOS layout structure for improved semiconductor device performance." Journal of Physics: Conference Series 2649, no. 1 (2023): 012040. http://dx.doi.org/10.1088/1742-6596/2649/1/012040.

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Abstract CMOS layout structure plays a very important role in the field of semiconductor. Since the invention of CMOS technology in the 1970s, engineers have developed many other CMOS layout technologies based on it. This paper will also focus on the CMOS transistor layout structure, focusing on the analysis of three more important structures, demonstrating their impact on the performance of semiconductor devices. Before that, this paper will first introduce the basic theory of CMOS, such as the drift and diffusion of charge carriers in PN junctions, and the working principle of PMOS and NMOS, so as to facilitate us to further describe the optimization and improvement of CMOS structure. Then, the performance and characteristics of each structure are introduced in detail, and finally the comparison is made to highlight their advantages in technology and performance compared with traditional structures. In the future, CMOS structure layout will also become a hot spot, constantly creating more reasonable and advanced structures to improve semiconductor performance.

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V.P, Visanthi. "FULL ADDER CIRCUIT DESIGN WITH LOW POWER AND HIGH SPEED AT 0.25µM CMOS TECHNOLOGY USING TANNER EDA." International Journal Of Trendy Research In Engineering And Technology 07, no. 01 (2023): 46–48. http://dx.doi.org/10.54473/ijtret.2023.7109.

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A CMOS Full Adder is designed using Tanner EDA Tool based on 0.25µm CMOS Technology. In the arithmetic logic unit (ALU), the full adder cell is one of the most frequently utilized digital circuit components and the fundamental functional unit of all computational circuits. Right now, a lot of work has been done to improve the architecture and functionality of full adder circuit designs. In this research, two innovative 1-bit full adder cell designs are developed using ten transistors and 0.25mm CMOS technology (10-T). Tanner software tools will be used in the design of the CMOS full adder to simulate the schematic and layout as well as compare the schematic and layout for the purpose of determining precise design limitations. As part of this, we are going to perform the simulation of the CMOS full adder using T-SPICE of Tanner EDA and its layout design using the Microwind tool. The parameters such as power consumption, Area, Propagation Delay, and Power Delay Product (PDP) are evaluated to analyze the proposed one-bit full adder

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Awang Salleh, Dayang Nur Salmi Dharmiza, and Rohana Sapawi. "A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes." Applied Mechanics and Materials 833 (April 2016): 135–39. http://dx.doi.org/10.4028/www.scientific.net/amm.833.135.

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Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

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Bae, Jongsuk, Junghyun Ham, Haeryun Jung, Wonsub Lim, Sooho Jo, and Youngoo Yang. "Design of Two-Stage CMOS Power Amplifier." Journal of Korean Institute of Electromagnetic Engineering and Science 25, no. 9 (2014): 895–902. http://dx.doi.org/10.5515/kjkiees.2014.25.9.895.

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Juarez-Mendoza, Eduardo, Francisco Asahel del Angel-Diaz, Alejandro Diaz-Sanchez, and Esteban Tlelo-Cuautle. "CMOS Design of Chaotic Systems Using Biquadratic OTA-C Filters." Journal of Low Power Electronics and Applications 14, no. 1 (2024): 14. http://dx.doi.org/10.3390/jlpea14010014.

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This manuscript shows the CMOS design of Lorenz systems using operational transconductance amplifiers (OTAs). Two Lorenz systems are then synchronized in a master–slave topology and used to implement a CMOS secure communication system. The contribution is devoted to the correct design of first- and second-order OTA-C filters, using 180 nm CMOS technology, to guarantee chaotic behavior. First, Simulink is used to simulate a secure communication system using two Lorenz systems connected in a master–slave topology, which is tested using sinusoidal signals that are masked by chaotic signals. Second, the Lorenz systems are scaled to have amplitudes of the state variables below 1 Volt, to allow for CMOS design using OTA-C filters. The transconductances of the OTAs are tuned to accomplish a Laplace transfer function. In this manner, this work highlights the design of a second-order CMOS OTA-C filter, whose damping factor is tuned to generate appropriate chaotic behavior. Finally, chaotic masking is performed by designing a whole CMOS secure communication system by using OTA-C based Lorenz systems, and its SPICE simulation results show its appropriateness for hardware security applications.

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Ren, Ming Yuan, Li Tian, Wei Wang, Xiao Wei Liu, and Zhi Gang Mao. "Design of Pre-Amplifiers for Photoelectric Detector." Applied Mechanics and Materials 380-384 (August 2013): 3308–11. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3308.

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This paper presents the design of low noise CMOS pre-amplifiers based on photoelectric detection systems, which can directly affect the detecting precision of the whole systems. The design of pre-amplifier circuit from photoelectric detector was introduced. The photoelectric conversion circuit, amplifier circuit bandwidth, amplifier circuit noise, amplifier circuit stabilization and other questions were mainly discussed, and an amplifier circuit capable of effectively decreasing the noise, the temperature drift and a large dynamic range was designed. This paper analyzes the sources of photoelectric detection circuit internal noise, and gives the formulas of internal noise, designs a variable equivalent load photoelectric conversion circuit, and is verified by experiments. Then the result is used to reduce the noise of CMOS based operational amplifiers and finally implement the design work of pre-amp using 0.5μm CMOS Technology.

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Valencia-Ponce, Martín Alejandro, Esteban Tlelo-Cuautle, and Luis Gerardo de la Fraga. "On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms." Electronics 10, no. 24 (2021): 3148. http://dx.doi.org/10.3390/electronics10243148.

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In CMOS integrated circuit (IC) design, operational amplifiers are one of the most useful active devices to enhance applications in analog signal processing, signal conditioning and so on. However, due to the CMOS technology downscaling, along the very large number of design variables and their trade-offs, it results difficult to reach target specifications without the application of optimization methods. For this reason, this work shows the advantages of performing many-objective optimization and this algorithm is compared to the well-known mono- and multi-objective metaheuristics, which have demonstrated their usefulness in sizing CMOS ICs. Three CMOS operational transconductance amplifiers are the case study in this work; they were sized by applying mono-, multi- and many-objective algorithms. The well-known non-dominated sorting genetic algorithm version 3 (NSGA-III) and the many-objective metaheuristic-based on the R2 indicator (MOMBI-II) were applied to size CMOS amplifiers and their sized solutions were compared to mono- and multi-objective algorithms. The CMOS amplifiers were optimized considering five targets, associated to a figure of merit (FoM), differential gain, power consumption, common-mode rejection ratio and total silicon area. The designs were performed using UMC 180 nm CMOS technology. To show the advantage of applying many-objective optimization algorithms to size CMOS amplifiers, the amplifier with the best performance was used to design a fractional-order integrator based on OTA-C filters. A variation analysis considering the process, the voltage and temperature (PVT) and a Monte Carlo analysis were performed to verify design robustness. Finally, the OTA-based fractional-order integrator was used to design a fractional-order chaotic oscillator, showing good agreement between numerical and SPICE simulations.

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Roy, Avisek, Mehdi Azadmehr, Bao Q. Ta, Philipp Häfliger, and Knut E. Aasmundtveit. "Design and Fabrication of CMOS Microstructures to Locally Synthesize Carbon Nanotubes for Gas Sensing." Sensors 19, no. 19 (2019): 4340. http://dx.doi.org/10.3390/s19194340.

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Carbon nanotubes (CNTs) can be grown locally on custom-designed CMOS microstructures to use them as a sensing material for manufacturing low-cost gas sensors, where CMOS readout circuits are directly integrated. Such a local CNT synthesis process using thermal chemical vapor deposition (CVD) requires temperatures near 900 °C, which is destructive for CMOS circuits. Therefore, it is necessary to ensure a high thermal gradient around the CNT growth structures to maintain CMOS-compatible temperature (below 300 °C) on the bulk part of the chip, where readout circuits are placed. This paper presents several promising designs of CNT growth microstructures and their thermomechanical analyses (by ANSYS Multiphysics software) to check the feasibility of local CNT synthesis in CMOS. Standard CMOS processes have several conductive interconnecting metal and polysilicon layers, both being suitable to serve as microheaters for local resistive heating to achieve the CNT growth temperature. Most of these microheaters need to be partially or fully suspended to produce the required thermal isolation for CMOS compatibility. Necessary CMOS post-processing steps to realize CNT growth structures are discussed. Layout designs of the microstructures, along with some of the microstructures fabricated in a standard AMS 350 nm CMOS process, are also presented in this paper.

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Nebhen, Jamel, Julien Dubois, Sofiene Mansouri, and Dominique Ginhac. "Low-noise and low power CMOS photoreceptor using split-length MOSFET." Journal of Electrical Engineering 70, no. 6 (2019): 480–85. http://dx.doi.org/10.2478/jee-2019-0081.

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Abstract This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply voltage, achieves a noise floor of 2μV/⎷Hz within the frequency range from 1 Hz to 10 kHz. The current consumption of the CMOS photoreceptor is 541 nA. This paper shows the need for the design of phototransduction circuit at low voltage, low noise and how these constraints are reflected in the design of CMOS vision sensor.

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He, Xinyu. "Design of CMOS circuits through transistor sizing techniques." Applied and Computational Engineering 12, no. 1 (2023): 1–12. http://dx.doi.org/10.54254/2755-2721/12/20230279.

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With the increasingly diverse functional requirements of contemporary electronic products, the complexity of CMOS circuits often used in chips becomes higher and the number of transistors used increases. To solve the resulting performance problems of CMOS circuits, researchers have searched for many transistor sizing technologies. This paper summarizes three methods of CMOS circuit optimization. The paper introduces these three methods in terms of principle, effect, and application scenarios, and compares them respectively. Through analysis and simulation, it can be found that the use of these methods in circuit design can effectively achieve the purpose of improving speed, reducing power consumption, and improving the overall performance of the circuit. This lays a solid foundation for finally being able to present a good product with excellent performance and enhance the market competitiveness of the product. CMOS circuits are widely used, and circuit optimization is of great importance to the overall circuit design, and better optimization methods can even promote the development of the entire electronics and chip manufacturing fields.

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Prof. Nikhil Surkar. "Design and Analysis of Optimized Fin-FETs." International Journal of New Practices in Management and Engineering 4, no. 04 (2015): 01–06. http://dx.doi.org/10.17762/ijnpme.v4i04.39.

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Semiconductor industry greatly depends on CMOS technology and now needs competent technology with handful benefits. This paper examines and analyzes the modern FINFET technology. This analysis is performed through 9 stages Ring Oscillator equipped with FINFET. Performance is analyzed by comparing the proposed structure with CMOS based 9 stage Ring Oscillator at the nano-scale level of abstraction.

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Xu, Ni, Woogeun Rhee, and Zhihua Wang. "Semidigital PLL Design for Low-Cost Low-Power Clock Generation." Journal of Electrical and Computer Engineering 2011 (2011): 1–9. http://dx.doi.org/10.1155/2011/235843.

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This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

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Chen, Jiahao. "Integrated circuit design based on CMOS technology principle and its application in GPU." Theoretical and Natural Science 12, no. 1 (2023): 141–46. http://dx.doi.org/10.54254/2753-8818/12/20230454.

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In today's society, the application of integrated circuit technology can be seen everywhere, especially in the past two decades. This paper mainly studies the principle and design of CMOS devices in IC technology and discusses the research and analysis of the acceleration algorithm of IC design. This paper adopts the research method of literature review and analysis to summarize the existing research results. This paper first introduces the development background of integrated circuit technology and the importance of CMOS technology. Subsequently, the concept and interconnection principle of CMOS device, and the combined circuit design and sequential logic circuit design principle of dynamic and static CMOS are explained in detail. Then, the application principle of CMOS technology in GPU is analyzed, and its specific application in GPU acceleration algorithm is analyzed. Finally, the application of CMOS technology in integrated circuits and its application and acceleration effect are summarized.

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Prajapati, Pankaj P., Anilkumar J. Kshatriya, Sureshbhai L. Bharvad, and Abhay B. Upadhyay. "Performance analysis of CMOS based analog circuit design with PVR variation." Bulletin of Electrical Engineering and Informatics 12, no. 1 (2023): 141–48. http://dx.doi.org/10.11591/eei.v12i1.4357.

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Process, supply voltage, and temperature (PVT) are three important factors which contribute to performance variation of the complementary metal–oxide–semiconductor (CMOS) based analog circuits. In this paper, CMOS based analog circuit design with the PVT variation effects are explored. The effects of the PVT variation on the performance of CMOS based analog circuits are introduced. The optimization of CMOS based analog circuits such as differential amplifier (DA) and two-stage operational amplifier (op amp) circuits with PVT variations with different algorithms such as cockoo search (CS), particle swam optimization (PSO), hybrid CSPSO, and differential evaluation (DE) algorithms is presented. Each algorithm is implemented using the C programming language, interfaced with Ngspice circuit simulator, and tested on the Intel®core™ i5, 2.40 GHz processor with 8 GB internal RAM using the Ubuntu operating system (OS). The result shows PVT variation affects the performance of CMOS circuit.

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Srivastava, A., and K. Venkatapathy. "Design and Implementation of a Low Power Ternary Full Adder." VLSI Design 4, no. 1 (1996): 75–81. http://dx.doi.org/10.1155/1996/94696.

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In this work, the design and implementation of a low power ternary full adder are presented in CMOS technology. In a ternary full adder design, the basic building blocks, the positive ternary inverter (PTI) and negative ternary inverter (NTI) are developed using a CMOS inverter and pass transistors. In designs of PTI and NTI, W/L ratios of transistors have been varied for their optimum performance. The ternary full adder and its building blocks have been simulated with SPICE 2G.6 using the MOSIS model parameters. The rise and fall times of PTI show an improvement by a factor of 14 and 4, respectively, and that of the NTI by a factor of nearly 4 and 17, respectively over that of earlier designs implemented in depletion-enhancement CMOS (DECMOS) technology. The noise margins improve by a factor of nearly 2 in PTI and NTI, respectively.The ternary full adder has been fabricated in MOSIS two micron n-well CMOS technology. The full adder and its building blocks, NTI and PTI have been tested experimentally for static and dynamic performance, compared with the SPICE simulated behavior, and close agreement is observed.The ternary-valued logic circuits designed in the present work which do not use depletion mode MOSFETS perform better than that implemented earlier in DECMOS technology. The present design is fully compatible with the current CMOS technology, uses fewer components and dissipates power in the microwatt range.

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Nasre, Vrushali G., and G. M. Asutkar G. M. Asutkar. "CMOS Band Gap Reference (BGR) Design Techniques: A Review." Indian Journal of Applied Research 3, no. 8 (2011): 235–38. http://dx.doi.org/10.15373/2249555x/aug2013/76.

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Zhan, Song, Bao Cheng Yu, and Chun Mei Wang. "CMOS Image Sensor-Driven Design Based on TMS320DM368." Applied Mechanics and Materials 687-691 (November 2014): 3097–101. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3097.

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A structure of video surveillance platform has been set up based on TI's TMS320DM368 (the following referred to as DM368).The driver of CMOS image sensor has been designed ,according to the valid image data read and timing requirements in the CMOS image sensor. A Aptina's CMOS image sensor AR0130 has been adopted. Acooriding its clock configuration, the ranks’ timing control, the output resolution and other design requirements, a method based on the scanning of ranks clock to divide the valid image area has been applied to set parameters for achieving the hardware device driver. The results show that the device can be normal work under the drive, and video signal outputs stable.

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Hsu, Hsiang Chen, Hui Yu Lee, and Yu Cha Hsu. "Thermal-Hygro-Mechanical Design for CMOS Image Sensor." Key Engineering Materials 364-366 (December 2007): 1151–56. http://dx.doi.org/10.4028/www.scientific.net/kem.364-366.1151.

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The characteristic of overall structure for CMOS image sensor has been studied in this research. A three-dimensional solid model of CMOS image sensor based on finite element ANSYS software is developed to predict the thermo-induced strain and the stress induced by moisture absorption. The predicted thermal-induced displacements were found to be very good agreement with the Moiré interferometer experimental in-plane deformation. The developed finite element 3D model, therefore, is applied to simulate the mechanism of thermal and hygroscopic stresses based on JEDEC pre-condition standard JESD22-A120. A series of comprehensive parametric studies were conducted in this research. The design rules for thermal optimization of CMOS image senor are summarized.

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Choi, Jin-Ho. "Design of CMOS Temperature Sensor Using Ring Oscillator." Journal of the Korea Institute of Information and Communication Engineering 19, no. 9 (2015): 2081–86. http://dx.doi.org/10.6109/jkiice.2015.19.9.2081.

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Poovannan, E., P. Ramani, and M. Ramkumar Prabhu. "Arithmetic CMOS Design with Better Properties." Research Journal of Applied Sciences, Engineering and Technology 5, no. 5 (2013): 1491–95. http://dx.doi.org/10.19026/rjaset.5.4893.

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Kalyani, P. "Low Power Design for CMOS Circuits." CVR Journal of Science & Technology 03, no. 1 (2012): 29–31. http://dx.doi.org/10.32377/cvrjst0306.

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Song, Ming Xin, Shan Shan Wang, and Guo Dong Sun. "CMOS Low Power Ring VCO Design." Advanced Materials Research 981 (July 2014): 70–73. http://dx.doi.org/10.4028/www.scientific.net/amr.981.70.

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A design project of voltage controlled oscillator which is the central component of the low voltage phase locked loop (PLL) is proposed in this paper. The VCO adopted the folding differential voltage controlled oscillator.Simulation results in Cadence Hspice indicate that the VCO proposed behaves in good linearity, simple structure, small phase noise.The frequency range from 125 to 787 MHz, the power consumption of this oscillator is only 6mW at central frequency is 480MHz with 3V power supply.

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York, Trevor. "Book Review: Digital CMOS Circuit Design." International Journal of Electrical Engineering & Education 24, no. 3 (1987): 283. http://dx.doi.org/10.1177/002072098702400321.

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Hatfield, John. "Book Review: CMOS Analog Circuit Design." International Journal of Electrical Engineering & Education 25, no. 2 (1988): 183. http://dx.doi.org/10.1177/002072098802500223.

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WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high precision.

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43

Myers, D. J., and P. A. Ivey. "A Design Style for VLSI CMOS." IEEE Journal of Solid-State Circuits 20, no. 3 (1985): 741–45. http://dx.doi.org/10.1109/jssc.1985.1052376.

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Pasternak, J. H., A. S. Shubat, and C. A. T. Salama. "CMOS differential pass-transistor logic design." IEEE Journal of Solid-State Circuits 22, no. 2 (1987): 216–22. http://dx.doi.org/10.1109/jssc.1987.1052705.

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Palmisano, G., and G. Palumbo. "High performance CMOS current comparator design." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 43, no. 12 (1996): 785–90. http://dx.doi.org/10.1109/82.553392.

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Olivera, Fabian, and Antonio Petraglia. "Adjustable Output CMOS Voltage Reference Design." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 10 (2020): 1690–94. http://dx.doi.org/10.1109/tcsii.2019.2943303.

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MANJUNATH, SHAMANNA, and DAMU RADHAKRISHNAN. "Efficient design of CMOS TSC checkers." International Journal of Electronics 71, no. 1 (1991): 67–79. http://dx.doi.org/10.1080/00207219108925459.

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Pei-Yuan Chiang, Chao-Wei Su, Sz-Yun Luo, Robert Hu, and Christina F. Jou. "Wide-IF-Band CMOS Mixer Design." IEEE Transactions on Microwave Theory and Techniques 58, no. 4 (2010): 831–40. http://dx.doi.org/10.1109/tmtt.2010.2041575.

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Blair, G. M. "PLA design for single-clock CMOS." IEEE Journal of Solid-State Circuits 27, no. 8 (1992): 1211–13. http://dx.doi.org/10.1109/4.148332.

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Manku, T. "Microwave CMOS-device physics and design." IEEE Journal of Solid-State Circuits 34, no. 3 (1999): 277–85. http://dx.doi.org/10.1109/4.748178.

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Journal articles on the topic 'CMOS Design'

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