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Wodnicki, Robert. "A CMOS foveated image sensor." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=23759.
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The foveated or log-polar mapping is a biologically motivated image transformation with the potential for realizing efficient real-time vision sensors. By using space-variant sampling, the foveation process compresses the data in the perceived scene, thereby producing a significant reduction in subsequent image processing computations. These savings make foveated image sensors attractive for use on autonomous mobile robots with limited available computing power. When fabricated in standard Complimentary Metal Oxide Semiconductor (CMOS) technology, foveated sensors benefit from the integration of image sensing and processing functions on one substrate, yielding a further reduction in power consumption and system mass. In this thesis, the design, implementation and test of a CMOS foveated image sensor are examined in detail. A new representation of the foveated mapping, called the hybrid model, is introduced to facilitate design of the sensor using a standard CMOS process. The imager is based on the archetypal CMOS Passive Pixel Sensor (PPS). A study of this technology is undertaken, including an investigation of some non-ideal effects. A detailed explanation of the design of the prototype CMOS foveated sensor is presented. Issues related to the use of a standard CMOS process are examined, and the development of a software tool for automatic layout generation explained. The theoretical discussion is followed by a presentation of a comprehensive analysis of the fabricated prototype. With the help of experimental results, including sample images, noise performance, maximum frame rate and power consumption, the merits of the fabricated prototype are demonstrated, and its potential for use as a mobile robot vision sensor investigated.
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Benyhesan, Mohammad Kassim. "Current-mode CMOS hybrid image sensor." Thesis, University of Missouri - Kansas City, 2013. http://pqdtopen.proquest.com/#viewpdf?dispub=1540634.
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<p> Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. </p><p> In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 × 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 <i>µm</i> CMOS process. Measurement results show that up to 39 <i>µW</i> of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several advantages over the voltage-mode. The most important advantages of using current-mode technique are: reduced power consumption of the chip, ease of arithmetic operations implementation, simplification of the circuit design and hence reduced layout complexity.</p>
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Cheng, Hsiu-Yu. "Wide dynamic range CMOS image sensor." Thesis, University of Oxford, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.547452.
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Das, Dipayan. "Wide dynamic range CMOS image sensor." Thesis, University of Oxford, 2011. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.572608.
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• Abstract Integrated digital imaging systems are widely used in consumer electronics today. Current digital image sensors have a linear respeiiSt. The limited dynamic range of linear digital image sensors results in saturation when the input dynamic range of the scene is larger than that of the camera. This limitation could be overcome using pixels with an output that is proportional to the logarithm of the detected photocurrent. Conventional CMOS pixels with a logarithmic response, using a transistor operating in the sub-threshold region, are capable of capturing wide dynamic range scenes with more than six decades of illumination intensity. But these pixels suffer from fixed pattern noise, slow response and low sensitivity. A five transistor (5T) pixel circuit for a standard 0.35-fLm CMOS process which integrates the photocurrent linearly and capable of a logarithmic response is described in the thesis. A key component of the 5T pixel is a time-dependent reference voltage. This voltage is applied to the gate of one of the transistors inside each pixel in the array for the duration of the exposure to generate a logarithmic response. A model derived to generate the reference voltage is described. Improvements were made to the reference voltage model to take into consideration the non-ideal effects such as charge feedthrough and threshold voltage variations. A potential problem associated with successfully tonemapping low photo currents with the 5T pixel has been described and a method to calculate the optimal value of reference current Iret proposed. This was shown to lead to an optimum photoresponse. Measurement results from fabricated 1-D and 2-D arrays of 5T pixels are presented and analysed. An overall DR of 97-dB (almost 5 decades) has been achieved from 100 mlux to 6.7 Klux. The slope of the logarithmic photoresponse was shown to be adjustable and controlled by the slope parameter S in the reference voltage model. A large output swing of over 1 V due to the large photoresponse slope in the logarithmic region results in greater signal-to-noise ratio compared to the conventional logarithmic pixel based on the subthreshold transistor operation (60 m V/decade). Digital and analogue reference voltage generating techniques are described with circuits implemented in 0.35-fLm CM OS process. Finally, a 5T NMOS pixel that is capable of WDR imaging with superior low-light performance (23 mlux) and greater DR (1l0-dB) than the 5T PMOS pixel is described. [ a
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Guo, Xiaochuan. "A time-base asynchronous readout cmos image sensor." [Gainesville, Fla.] : University of Florida, 2002. http://purl.fcla.edu/fcla/etd/UFE0000540.
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Pattnaik, Abhijeet. "DESIGN OF A CMOS BASED IMAGE SENSOR USING COMPRESSIVE IMAGE SENSING." OpenSIUC, 2021. https://opensiuc.lib.siu.edu/theses/2868.
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This work optimizes a CMOS image pixel sensor circuit for being used in a compressive sensing (CS) image sensor. The CS image sensor sums neighbor pixel outputs and hence reduces analog to digital conversions. Efforts are also made to improve the circuit that performs such pixel summation. With the optimized design, a CMOS image sensor circuit with a compression ratio of 4 is designed using a 130 nm CMOS technology from Global foundries. The design pixel sensor has a 256X256 pixel array. Simulation shows that the developed image sensors can achieve peak signal to noise ratio (PSNR) of 28 dB and 37.8 dB for benchmark images Cameraman and Lenna, respectively.
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Saffih, Fayçal. "Foveated Sampling Architectures for CMOS Image Sensors." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/820.
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Electronic imaging technologies are faced with the challenge of power consumption when transmitting large amounts of image data from the acquisition imager to the display or processing devices. This is especially a concern for portable applications, and becomes more prominent in increasingly high-resolution, high-frame rate imagers. Therefore, new sampling techniques are needed to minimize transmitted data, while maximizing the conveyed image information. <br /><br /> From this point of view, two approaches have been proposed and implemented in this thesis: <ol> <li> A system-level approach, in which the classical 1D row sampling CMOS imager is modified to a 2D ring sampling pyramidal architecture, using the same standard three transistor (3T) active pixel sensor (APS). </li> <li> A device-level approach, in which the classical orthogonal architecture has been preserved while altering the APS device structure, to design an expandable multiresolution image sensor. </li> </ol> A new scanning scheme has been suggested for the pyramidal image sensor, resulting in an intrascene foveated dynamic range (FDR) similar in profile to that of the human eye. In this scheme, the inner rings of the imager have a higher dynamic range than the outer rings. The pyramidal imager transmits the sampled image through 8 parallel output channels, allowing higher frame rates. The human eye is known to have less sensitivity to oblique contrast. Using this fact on the typical oblique distribution of fixed pattern noise, we demonstrate lower perception of this noise than the orthogonal FPN distribution of classical CMOS imagers. <br /><br /> The multiresolution image sensor principle is based on averaging regions of low interest from frame-sampled image kernels. One pixel is read from each kernel while keeping pixels in the region of interest at their high resolution. This significantly reduces the transferred data and increases the frame rate. Such architecture allows for programmability and expandability of multiresolution imaging applications.
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Wang, Ching-Chun 1969. "A study of CMOS technologies for image sensor applications." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8214.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.<br>Includes bibliographical references (p. 179-183).<br>CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially lower price. The advantages make this technology competent for the next-generation solid-state imaging applications. However, CMOS processes are originally developed for high-performance digital circuits. Fabricating high-quality embedded image sensors with CMOS technologies is not a straightforward task. This motivates the study of CMOS technologies for imaging applications presented in this thesis. The major content of this study can be partitioned into four parts: (a) A two-stage characterization methodology is developed for sensor optimization, including the characterization of large-area photodiodes and comparative analyses on small-dimension sensor arrays with various pixel structures, junction types of the sensors, and other process-related conditions. (b) The mechanism of hot-carrier induced excess minority carriers occurred at the in-pixel transistors is identified and investigated. The influence of the excess carriers on imager performance is analyzed. Suggestions on the pixel design are provided. (c) Signal cross-talk between adjacent pixels is quantified and studied using a sensor array with a specially designed metal shield pattern, which exposes the center pixel and covers the others. The influence of cross-talk on color imager performance is analyzed. Process and layout improvements on cross-talk are also proposed. (d) The trend of pixel size reduction is investigated from the perspective of the achievable optical lens resolution. Using the modulation transfer function (MTF) as an index, optical simulations are performed to examine the relation between the lens resolution and the lens complexity.<br>by Ching-Chun Wang.<br>Ph.D.
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Pour, Golsa Moayeri. "A Hybrid CMOS Image Sensor with Energy Harvesting Capability." Thesis, Purdue University, 2015. http://pqdtopen.proquest.com/#viewpdf?dispub=3734524.
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<p> During the past decades fast progress in CMOS fabrication technology has driven the miniaturization of electronic circuits. Every 2 to 3 years a new technology node has been introduced that reduced the sizes of all features in a circuit by 0.7, resulting in a reduction of the circuit area by half. This scaling has resulted in huge cost reduction for electronic circuits, reduced power consumption and increased circuit speed. The rapid cost and area reduction has stimulated new applications for CMOS circuits and the integration of more functionality on the same die. In recent years self-powered electronic circuits are investigated by integrating energy harvesting devices into electronic circuits such as for example solar cells. Such self powered electronic circuits are of interest for autonomous sensor applications.</p><p> In this thesis a 64 x 64 CMOS pixel analyzed array with solar energy harvesting functionality has been designed, simulated and fabricated. The substrate-well photodiodes within each pixel are used for light sensing and as solar cells. For such a hybrid pixel design the traditional active pixel design was modified in order to be able to bias the fundamental pn-junctions as required by the momentary operation mode. In order to be able to charge a battery, the voltage produced by the pn-junctions in energy harvesting mode had to be boosted up. For this purpose a DC-DC power converter was implemented into the circuit. Low-power design techniques were used in the circuit design phase using Cadence software for the design and simulation. The final pixel array was fabricated in a 0.5 μm CMOS process.</p><p> A printed circuit board hosting an FPGA and supporting circuitry was designed and fabricated to test the fabricated CMOS microchip. A system-level model was also developed to gain a deeper insight into the trade off between energy harvesting and frame rate. It was found out that, under sunny outdoor condition, the energy harvesting pixel array can power itself up if the frame rate is reduced to 0.5 frames/s.</p>
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Chen, Shoushun. "Time domain CMOS image sensor : from photodetection to on-chip image processing /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20CHEN.
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Hu, Li. "Low power CMOS image sensor using adaptive address event representation /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20HU.
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Feng, Zhenfu. "Fast scalable and variability aware CMOS image sensor simulation methodology." Phd thesis, Ecole Centrale de Lyon, 2014. http://tel.archives-ouvertes.fr/tel-01066786.
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The resolution of CMOS image sensor is becoming higher and higher, while for identifying its performance, designers need to do a series of simulations, and this work consumes large CPU time in classical design environment. This thesis titled "Fast Scalable and Variability Aware CMOS Image Sensor Simulation Methodology" is dedicated to explore a new simulation methodology for improving the simulation capability. This simulation methodology is used to study the image sensor performance versus low level design parameter, such as transistor size and process variability. The simulation methodology achieves error less than 0.4% on 3T-APS architecture. The methodology is tested in various pixel architectures, and it is used in simulating image sensor with 15 million pixels, the simulation capability is improved 64 times and time consumption is reduced from days to minutes. The potential application includes simulating array-based circuit, such as memory circuit matrix simulation.
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Mishu, Pujan Kumar Chowdhury. "DESIGN OF CMOS COMPRESSIVE SENSING IMAGE SENSORS." OpenSIUC, 2018. https://opensiuc.lib.siu.edu/theses/2446.
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This work investigates the optimal measurement matrices that can be used in compressive sensing (CS) image sensors. It also optimizes CMOS current-model pixel cell circuits for CS image sensors. Based on the outcomes from these optimization studies, three CS image senor circuits with compression ratios of 4, 6, and 8 are designed with using a 130 nm CMOS technology. The pixel arrays used in the image sensors has a size of 256X256. Circuit simulations with benchmark image Lenna show that the three images sensors can achieve peak signal to noise ratio (PSNR) values of 37.64, 33.29, and 32.44 dB respectively.
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Bonnard, Rémi. "Burst CMOS image sensor with on-chip analog to digital conversion." Thesis, Strasbourg, 2016. http://www.theses.fr/2016STRAD006/document.
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Ce travail vise à étudier l’apport des technologies d’intégration 3D à l’imagerie CMOS ultra-rapide. La gamme de vitesse d’acquisition considérée ici est du million au milliard d’images par seconde. Cependant au-delà d’une dizaine de milliers d’images par seconde, les architectures classiques de capteur d’images sont limitées par la bande passante des buffers de sortie. Pour atteindre des fréquences supérieures, une architecture d’imageur burst est utilisée où une séquence d’une centaine d’images est acquise et stockée dans le capteur. Les technologies d’intégration 3D ont connu un engouement depuis une dizaine d’années et sont considérées comme une solution complémentaire aux travaux menés sur les dispositifs (transistors, composants passifs) pour améliorer les performances des circuits intégrés. Notre choix s’est porté sur une technologie où les circuits intégrés sont directement empilés avant la mise en boitier (3D-SIC). La densité d’interconnexions entre les différents circuits est suffisante pour permettre l’implémentation d’interconnexions au niveau du pixel. L’intégration 3D offre d’intéressants avantages à l’imagerie intégrée car elle permet de déporter l’électronique de lecture sous le pixel. Elle permet ainsi de maximiser le facteur de remplissage du pixel tout en offrant une large place aux circuits de conditionnement du signal. Dans le cas de l’imagerie burst, cette technologie permet de consacrer une plus grande surface aux mémoires dédiées au stockage de la séquence d’image et ce au plus proche des pixels. Elle permet aussi de réaliser sur la puce la conversion analogique numérique des images acquises<br>This work aims to study the inflows of the 3D integration technology to ultra-high speed CMOS imaging. The acquisition speed range considered here is between one million to one billion images per second. However above ten thousand images per second, classical image sensor architectures are limited by the data bandwidth of the output buffers. To reach higher acquisition frequencies, a burst architecture is used where a set of about one hundred images are acquired and stored on-chip. 3D integration technologies become popular more than ten years ago and are considered as a complementary solution to the technological improvements of the devices. We have chosen a technology where integrated circuits are stacked on the top of each other (3D-SIC). The interconnection density between the circuits is high enough to enable interconnections at the pixel level. The 3D integration offers some significant advantages because it allows deporting the readout electronic below the pixel. It thus increases the fill factor of the pixel while offering a wide area to the signal processing circuit. For burst imaging, this technology provides more room to the memory dedicated to the image storage while staying close to the pixel. It also allows implementing analog to digital converter on-chip
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Matsunaga, Shinichiro. "A single-chip CMOS tracking image sensor for a complex target." Thesis, University of Edinburgh, 2002. http://hdl.handle.net/1842/15285.
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Recently CMOS sensors have been greatly improved, and various smart sensors, which include processing units inside the chip, have been reported. Although a number of methods for motion detection are reported in the literature, little attention has been paid to tracking sensors. Many motion detection sensors have been reported, and sometimes motion detection and motion object tracking are regarded as equivalent, since they typically use the same algorithm at the front end. However they are not the same. Tracking means tracing the progress of objects as they move about in a visual scene. The target must be followed continuously for a long time. On the other hand motion detectors only output instantaneous target movement. There are two main problems in the existing design of tracking sensors. Firstly they cannot handle complex target images, therefore simple features are used as the target for some sensors, even though the target does not always have those features in the real-world. Usually those sensors only track simple features such as edges or bright points. Secondly the precision of tracking is quite poor due to their circuit techniques. So although they perform well on synthetic data, performance is poor on real-world images. This thesis investigates how to realize a single chip tracking sensor which can deal with complex real-world object. A survey of existing tracking algorithms, which can be implemented on silicon is presented. A computation directed algorithm, which is known as BMA (Block Matching Algorithm) has been adopted and modified. This algorithm can deal not only with edges but also with more ambiguous features, and a performance of the algorithm is tested with real-world images. Hybrid circuits consisting sensors, analogue and digital circuits have been developed, and high precision tracking circuits are presented. The circuits, which incorporate <i>64x64 </i>Active Pixel Sensors, parallel analogue memory and a Switched Capacitor parallel processing unit, are implemented on a single chip and fabricated. The circuits have been tested electrically, and total chip performance has been examined with test bed for tracking. Finally ideas for future improvements are presented. These are actually possible with current CMOS technology.
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Storm, Graeme George. "Extended dynamic range from a combined linear-logarithmic CMOS image sensor." Thesis, University of Edinburgh, 2004. http://hdl.handle.net/1842/14495.
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Dynamic Range determines the ability to see detail in scenes with varying illumination intensities, whether the viewing element is an eye, conventional film, or a digital image sensor. There are two distinct measures of dynamic range: interscene and intrascene. The first is the absolute range viewable, where the viewing mechanism has time to adapt to the full range of sensitivity to incident illumination and the second is the range achievable in just a single setting and time. The research reported in this Thesis investigates how to combine linear and logarithmic modes of circuit operation to improve CMOS imager intrascene dynamic range. A single chip, 360x288 pixel image sensor has been designed, fabricated and characterized to demonstrate the ideas developed during the research. The pixel circuits are switchable between linear and logarithmic modes: after the set exposure period the linear result is readout then the logarithmic mode is switched in and read-out. Single or two parameter calibration can be performed to reduce the relatively high level of FPN in the raw logarithmic data. The settling time of the logarithmic mode of operation is identified as an important constraint on this approach and is optimized by the inclusion of an amplifier. To permit a pixel pitch of 5.6µm in a 0.18µm technology and achieve a 33% fill-factor, circuit and layout architectures have been devised to place the majority of the amplifier in the column in a way that allows it to be switchable between rows. The combining of linear and logarithmic data in a single image provides an intrascene dynamic range in excess of 120dB. The sensor can operate at 26 frames per second when employing single parameter calibration of the logarithmic mode. Comprehensive characterization of both modes and the overall performance of the sensor is also outlined. Critical discussion and suggestions on further research conclude the Thesis.
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Shen, Chao. "Study of CMOS active pixel image sensor on SOI/SOS substrate /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20SHEN.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.<br>Includes bibliographical references (leaves 67-69). Also available in electronic version. Access restricted to campus users.
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Robucci, Ryan. "On Chip Error Compensation, Light Adaptation, and Image Enhancement with a CMOS Transform Image Sensor." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6986.
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CMOS imagers are replacing CCD imagers in many applications and will continue to make new applications possible. CMOS imaging offers lower cost implementations on standard CMOS processes which allow for mixed signal processing on-chip. A system-on-a-chip approach offers the ability to perform complex algorithms faster, in less space, and with lower power and noise. Our transform imager is an implementation of a mixed focal plane and peripheral computation imager which allows high fill factor with high computational rates at low power. However, in order to use the technology effectively a need to verify and further understand the behavior and of the pixel elements in this transform imager was needed. This thesis presents a study of the pixel elements and mismatches and errors in the pixel array of this imager. From there, a discussion about removing offsets and an implementation of a circuit to remove the largest offsets is shown. To further enhance performance, initial work to develop light adaptive readout circuits is presented. Finally, an overview is given of a newly designed one-megapixel transform imager with many design improvements.
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Breidenassel, Andreas. "A high dynamic range CMOS image sensor with adaptive integration time control." [S.l. : s.n.], 2005. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11811225.
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Cruz, Carlos Augusto de Moraes. "Simplified wide dynamic range CMOS image sensor with 3t APS reset-drain actuation." Universidade Federal de Minas Gerais, 2014. http://hdl.handle.net/1843/BUOS-9PFG8J.
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An image sensor is an array of small light-sensitive cells called pixel sensors. A pixel, or picture pix element el, is the smallest unit of an image. Therefore a pixel sensor is the smallest cell of an image sensor, which is able to detect a single image dot. Such image dot is then used to reconstruct a complete image frame. Image sensors built in CMOS technology are nowadays largely employed either in professional cameras or in personal mobile devices with embedded cameras. One of the most important features of a good image sensor is the ability to accommodate in the same image regions of high and low luminosity, a feature known as the sensor dynamic range. Many techniques, found in the literature, are able to extend the sensor dynamic range, each with their advantages and disadvantages, either by extending the saturation level or by reducing the noise floor. Non-idealities introduced during fabrication produce unwanted image artifacts known as fixed-pattern noise FPN and are among the main contributors to the noise floor in CMOS image sensors. Techniques applied to reduce FPN in image sensors with large dynamic range are still a challenge, because in applying these techniques other essential features of the sensor are jeopardized, as its processing speed, the reduction of photosensitive area, or the increase in fabrication costs. The main goal of this work is the improvement of CMOS image sensors, operating with wide dynamic range for general practical purposes, through the application of simple circuit control techniques, without interfering in the fabrication process of the imager. In order to achieve this goal, the present work proposes a simple and innovative approach to increase the dynamic range of the basic and most popular pixel sensor architecture currently employed in CMOS image sensors. The proposed idea differs from the current state-of-art in two essential points. First, because it is able to increase the sensor dynamic range without the need of boosting the level of any control signal above that of the supply voltage. Second, because, other than any different techniques found in literature, it is able to reduce FNP in this sort of image sensor by means of a simple control strategy. Boosting the level of some control signals is necessary, in previous techniques found in the literature, in order to avoid the use of more complex pixel-sensor architectures, which reduces the sensor photosensitive area. On the other hand, internal voltage boosting is harmful because it tends to reduce the life time of the imager. The simplified way to reduce FPN in the herein proposed technique is able to keep unaltered important features of the sensor, as those cited above, at no additional fabrication cost.<br>Um sensor de imagem é uma matriz de pequenas células fotossensíveis chamadas sensores de pixeis. Um pixel, elemento el fotográfico (picture) pix, é a menor porção de uma imagem. Assim o sensor de pixel é a menor célula de um sensor de imagem, capaz de detectar um ponto singular da imagem. Este ponto é então usado para reconstruir um quadro completo de imagem. Sensores de imagem CMOS são atualmente largamente utilizados tanto em câmeras profissionais como em aparelhos moveis em geral como celulares. Uma importante característica de um bom sensor de imagem é a capacidade de acomodar na mesma imagem regiões de alta e baixa luminosidade, chamada de alcance dinâmico do sensor. Muitas técnicas, encontradas na literatura, são capazes de aumentar o alcance dinâmico do sensor, cada uma com vantagens e desvantagens, tanto retardando o nível de saturação quanto reduzindo o ruído base. Não idealidades introduzidas durante o processo de fabricação produzem artefatos indesejáveis na imagem conhecidos com ruído de padrão fixo (fixed-pattern noise) FPN e está entre os principais contribuintes para a determinação do ruído base em sensores de imagem CMOS. Redução de FPN em sensores de imagem com largo alcance dinâmico ainda é um desafio, pois ao aplicar qualquer das técnicas existentes, outras características essenciais do sensor são comprometidas, como velocidade de processamento, redução de área fotossensível, ou aumento de custo de fabricação. Este trabalho tem por objetivo aprimorar a operação de sensores de imagem CMOS, que operam com largo alcance dinâmico para aplicações praticas em geral, através da aplicação de técnicas simples de circuito, sem interferir no processo de fabricação. Para isso é proposto uma maneira simples e inovadora de aumentar o alcance dinâmico da mais básica e popular arquitetura de sensor de pixel atualmente usada em tecnologias CMOS. A ideia proposta tem duas diferenças básicas do corrente estado-da-arte. A primeira é a capacidade de aumentar o alcance dinâmico sem elevar o nível de tensão de qualquer sinal de controle acima do nível da alimentação. A segunda é a simplicidade da técnica de redução de FPN neste tipo de sensor em relação às demais encontradas na literatura. Nas técnicas, atualmente encontradas na literatura, a elevação do nível de tensão em alguns sinais de controle é necessária para evitar arquiteturas mais complexas, que reduzem a área fotossensível do sensor. Por outro lado a elevação da tensão acima do nível da alimentação é prejudicial, pois reduz o tempo de vida útil do sensor de imagem. A simplicidade da técnica de redução de FPN proposta neste trabalho é capaz de manter inalterada características importantes do sensor, como aquelas citadas acima, sem custo de fabricação adicional.
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Huang, Yan-Ru, and 黃彥儒. "Reaserch and Development of CMOS Image Sensor Micro Multi-Layer Nonspherical Lens Module Inspection System." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/31625845103671355504.
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碩士<br>國立臺灣科技大學<br>自動化及控制研究所<br>102<br>This paper developed an optical inspection system of CMOS image sensor (CIS) micro multi-layer non-spherical lens module. However, the CIS lens module structure was multi-layer. When light passed through the non-spherical lens module, it will cause a halo because of reflection and refraction. It led defect is difficult to be found. When acquiring the image, the image resolution and size of defects needed to be considered. It caused the magnification lens’s depth of field does not cover the height of the inspected object. The mentioned two cases would be difficult to perform a follow-up defect detection so this paper developed solutions these problem, and developed a CIS micro multi-layer non-spherical lens module inspection system.
The CIS micro multi-layer non-spherical lens module inspection system consisted three main components: (1) Image preprocessing, (2) Defect inspection procedure, and (3) Defect recognition. The first component mainly used Hough transform to detect circle and to segment region of interest (ROI), and then amended illumination unevenness by using single-scale Retinex. The second component used the Kuwahara filter, control limit method, region growing, etc to segment the defect. In order to solve the problem of lens’s depth field not covering the inspected object’s height, the multi-image was acquired. This paper proposed a way to avoid major defect that influenced different layers image by judging defect unabridged rate and defect sharp rate, and calculated the defect feature. Finally, this study used a support vector machine to recognize different kinds of defect. The experimental result showed the accuracy of defect recognition is 97.97 %. This paper proposed an optical inspection system of CMOS image sensor micro multi-layer non-spherical lens module that effectively detected and recognized the defects.
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Laio, Chi-Hung, and 廖啟宏. "CMOS Image Sensor Technology (I)." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/45000030569043876291.
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碩士<br>國立交通大學<br>電子工程系<br>89<br>Recently, there has been a growing interest in CMOS image sensors. The major reason for this interest is the customer demand for miniaturized, low-power, and low-coast digital cameras. CMOS image sensors offer a great potential to integrate a significant amount of VLSI electronics on a single chip and reduce discrete components and packaging costs. It is now straightforward to envision a single-chip camera that has integrated timing and control electronics, sensor array, signal processing electronics, analog-to-digital converter (ADC) and full digital interface. Such a camera-on-a-chip will operate with standard logic supply voltages and consume power measured in the tens of milli-watts.
The CMOS image sensor under studies includes three important parts: the first is pixel array, the second is on-chip signal processing and the third is programmable-gain amplifier. The pixel size is the key point for CMOS image sensors in high-resolution applications. In this thesis, the structure of three transistors is proposed. On-chip analog signal processing can be used to improve the performance and functionality of a CMOS image sensor. The general method is to use correlated-double-sampling (CDS) to suppress kTC noise from pixel reset, 1/f noise from the in-pixel source follower amplifier, and fixed-pattern-noise (FPN) originating from pixel-to-pixel variation in source-follower threshold voltage. The programmable gain settings are used to create color-filter-patterns.
The CMOS image sensor uses the standard logic process offered by TSMC (0.35um) with applied voltage of 3.3v and operates at 25MHz, and the pixel array is 640*480.
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Liao, Yi-Hui, та 廖怡卉. "CMOS Image Sensor Technology(二)". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/57469001736875199438.
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碩士<br>國立交通大學<br>電子工程系<br>89<br>The pixels of an image sensor are based on CCD (Charge-Coupled device) in current market for high-resolution applications. However, the disadvantages of CCD are large power consumption and incompatible in process with CMOS (Complementary metal-oxide semiconductor) elements for system on a chip to reduce cost. This thesis gives the architecture of a CMOS image sensor chip, including serial interface and its control, the image sensor operation and its control, and the image sensor registers. The serial interface includes synchronous interface and universal asynchronous transmitter and receiver. The main control blocks of the image sensor include the pixel and readout block control, the programmable gain amplifier block control, and the analog to digital converter control. The data of register sets is used to control the capture image operation of the image sensor and the image data processing of the image chip.
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"High Speed CMOS Image Sensor." Master's thesis, 2016. http://hdl.handle.net/2286/R.I.40301.
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abstract: High speed image sensors are used as a diagnostic tool to analyze high speed processes for industrial, automotive, defense and biomedical application. The high fame rate of these sensors, capture a series of images that enables the viewer to understand and analyze the high speed phenomena. However, the pixel readout circuits designed for these sensors with a high frame rate (100fps to 1 Mfps) have a very low fill factor which are less than 58%. For high speed operation, the exposure time is less and (or) the light intensity incident on the image sensor is less. This makes it difficult for the sensor to detect faint light signals and gives a lower limit on the signal levels being detected by the sensor. Moreover, the leakage paths in the pixel readout circuit also sets a limit on the signal level being detected. Therefore, the fill factor of the pixel should be maximized and the leakage currents in the readout circuits should be minimized.
This thesis work presents the design of the pixel readout circuit suitable for high speed and low light imaging application. The circuit is an improvement to the 6T pixel readout architecture. The designed readout circuit minimizes the leakage currents in the circuit and detects light producing a signal level of 350µV at the cathode of the photodiode. A novel layout technique is used for the pixel, which improves the fill factor of the pixel to 64.625%. The read out circuit designed is an integral part of high speed image sensor, which is fabricated using a 0.18 µm CMOS technology with the die size of 3.1mm x 3.4 mm, the pixel size of 20µm x 20 µm, number of pixel of 96 x 96 and four 10-bit pipelined ADC’s. The image sensor achieves a high frame rate of 10508 fps and readout speed of 96 M pixels / sec.<br>Dissertation/Thesis<br>Masters Thesis Electrical Engineering 2016
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HUANG, PO-CHIA, and 黃柏嘉. "CMOS image sensor test method." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/urx865.
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碩士<br>中華大學<br>電機工程學系<br>107<br>This paper discusses the test method of CMOS Image Sensor (CIS), which uses the independent precision measurement function of digital signal tester as the basis of CIS test, and then according to the signal format of D-PHY protocol of Mobile Industry Processor Interface (MIPI) Alliance. The image processing accessories for decoding and sorting are designed, and the digital signal testing machine is combined with the image processing accessories to form a CIS testing machine, and a testing process flow is established, and finally the electrical and image testing of the CIS is performed.
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Chia-NanYeh and 葉佳楠. "High Performance CMOS Image Sensor System." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/81097590315792773942.
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博士<br>國立成功大學<br>電機工程學系碩博士班<br>98<br>In this dissertation, first, two power saving techniques are proposed to reduce both dynamic and static power consumption of shift-register-based readout control circuits in conventional CMOS image sensors. To reduce the power consumption in dynamic domain, a new clock gating control unit (CGCU) is designed and inserted in front of an inverter in the distributed clock tree. The CGCUs operate as pruners for disabling portions of the circuitry where flip-flops do not change state. Without using extra control signals, the signals generated by the shift register itself are utilized as the control signals of CGCUs. According to the analysis and simulations, the dynamic power dissipation is proportional to the logarithm of the number of D flip-flops. More than 90% of dynamic power saving is achieved when reading out a frame with size of equal to or larger than 128×128. The static power dissipation is mainly from the leakage current. A low leakage D filp-flop by adopting the stack technique is designed. Simulations show that more than 80% of static power saving is achieved.
Second, a folding technique is proposed to reduce the decoder circuit complexity of a flash ADC in the conventional CMOS image sensors. After folding, a k-bit decoder is replaced with two sub-decoders. The decoding of the upper k/2 bits and the lower k/2 bits can be accomplished respectively. Consequently, the number of inputs to the decoder is reduced to the square root of the original. Analytic results show that for different decoder structures, more than 17% of hardware and 13% of time delay can be saved. Moreover, the tolerance of bubble induced errors is enhanced. A 6-bit flash ADC has been implemented in 0.18-μm CMOS that occupies 0.37mm×0.35mm active area. Simulations show that the figure-of-merit number is as low as 1.03 pJ/conversion-step at 1G Sample/s and the maximum bubble induced error is limited to the number of bubbles.
Third, we propose an adaptive-sampling algorithm and develop a digital CMOS pixel sensor which has features of wide dynamic range and approximated-logarithmic response. In this new architecture the pixel-level analog-to-digital conversion is realized by employing a comparator combined with a 4-bit in-pixel static memory. Under different response modes, the corresponding 8 bits digitalized value of a pixel can be obtained by applying the proposed timing control schemes. Since the signal processing is accomplished at pixel-level, both power consumption and hardware cost are lowered. The designed pixel occupies an area of 15.8 μm×15.8 μm with a fill factor of 21%. Simulation results validate the effectiveness of the proposed DPS and the achievable dynamic range is 48 dB in linear response mode and 114 dB in logarithmic response mode respectively.
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Deng, Guei-Fu, and 鄧貴福. "Study of pupil lens module for CMOS sensor testing." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/s9udxw.
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碩士<br>國立高雄應用科技大學<br>電機工程系博碩士班<br>103<br>In this study, it is proposed that a new pupil lens module (PLM) is used for CMOS image sensor integrated circuits testing. Parallel light provided by the integrated circuit testing machine, Irradiation in the PLM, let the light can be evenly distributed in the CMOS image sensor, able to detect the illumination uniformity, and which can accomplish the illumination on the tested integrated circuits to be less than 2% in uniformity deviation. The PLM includes achromatic lens, pupil and secondary element. The secondary element design, it is use optical analysis software to get illuminance distribution data and light position correspond relationship, according to the above data to adjust the structure of secondary element, in order to achieve the desired ideal illumination uniformity distribution.
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Chang, Chia-Fu, and 張家福. "A study on discolor image of CMOS image sensor." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/24192408069520180146.
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碩士<br>國立交通大學<br>工學院半導體材料與製程設備學程<br>103<br>Without a doubt, CMOS(Complementary Metal-Oxide-Semiconductor) image sensor, replacing CCD(Charge-Coupled Device) image sensor, is the mainstream of image sensor market in recent years. CMOS image sensor is used in many kinds of application, such as smart phone, tablet, vehicle video record, surveillance camera, and the visual devices in future smart car. So it has huge market and infinite business.
This thesis is base on CMOS image sensor sample with discolor phenomenon for study. First, we use image and failure analysis to find out the root cause of discolor image as well as the physical defect location, then simulate image signal with different pixel structure by FDTD(Finite Difference Time Domain) optical simulation software. Finally, we compare the simulation result and actual image signal provided by CP(Circuit Probing) testing then to verify the accuracy of FDTD method for the estimation of quantum efficiency in unit pixel and image signal of CMOS image sensor.
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陳虹竹. "SPICE MODEL OF CMOS IMAGE SENSOR PHOTODIODE." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/90553381467195603824.
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碩士<br>國立清華大學<br>電子工程研究所<br>93<br>A novel photodiode model which better describes the electro-optical behavior of the CMOS image sensor has been developed. The conventional diode model adopted by Bsim 3.3 suffers from the violation between simulation and measurement results. The sources of the violation are analyzed into details. A novel mathematical model is proposed. By using TSMC 0.35μm CMOS technology, photodiodes with different structures have been fabricated and measured. The results can show the relationship between the diode current and the operation voltage, temperature, photo lux and wavelength, respectively. And the results can be used to extract the relevant parameters. Moreover, the proposed mathematical model and the extracted parameters can provide a precise environment for the diode current simulation.
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Yen, Shiu-Fin, and 葉秀芬. "A High Dynamic-Range CMOS Image Sensor." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/32905305978387920276.
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Huang, Ling-Yen, and 黃鈴晏. "Competition Analysis of CMOS Image Sensor Marke." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/h4d533.
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碩士<br>國立交通大學<br>管理學院科技管理學程<br>106<br>The development of semiconductor and package industry lead the CMOS Image sensor technology commercialization. Image sensors are widely used. With the prevalence of multimedia multimedia, digital image has gradually become a trend. The mobile device industry including mobile phone, IOT and Automobile electronics adopt the sensor application provide the market growth momentum of CMOS Image Sensor market The overall image sensor market in 2016 reached 11.6 billion US dollars. According to the analysis report of Yole Développement, they predict the market will enjoy 10% compound annual growth rate (CAGR). There are many players join in the market competition. Faced with fierce market competition, manufacturers must have a faster product development process, complex supply chain management with product life cycle and adopt an effective competitive strategy to meet the Internet of Things era.
At the industry level, I use the diamond model and the five forces to analyze the competition strategy of the image sensor manufacturers. At the company level, the case study is used to discuss the suitable business model for the case company and put forward practical management implications through expert interview.
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Lai, Han-hsin, and 賴漢新. "The Study on Metering Technology for CMOS Image Module." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/h8nd23.
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碩士<br>國立虎尾科技大學<br>光電與材料科技研究所<br>95<br>Owing to the image problems caused by light, we propose solutions in this thesis. First of all, the method is Multi-zone evaluative metering. This light metering system divides the whole frame into multiple sections and decides the metering weight of fixed section according to where the main object is.
Our main goal is to design a module for building into the door phone system, due to particular requirements of environment conditions for digital door phone system, module what we design is to adjust the image by using the back-lighted image detection and the algorithm of compensation. Using Gamma curve to tune the brightness of image can increase the brightness of object at back light as well as preserve the brightness of other fractions of the image. Through this compensation after light metering process, the image can be reached higher resolution.
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Lin, Jiunn-Jyi, and 林俊吉. "Competitive Strategies in Semiconductor CMOS Image Sensor Companies." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/57437806549082352566.
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碩士<br>國立臺灣大學<br>商學組<br>95<br>Global CMOS Image Sensor industry isgrowing rapidly in recent years along with camera phone、DSC、notebook camera and other consumer electronic devices with an estimated growth rate of 30% ACGR. Taiwan CIS companies ought to integrate wafer foundry、back-end testing and package companies to efficiently form a global competitive business model.
In this paper the author focuses on the competitive strategies for both fabless and wafer foundry companies within the CIS industry. The conclusion below summarises by the analysis of industry issues, the evolution of IC industry、the CIS supply model and strategy、the competitive strategies、the Fabless-Foundry business transaction model、the vertical integration factorsand the industry game theory and conflict reconciliation.
(a) The rapid growth of the CIS industry provides both fabless and wafer foundry companies a sustainable competitive niche to penetrate the marketplace.
(b) In the CIS industry, the leaders of both fabless and wafer foundry have established a joint venture in the back-end CF/OCM/WLCSP manufacturing services and have strengthened mutual partnership to widen the competitive gap with other competitors, maintained competition advantage for the long time and further challenge IDM for marketshare leadership.
(c) "Price Strategy Conflict" is caused by competitive forces that try to capture market share by low cost pricing strategy. This competitive force can be quantified by the sensitivity analysis of dynamic game theory as well as the various parameters of the competitors. Indeed, this external influence can make an impact on the Joint Venture and cause considerable conflict. This conflict; however, can be managed by a balanced investment into the Joint Venture by the fabless company. "Capacity Strategy Conflict" is caused by the conflicting objectives of both JV shareholders - both in satisfying customer capacity needs as well as meeting the financial requirements imposed by financial metrics such as return on assets. Hence, through TOC analysis, it is recommended that the shareholders should develop a model that combines the need to satisfy operational capacity constraints as well as financial returns for their investment in order to optimize the results in the JV.
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Wei-MingTsai and 蔡維民. "Simulation of Film Structure for CMOS Image Sensor." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/12822583323585635237.
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Wang, Chun-Chieh, and 王俊杰. "Design of High Dynamic Range CMOS Image Sensor." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/76141104540573002992.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>92<br>Abstract
CMOS image sensors have some advantages compare with Charge-Coupled Device (CCD) that are on-chip functionality、 system power reduction、 cost and area. Typical CMOS image sensors do not have sufficient Dynamic Range (DR) (around 60 dB) to capture the full range of illumination in the real world (over 100 dB). To increase DR, several methods have been proposed using the time as a control variable. However, these methods do not increase peak Signal-to-Noise Ratio (SNR).
In this paper, we design a high DR and SNR CMOS imaging system which using pixel level Analog-to-Digital Converter (ADC), and digital data is read out at high speeds.[23] We intend to develop an image sensor by using TSMC CMOS 0.18 μm technology. Consequently, DR and peak SNR are increased simultaneously.
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Liu, Kuo-Chih, and 劉國志. "Reseach of Lenless CMOS Sensor for Image Precessing." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/97720366974410481735.
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碩士<br>國立屏東科技大學<br>車輛工程系所<br>100<br>This study presents a study of the lenless CMOS (Complementary Metal-Oxide-Semiconductor) sensor integrating a NI LabVIEW image processing program for particles recognition and size analysis. The micro-image recognition and size analysis system includes a lenless CMOS sensor, a PDMS (poly-dimethylsiloxane) microfluidic detection chip by a lithography process and a NI LabVIEW image processing program. In the image processing program, the particles number and size can be distinguished by the pixel size utilizing the raw image acquired from the lenless CMOS sensor. The system test results are verified in the commercial optical microscope by the same scale photograph.
In this study, the variety of samples in different size polystyrene (PS) latex particles of 5 μm, 8.18 μm, 10 μm, 15 μm, and mixed different particles of 5 μm, 10 μm and 5 μm, 10 μm, 15 μm are demonstrated. The test results show the lenless CMOS image analysis and processing system can distinguish the 5 μm, 8.18 μm, 10 μm and 15 μm particles clearly. Therefore, we conclude that the lenless CMOS image anlysis and
processing system provides a highly accurate and efficient portable device for particle counting and real time monitoring.
Keyword：lenless、CMOS sensor、lithography process、image
analysis、image processing.
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Nilchi, Alireza. "Focal-plane CMOS algorithmically-multiplying computational image sensor." 2008. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=771959&T=F.
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Zhang, Yu-Cheng, and 張育誠. "Light Guide Bar Design For Contact Image Sensor Module." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/8hy5hg.
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碩士<br>國立中央大學<br>光電科學與工程學系<br>107<br>In this thesis, a novel concept for the design of a light guide bar has been firstly proposed. We apply a certain blade with high temperature for shaping the necessary grooves on the bottom of the light guide bar. All the sculpturing parameters, including the repeatability of the light guide bars, the accuracy of the groove periods, and the precision for the groove depth, are extensively verified. The groove periods and depths have been carefully optimized in order to have uniform output light distribution. Generally, the PRNU value is requested as low as less than 30 %. The simulation design is then realized in mass production and greatly help the production time and cost.
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Olyaei, Ashkan. "ViPro: Focal-plane CMOS spatially-oversampling computational image sensor." 2006. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=442048&T=F.
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劉書成. "Study on Parameters Extraction Method of CMOS Image Sensor." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/11360920442841847119.
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碩士<br>國立清華大學<br>電子工程研究所<br>93<br>The parameter measurements of CMOS image active sensor are fundamental for the performance optimization of CMOS APS. However, most critical parameters of a APS, such as capacitance and dark current, are difficult to measure directly. A simple method based on CBCM for measuring the capacitance of CMOS active image sensor has been proposed. Samples fabricated by 0.35μm standard CMOS process are designed and measured. Using the extracted capacitance value from this CBCM technique, the quantum efficiency and dark current of CMOS APS can be accurately predicted .The proposed methods for parameters extraction in a CMOS APS are proven to provide high accuracy without the need of large-area test patterns.
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Chen, Pao-Yuan, and 陳保源. "Capacity planning for CMOS Image Sensor wafer reconstruction company." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/tsu245.
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碩士<br>國立交通大學<br>管理學院工業工程與管理學程<br>103<br>Capacity planning in CMOS Image Sensor wafer reconstruction (Wafer reconstruction, RW) industry includes aggregate planning and tool assignment. Aggregate planning is a quarterly decision that determines weekly production level of different products. Tool assignment is a weekly decision that matches products and tools. Conventionally, these decisions are determined based on experience. Thus the decision process is very time consuming, and the decision quality has room for improvement. The objective of this thesis is to propose a new optimization-based decision framework to resolve the problem. Considering all constraints and production parameters, new decision modules are implemented on excel solver. The new modules significantly enhance the decision quality and shorten the decision time.
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He, Ren-Ruei, and 何仁睿. "Detection Platform of Cell Migration using CMOS Image Sensor." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/56670018536844468341.
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碩士<br>國立暨南國際大學<br>電機工程學系<br>102<br>This thesis presents a cell migration sensor chip which contains CMOS image
sensor array (CIS) and a successive approximation register (SAR) ADC. The migration
activity of living cells placed directly on the surface of the image sensor chip is
converted into electronic signal by the sensor chip. The fixed-pattern noise is removed
through correlated double sampling circuit. The SAR ADC is then employed to convert
the sensed signal into digital format for displaying, storage and analysis on the detection
platform.
To verify the cell migration sensor chip, a prototype chip with 8×8 image sensor
array is implemented using TSMC 0.18μm 1P6M CMOS process provided by CIC. The
CMOS image sensor has a fill factor of about 67.85% and consumes less than 60.76μW.
The measurement results of the ADC show that the SNDR and ENOB are 51.46dB and
8.26-bit, respectively, at 2MS/s sampling rate and 52.897k Hz input frequency with
power consumption of 108.41μW at 1.8V supply voltage. The FOM is 169.77
fJ/conversion. The whole chip area is 880μm×880μm, and the power consumption is
less than 169.17μW.
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Chang, Jui-YU, and 張瑞譽. "Wide dynamic range CMOS image sensor with multiple sampling." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/09376792647015469346.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>95<br>Recently, many papers proposed the characteristic of the logarithmic output response was suitable to human eye’s sensitivity. Dynamic range is the ratio of the largest
non-saturating signal to the smallest detectable signal, which is a critical figure of merit for image sensor. Hence the CMOS image sensor which has high dynamic range and logarithmic output response are many people’s objectives. But in order to complete the above objectives, the complex of the hardware often increase.
In this thesis, we proposed a novel multiple sampling scheme based on the architecture of the digital pixel sensor (DPS). The output from the pixel is digital format.
This will lead to very high readout speed. This novel sampling scheme has the advantages of high dynamic range, logarithmic output response, lower complexity of the hardware and high speed capturing simultaneously.
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Lee, Hui-Yu, and 李輝宇. "Thermal Analysis And Reliability Test For CMOS Image Sensor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/43014006181526943867.
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碩士<br>義守大學<br>機械與自動化工程學系碩士班<br>94<br>Due to huge demand for optical mouse, digital cameras, photo-mobile phones, web-cam and optoelectronic devices in home entertainment in recent years, the production and packaging techniques for CMOS image sensor (CIS) have been rapidly developed and improved. The CIS will gradually become main product to take over CCD camera for its low price and high performance.
The reliability and thermal design for CMOS image sensor has been fully studied in this paper. It has been found that uv glue and solder paste are much easiest to failure in thermal fatigue for CIS structure. Therefore, it would be an important issue to choose suitable materials for CIS package. The thermal and moisture-absorption characteristic of uv glue and molding compound (Dam) for CIS have been studied in this paper. In addition, the predicted thermal fatigue life for different series of lead-free SnAgCu solder paste has been conducted in this research.
Because the coefficient of thermal expansion (CTE) of the air is much greater than other materials and the rate of absorbed moisture is faster than other polymer materials, it is important to develop an effective moisture-resistant mechanism for CIS package, which has been carefully studied in this paper.
A three-dimensional solid model of CMOS image sensor based on finite element ANSYS software is developed to predict the thermal-induced strain, stress distributions, and the hygroscopic swelling strain. The predicted thermal-induced displacements were found to be excellent agreement with the Moir? Interferometry experimental in-plane deformation. In this paper, the application of sub-model scheme in thermal cycle test prediction was also studied for its efficiency and interesting in recent years.
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Chen, Po-Yu, and 陳柏宇. "The Simulation of 0.11um CMOS Technology for Back Side Illumination CMOS Image Sensor." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/81443192844142501237.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>104<br>Back Side Illuminated(BSI) image sensor not only reduce the noise problem of early CMOS image sensor(CIS), but also significantly improve the ability to detect dark environment which once was one of the weaknesses of Front Side Illuminated(FSI) image sensor, making the BSI-CIS become the mainstream of image sensor. However, with the CMOS process and pixel size continuous shrink down, BSI-CIS has encountered some new problem.
For the main purpose of this essay is to use TCAD stimulation platform for processing the stimulation of 0.11um CMOS technology for BSI-CIS, and observe the effect of implant concentration on the image sensor. Fourth more, we hope to use the outcome to assist the direction of the process, and in the end create a better image sensor.
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Tsai, Chia-Yang, and 蔡嘉洋. "Design of locally-scanning CMOS Image Sensor for block-based Image processing applications." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/46057719321212987091.
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碩士<br>國立交通大學<br>電機學院電機產業專班<br>97<br>The purpose of this thesis is to design a CMOS Image Sensor which can reduce the area of post-processing buffer memory, caused by pixel output order of raster scan and processing sequence of block-based image processing system does not match, to reduce cost and power consumption. This thesis designs two kinds of locally-scanning CMOS Image Sensor, block-scanning CMOS Image Sensor and locally-raster-scanning CMOS Image Sensor. To compare with raster-scanning CMOS Image Sensor, locally-scanning CMOS Image Sensor can reduce over 95% area of post-processing buffer memory and also can save at most 48.8309% energy consumption.
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Shun-Wen, Hsiao. "Electrical and Optical Simulation of CMOS Image Sensor and Microlens." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2107200620105700.
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莊英傑. "A Nonlinear A/D Converter Design for CMOS Image Sensor." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/01548886882305031377.
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碩士<br>國立清華大學<br>電機工程學系<br>90<br>Advantage of CMOS image sensor such as high integration and low power makes this kind of image sensor have its position. But tradeoff between dynamic range and output swing is undesirable. In this thesis, a nonlinear A/D converter design for CMOS image sensor is described and designed with a 0.35 um 1P4M process. The nonlinear transfer function of the proposed A/D converter changes the resolution distribution of the output data, thereby improving the overall sensor’s resolution in low illumination and overcoming the effect of the sharp break point in the pixel cell’s photo-electrical characteristic.
The A/D converter uses successive-approximation register architecture with current-mode D/A converter. It has input range of 0V to 1.5V and 8-bit output data. The total power consumption is 17.12mW and the total area is about 240000 um2.
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鄭喬任. "Design of CMOS Image Sensor Geometry and Micro-lens Structure." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/20897757087537649003.
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碩士<br>國立清華大學<br>電子工程研究所<br>93<br>Due to the CMOS technology scaling, the smaller imaging pixels provide higher resolution application. As doping concentration in a photodiode increases, the sensitivity of a pixel becomes lower. The cross-talk effect due to light scattering to adjacent cells is getting worse as pixel size reduces. Therefore, the optical issue should be considered carefully. In this work, two major subjects are investigated. First, modifying photodiode layout to achieve better pixel performance. From the experiments results, rounded corner photodiode can achieve lower dark current. In addition, a two-dimensional optical pixel model is proposed to study the micro-lens design and cross-talk effect due to light scattering. By optical and electrical simulation using MEDICI program, the pixel performance when micro-lens parameters and photodiode area design is discussed. Light Spot Color Filtering based on this model is proposed to replace Color Filter Array application. This model also allows for cross-talk simulation and cross-talk suppression effects as a result of different blocking materials. From simulation results, the metal can block the obliquely incident light efficiently. This study can help sensor designers not only to understand the ray trace in a sensor pixel but also serve as a reference for pixel and micro-lens design.
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Hsiao, Shun-Wen, and 蕭舜文. "Electrical and Optical Simulation of CMOS Image Sensor and Microlens." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/14867253281295880647.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>94<br>This thesis focuses on simulation of solid-state image sensor. The parameters used are based on complementary metal-oxide-semiconductor process (CMOS) and CMOS image sensor (CIS) technology. The characteristics of a solid-state image sensor could be divided into two parts – electrical and optical. In this work, both of them are combined into one simulation structure, therefore, provide a good way to understand and design a pixel.
The simulation of fundamental behavior of p-n photodiode and pinned photodiode is presented. And then optical structure, microlens, is put into the consideration together with photodiode simulation. The photoresponse mentioned in the following discussion is in terms of photocurrent of photodiode.