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Relevant bibliographies by topics / CMOS integrated circuits / Dissertations / Theses

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Dissertations / Theses on the topic 'CMOS integrated circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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1

Chen, Yonggang Suhling J. C. Jaeger Richard C. "CMOS stress sensor circuits." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Fall/Dissertations/CHEN_YONGGANG_42.pdf.

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2

Nissinen, J. (Jan). "Integrated CMOS circuits for laser radar transceivers." Doctoral thesis, Oulun yliopisto, 2011. http://urn.fi/urn:isbn:9789514295454.

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Abstract The main aim of this work was to design CMOS receiver channels for the integrated receiver chip of a pulsed time-of-flight (TOF) laser rangefinder. The chip includes both the receiver channel and the time-to-digital converter (TDC) in a single die, thus increasing the level of integration of the system, with the corresponding advantages of a cheaper price and lower power consumption, for example. Receiver channels with both linear and leading edge timing discriminator schemes were investigated. In general the receiver channel consists of a preamplifier, a postamplifier and a timing co

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3

Woo, Sang Hyun. "Low noise RF CMOS receiver integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50127.

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The objective of this research is to design and implement low-noise wideband RFIC components with CMOS technology for the direct-conversion architecture. This research proposes noise reduction techniques to improve the thermal noise and flicker noise contribution of a low noise amplifier (LNA) and a mixer. Of these techniques, the LNA is found to reduce noise, boost gain, and consume a relatively low amount of power without sacrificing the wideband and linearity advantages of a conventional common gate (CG) topology. The research concludes by investigating the proposed mixer topology, which se

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4

Fayed, Ayman Adel. "Adaptive techniques for analog and mixed signal integrated circuits." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1097519730.

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Thesis (Ph. D.)--Ohio State University, 2004.<br>Title from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).

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5

Rabe, Dirk. "Accurate power analysis of integrated CMOS circuits on gate level." [S.l.] : [s.n.], 2001. http://deposit.ddb.de/cgi-bin/dokserv?idn=962733520.

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6

SamadiBoroujeni, MohammadReza. "High performance CMOS integrated circuits for optical receivers." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1108.

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7

Fan, Xinyue. "Intra-gate fault diagnosis of CMOS integrated circuits." Thesis, University of Oxford, 2006. http://ora.ox.ac.uk/objects/uuid:0cd2ed35-1e98-427e-a402-a27fd50752d1.

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Knowing the root cause of why an Integrated Circuit (1C) device fails to function properly is the key to provide the corrective measures to increase the yield and shorten the time to market. In recent years, electrical fault diagnosis method has received growing attention due to the effective and indispensable guiding role it plays in modern fault localization practice when physical measures are more and more confined by the shrinking feature size and condensed internal structure. While most of the fault diagnosis tools are based on gate level fault models, many faults are actually at the tran

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8

Smith, Anthony V. W. "Implementation of neural networks as CMOS integrated circuits." Thesis, University of Edinburgh, 1988. http://hdl.handle.net/1842/11408.

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This thesis describes research into the VLSI implementation of neural networks. A novel approach is detailed, which uses streams of pulses to signal neural states and chopping clocks to perform multiplication on these streams of pulses. Practical results, using custom VLSI devices, are presented. A second approach uses reduced precision arithmetic as the basis of a digital neural simulator and shows how this arithmetic technique can be used to solve neural problems. Simulation results confirm the viability of this method.

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9

Bhattacharya, Ritabrata. "Programmable and broadband CMOS radio frequency integrated circuits." Thesis, IIT Delhi, 2016. http://eprint.iitd.ac.in:80//handle/2074/8188.

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10

Neto, Murillo Fraguas Franco. "Técnica para o projeto de um amplificador operacional folded cascode, classe AB, em tecnologia CMOS." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-05092006-152855/.

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A tendência mundial em torno de sistemas SoC System on Chip baseados em processo CMOS Complementary Metal Oxide Semiconductor digital, apresenta cada vez mais desafios aos projetistas de circuitos integrados. Em especial se observa que enquanto os projetistas de circuitos digitais podem contar com bibliotecas cada vez mais completas de células digitais semi-prontas e ferramentas cada vez mais poderosas para o aprimoramento do projeto, os projetistas analógicos não contam com tais facilidades, sendo necessário realizar o projeto de novas células analógicas para cada especificação recebi

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11

Bollinger, S. Wayne. "Hierarchical test generation for CMOS circuits." Diss., This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-07282008-134708/.

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12

Miranda, Fernando Pedro Henriques de. "Estudo e projeto de circuitos dual-modulus prescalers em tecnologia CMOS." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14122006-154818/.

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Este trabalho consiste no estudo e projeto de circuitos Dual-Modulus Prescaler utilizados em sistemas de comunicação RF (radio frequency). Sistemas de comunicação RF trabalham em bandas de freqüência pré-definidas e dentro destas há, normalmente, vários canais para transmissão. Neste caso, decidido o canal onde se vai trabalhar, o receptor e o transmissor geram, através de um circuito chamado Sintetizador de Freqüências, sinais que têm a freqüência igual a freqüência central do canal utilizado. Esses sinais ou tons são empregados na modulação e demodulação das informações transmitidas ou receb

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13

Huang, Qin. "Devices and technology for CMOS compatible power integrated circuits." Thesis, University of Cambridge, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.240973.

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14

Jiang, Wenjie 1963. "Hot-carrier reliability assessment in CMOS digital integrated circuits." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/47514.

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15

Constantinou, L. "Novel CMOS integrated current driver circuits for bioimpedance measurements." Thesis, University College London (University of London), 2014. http://discovery.ucl.ac.uk/1458860/.

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Bioimpedance spectroscopy is a study of the variation of tissue’s electrical properties, both conductive and dielectric, through a frequency spectrum (100Hz to 1MHz). It involves the application of AC signals to the surface of the tissue via electrode pairs, which can either be a current signal or a voltage signal, and the resulting surface signals are recorded via a separate or the same pair. The recorded signals are converted to impedance measurements via a demodulation procedure. The study of tissue’s electrical properties can provide with useful information regarding both its physiology an

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16

Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.

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17

Subramanian, Viswanathan. "Enabling techniques for Si integrated transceiver circuits." Berlin mbv, 2009. http://d-nb.info/998051705/04.

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18

Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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19

Maiuri, Ovidio V. "Testing of digital CMOS integrated circuits : the multidimensional testing paradigm." Thesis, University of Oxford, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299132.

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20

Kilic, Yavuz. "Testing techniques and fault simulation for analogue CMOS integrated circuits." Thesis, University of Southampton, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.390727.

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21

Murji, Rizwan Deen M. Jamal. "Low-power CMOS radio frequency integrated circuits for frequency synthesis /." *McMaster only, 2005.

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22

Kwon, Ohsang. "On high performance multiplier design using dynamic CMOS circuits /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004310.

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23

Sagahyroon, Assim Abdelrahman. "An intelligence driven test system for detection of stuck-open faults in CMOS sequential circuits." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184763.

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This paper discusses an intelligence driven test system for generation of test sequences for stuck-open faults in CMOS VLSI sequential circuits. The networks in system evaluation are compiled from an RTL representation of the digital system. To excite a stuck-open fault it is only necessary that the output of the gate containing the fault take on opposite values during two successive clock periods. Excitation of the fault must therefore constrain two successive input/present-state vectors, referred to in the paper as the pregoal and goal nodes respectively. An initialization procedure is used

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24

Larson, Bruce C. (Bruce Carl). "Design considerations for minimizing noise in micropower CMOS integrated circuits." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/40228.

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25

Guo, Xiaoling. "CMOS intra-chip wireless clock distribution." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0011427.

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26

Deshpande, Sandeep. "A cost quality model for CMOS IC design." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020251/.

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27

Hildreth, Scott A. "Statistical SPICE parameter extraction for an N-Well CMOS process /." Online version of thesis, 1995. http://hdl.handle.net/1850/12177.

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28

Wang, Fan Agrawal Vishwani D. "Soft error rate determination for nanometer CMOS VLSI circuits." Auburn, Ala, 2008. http://hdl.handle.net/10415/1517.

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29

Massingham, John William. "A design technique for mixed ECL and CMOS circuitry." Thesis, University of Aberdeen, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241357.

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In this thesis, the principles of mixing ECL and CMOS technologies have been investigated with the intention of increasing the operating speed of synchronous systems. To achieve this, the design will be primarily CMOS based with the critical path implemented in ECL to reduce the delay and hence improve the execution time. Logic conversion circuitry between the two technologies has been designed, with the CMOS-ECL conversion circuit being a simple enhancement of the basic ECL current switch and ECL-CMOS translation being achieved with 0.5ns using a "double inverter circuit". To reduce the power

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30

Wang, Zhenhua. "Current-mode analog integrated circuits and linearization techniques in CMOS technology /." [S.l.] : [s.n.], 1990. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=9188.

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31

Zhu, Yongdong. "Parasitic-aware design and layout for RF CMOS analogue integrated circuits." Thesis, University of Essex, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.442535.

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32

Salem, Jebreel Mohamed Muftah. "A Reliable CMOS Receiver for Power Line Communications in Integrated Circuits." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/30942.

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Power line communications (PLC) in integrated circuits (ICs) was proposed by Dr. Dong S. Haâ group in 2005. Their goal was to utilize the power distribution network for data communications as well as delivery of power, so that the routing overhead can be avoided and the number of pins in the chip can be reduced. Dr. Haâ s group demonstrated through measurements the existence of pass-bands in the power distribution networks and the feasibility of power line communications in ICs. Several PLC receivers were developed to recover data superimposed on the power lines of an IC. This thesis res

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33

Chen, Xi. "Contribution to electromagnetic emission. Modeling and characterization of CMOS integrated circuits." Toulouse, INSA, 2000. http://www.theses.fr/2000ISAT0024.

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La reduction de l'emission parasite est devenue une contrainte majeure dans la conception des circuits integres. Portant initialement sur les equipements electroniques, la contrainte de compatibilite electromagnetique s'est repercutee sur le composant lui meme, du fait de l'evolution technologique et de l'avenement des systemes sur puce. Les circuits integres doivent de ce fait etre selectionnes, ainsi que leurs composants environnants, de maniere a respecter les contraintes cem de l'equipement. Cependant, le comportement cem du composant fait encore rarement partie de la specification initial

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34

Xuan, Xiangdong. "Analysis and design of reliable mixed-signal CMOS circuits." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-08032004-185515/unrestricted/xuan%5Fxiangdong%5F200412%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Singh, Adit, Committee Member ; Chatterjee, Abhijit, Committee Chairl May, Gary, Committee Member ; Keezer, David, Committee Member ; Swaminathan, Madhavan, Committee Member. Vita. Includes bibliographical references.

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35

Leite, Bernardo. "Design and modeling of mm-wave integrated transformers in CMOS and BiCMOS technologies." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2011. http://tel.archives-ouvertes.fr/tel-00667744.

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Les systèmes de communication sans fil en fréquences millimétriques ont gagné considérablement en importance au cours des dernières années. Des applications comme les réseaux WLAN et WPAN à 60 GHz, le radar automobile autour de 80 GHz ou l'imagerie à 94 GHz sont apparues, demandant un effort conséquent pour la conception des circuits intégrés émetteurs et récepteurs sur silicium. Dans ce contexte, les transformateurs intégrés sont particulièrement intéressants. Ils peuvent réaliser des fonctions comme l'adaptation d'impédance, la conversion du mode asymétrique au différentiel et la combinaison

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36

Lu, Yuanlin. "Power and performance optimization of static CMOS circuits with process variation." Auburn, Ala., 2007. http://repo.lib.auburn.edu/07M%20Dissertations/LU_YUANLIN_28.pdf.

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37

STENGER, VINCENT EDWARD. "VERTICAL MULTIMODE INTERFERENCE OPTICAL WAVEGUIDE TAPS FOR SILICON CMOS CIRCUITS." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1069795415.

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38

Kasturi, Prasan. "A CAD tool for analog and mixed signal CMOS circuits /." View online ; access limited to URI, 2006. http://0-digitalcommons.uri.edu.helin.uri.edu/dissertations/AAI3248232.

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39

Matres, Abril Joaquín. "Ultrafast, CMOS compatible, integrated all optical switching." Doctoral thesis, Universitat Politècnica de València, 2014. http://hdl.handle.net/10251/37984.

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El proyecto consistirá en implementar funcionalidades fotónicas avanzadas sobre silicio tales como conmutación ultra rápida o la realización de puertas lógicas todo ópticas. Para ello se emplearán efectos no lineales del silicio basados en el efecto Kerr, producido por el coeficiente no lineal de tercer orden chi(3) .Los dispositivos deberán funcionar al menos a 40Gbps para que sean competitivos con los dispositivos actuales de última generación. También deberán ser compatibles con tecnología CMOS, lo cual es crucial para que la fabricación se pueda realizar a gran escala a precios competitivo

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40

Johnstone, Kevin Kennedy. "On the nature and effect of power distribution noise in CMOS digital integrated circuits." Thesis, Middlesex University, 1991. http://eprints.mdx.ac.uk/13368/.

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The thesis reports on the development of a novel simulation method aimed at modelling power distribution noise generated in digital CMOS integrated circuits. The simulation method has resulted in new information concerning: 1. The magnitude and nature of the power distribution noise and its dependence on the performance and electrical characteristics of the packaged integrated circuit. Emphasis is laid on the effects of resistive, capacitative and inductive elements associated with the packaged circuit. 2. Power distribution noise associated with a generic systolic array circuit comprising 1,0

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41

Ross, Kyle Gene. "Distributed amplifier circuit design using a commercial CMOS process technology." Thesis, Montana State University, 2006. http://etd.lib.montana.edu/etd/2006/ross/RossK0806.pdf.

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42

Noe, Sidney Scott. "Alternative gate designs for improved radiation hardness in bulk CMOS integrated circuits." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1997. http://handle.dtic.mil/100.2/ADA331678.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 1997.<br>"March 1997." Thesis advisor(s): Douglas J. Fouts. Includes bibliographical references (p. 233-235). Also available online.

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43

Iyer, Gopal Balakrishnan. "Digital communication and control circuits for 60ghz fully integrated CMOS digital radio." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/39589.

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Emerging "bandwidth hungry" applications such as high definition video distribution and ultra fast multimedia side-loading have extended the need for multi-gigabit wireless solutions beyond the reach of conventional WLAN technology or even more recently emerging UWB and MIMO systems. The availability of 7GHz of unlicensed bandwidth in the 60GHz spectrum, represents a unique opportunity to address such data-throughput requirements. The 60GHz Integrated CMOS digital radio chipset comprises of PHY and MAC layers, RF transceiver, High-Speed Digital Interface and an underlying Serial Communication

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44

Madathil, Sankara Narayanan Ekkanath. "CMOS compatible lateral MOS controlled power devices for High Voltage Integrated Circuits." Thesis, University of Cambridge, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.240223.

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45

Long, Ethan Schuyler. "The Role of Temperature in Testing Deep Submicron CMOS ASICs." PDXScholar, 2003. https://pdxscholar.library.pdx.edu/open_access_etds/34.

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Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characterist

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46

Aziz, Syed Mahfuzul. "The realisation of high-speed, testable multipliers suitable for synthesis using differential CMOS circuits." Thesis, University of Kent, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.240166.

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47

Park, Byeong-Ha. "A low-voltage, low-power, CMOS 900MHZ frequency synthesizer." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/16686.

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48

Hincapié, Jorge Armando Oliveros. "Aplicação da programação geométrica no projeto de filtros Gm-C para receptores RF CMOS." Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-19012011-131843/.

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A tendência do mercado da microeletrônica é integrar em um mesmo chip sistemas eletrônicos completos, incluindo simultaneamente circuitos analógicos, digitais e RF. Por causa da complexidade do problema de projeto, a parte analógica e RF desses sistemas é o gargalo do desenvolvimento. Uma alternativa de projeto para circuitos analógicos é formular o projeto como um problema de otimização matemática conhecido como programação geométrica. As vantagens são: o ótimo global é obtido eficientemente, e é possível fazer automatização do projeto. A principal desvantagem é que não todos os parâmetros e

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49

Palacio, Jose Alejandro Amaya. "Gerador de sinais para aplicação da espectroscopia de bioimpedânica elétrica na detecção de câncer." Universidade de São Paulo, 2017. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-27092017-091615/.

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No intervalo de valores de frequência de poucos kHz até 1 MHz, nomeado às vezes como região de dispersão ?, as estruturas das células são o principal determinante da impedância do tecido. Esse é o fundamento básico da Espectroscopia da Bioimpedância Elétrica - EBE, a qual tem importância significativa como ferramenta de diagnóstico do câncer de colo no útero - CCU. A EBE consiste na medição de impedância elétrica do tecido cervical para diferentes valores de frequência. A diferença do comportamento no valor da impedância na frequência entre o tecido normal e o cancerígeno é usada para detectar

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50

Layton, Kent D. "Low-voltage analog CMOS architectures and design methods /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2141.pdf.

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