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Journal articles on the topic 'CMOS integrated circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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1

Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

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Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF cir

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2

Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

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Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices

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3

Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to

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4

Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.

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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits bec

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Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circu

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WANG, WEIZHI, and DONGMING JIN. "CMOS DESIGN OF ANALOG FUZZY SYSTEM." Journal of Circuits, Systems and Computers 14, no. 06 (2005): 1101–12. http://dx.doi.org/10.1142/s0218126605002830.

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This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high p

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7

Kleinfelder, S., F. Bieser, Yandong Chen, et al. "Novel integrated CMOS sensor circuits." IEEE Transactions on Nuclear Science 51, no. 5 (2004): 2328–36. http://dx.doi.org/10.1109/tns.2004.836150.

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8

Clark, David T., Ewan P. Ramsay, A. E. Murphy, et al. "High Temperature Silicon Carbide CMOS Integrated Circuits." Materials Science Forum 679-680 (March 2011): 726–29. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.726.

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The wide band-gap of Silicon Carbide (SiC) makes it a material suitable for high temperature integrated circuits [1], potentially operating up to and beyond 450°C. This paper describes the development of a 15V SiC CMOS technology developed to operate at high temperatures, n and p-channel transistor and preliminary circuit performance over temperature achieved in this technology.

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9

Thompson, R. F., D. T. Clark, A. E. Murphy, et al. "High Temperature Silicon Carbide CMOS Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (2011): 000115–19. http://dx.doi.org/10.4071/hiten-paper5-dclark.

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The wide band-gap of Silicon Carbide makes it a material suitable for IC's [1] operating up to 450°C. The maximum operating temperature achieved will depend on the transistor technology selected, interconnect metallisation and device packaging. This paper describes transistor and circuit results achieved in SiC CMOS technology, where the major issue addressed is the gate dielectric performance. N and p-channel MOSFET structures have been demonstrated operating at temperatures up to 400°C Test circuits including simple logic cells, ring oscillators, operational amplifiers and gate drive circuit

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10

ALARCÓN, EDUARD, GERARD VILLAR, and ALBERTO POVEDA. "CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS." Journal of Circuits, Systems and Computers 13, no. 04 (2004): 789–811. http://dx.doi.org/10.1142/s0218126604001714.

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Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS

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11

Chen, Jiahao. "Integrated circuit design based on CMOS technology principle and its application in GPU." Theoretical and Natural Science 12, no. 1 (2023): 141–46. http://dx.doi.org/10.54254/2753-8818/12/20230454.

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In today's society, the application of integrated circuit technology can be seen everywhere, especially in the past two decades. This paper mainly studies the principle and design of CMOS devices in IC technology and discusses the research and analysis of the acceleration algorithm of IC design. This paper adopts the research method of literature review and analysis to summarize the existing research results. This paper first introduces the development background of integrated circuit technology and the importance of CMOS technology. Subsequently, the concept and interconnection principle of C

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12

Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

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Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100

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13

Chang, Chun-Rong, Zih-Jyun Dai та Chun-Yu Lin. "π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology". Materials 16, № 7 (2023): 2562. http://dx.doi.org/10.3390/ma16072562.

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CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustnes

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14

Vera Casañas, César William, Thainann Henrique Pereira de Castro, Gabriel Antonio Fanelli de Souza, Robson Luiz Moreno, and Dalton Martini Colombo. "Review of CMOS Currente References." Journal of Integrated Circuits and Systems 17, no. 1 (2022): 1–9. http://dx.doi.org/10.29292/jics.v17i1.592.

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A current reference is able to provide a precise and accurate current for other circuits inside a chip. This type of electronic circuit is employed as a building block in numerous analog and mixed-signal circuits. Moreover, it is a fundamental component of current-mode circuits. This work discusses the basic and essential concepts of designing CMOS integrated current references. A review of conventional topologies is presented, including current mirrors and current references. Temperature dependence is discussed, along with PTAT and CTAT topologies, and some low-power/low-voltage implementatio

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Jendernalik, Waldemar, Jacek Jakusz, Grzegorz Blakiewicz, Stanisław Szczepański та Robert Piotrowski. "Characteristics of an Image Sensor with Early-Vision Processing Fabricated in Standard 0.35 μm Cmos Technology". Metrology and Measurement Systems 19, № 2 (2012): 191–202. http://dx.doi.org/10.2478/v10178-012-0017-8.

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Characteristics of an Image Sensor with Early-Vision Processing Fabricated in Standard 0.35 μm Cmos TechnologyThe article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 μm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of

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16

Shanmuga Raju, S., and B. Paulchamy. "Development and Optimization of a Penta-Magnetic Tunnel Junction Circuit Integrated with Hybrid Transmission Gate Logic for Efficient Low-Power and High-Speed Performance." Journal of Nanoelectronics and Optoelectronics 19, no. 12 (2024): 1347–59. https://doi.org/10.1166/jno.2024.3701.

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In response to the ever-increasing need for fast, low-power circuits, conventional CMOS-based designs are becoming increasingly unsuitable, particularly for use in logic circuits and memory devices. The multi-state behavior of Magnetic Tunnel Junction (MTJ) circuits has attracted attention because of their potential in non-volatile memory and logic operations. To achieve the targeted reductions in power consumption and increases in switching speed, it is essential to integrate these circuits with performance-optimizing logic gates. To overcome the drawbacks of traditional circuits, we present

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17

Goswami, Neelaksha, and Satendra Singh. "Learning on Proposal and Optimization of Stumpy Influence CMOS Transconductance Operational Amplifier." RESEARCH REVIEW International Journal of Multidisciplinary 6, no. 12 (2021): 184–90. http://dx.doi.org/10.31305/rrijm.2021.v06.i12.028.

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Portable systems, such as wireless communication systems, laptops, smart phones, consumer electronics, and implanted medical devices, are in high demand in the rapidly expanding consumer market. When it comes to extending the running duration of these portable devices, low-power and low-voltage integrated circuits are used almost universally to achieve this. The design of an analogue integrated circuit with somewhat excellent processing characteristics, when compared to its digital equivalent, is a difficult undertaking, especially when it comes to applications requiring low voltage and low po

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18

Li, Ruotong. "Analysis of Delay Limitation and Circuit Power Balance Optimisation for CMOS Based Circuits." Transactions on Computer Science and Intelligent Systems Research 5 (August 12, 2024): 355–60. http://dx.doi.org/10.62051/505v3198.

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As integrated circuits and technology have advanced, people's requirements for integrated circuits are getting higher and higher, and integrated circuits with high performance, low latency and low power consumption characteristics are needed to satisfy all kinds of human needs. However, meeting these needs requires a balanced optimization of circuit delay and energy consumption. The gate size and voltage need to be varied simultaneously, and the most suitable voltage and gate are found by combining the gate size and voltage ratio using a linear programming solver. This method can find the opti

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19

Niitsu, Kiichi, and Kazuo Nakazato. "Biosensor Integrated Circuits Using CMOS Technology." IEEJ Transactions on Sensors and Micromachines 137, no. 10 (2017): 291–95. http://dx.doi.org/10.1541/ieejsmas.137.291.

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20

MOUFTAH, H. T., and K. C. SMITH. "CMOS integrated circuits for multivalued logic." International Journal of Electronics 58, no. 1 (1985): 43–50. http://dx.doi.org/10.1080/00207218508939001.

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21

Kostov, P., K. Schneider-Hornstein, and H. Zimmermann. "Phototransistors for CMOS Optoelectronic Integrated Circuits." Sensors and Actuators A: Physical 172, no. 1 (2011): 140–47. http://dx.doi.org/10.1016/j.sna.2011.03.056.

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22

Yordanov, Hristomir, and Peter Russer. "Antennas embedded in CMOS integrated circuits." Facta universitatis - series: Electronics and Energetics 23, no. 2 (2010): 169–77. http://dx.doi.org/10.2298/fuee1002169y.

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In this work we propose novel integrated antennas for chip-to-chip wireless interconnects. In order to save chip area, the available CMOS circuit ground planes can be used as radiating elements. The interference between the integrated antennas and the on-chip circuit interconnects should be minimised. This can be obtained by introducing a transformer in the antenna feeding network.

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23

Sharroush, Sherif. "Analog CMOS Design in Nanometer Regime." Jordan Journal of Electrical Engineering 10, no. 4 (2024): 1. http://dx.doi.org/10.5455/jjee.204-1703756483.

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There is no doubt that the short-channel effects have affected the analysis and design of modern analog CMOS integrated circuits significantly. Thus, models that take into account these effects must be adopted in order to obtain more accurate results. In this paper, the AC small-signal low-frequency equivalent circuit of the short-channel MOSFET transistor is developed using an appropriate model. The impact of short-channel effects on the operation of basic building blocks of analog integrated circuits such as basic amplifier configurations, cascode stage, differential amplifier and composite

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24

B, Harshitha. "An Area and Power Optimization for Level Shifters using 45nm CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 4951–55. http://dx.doi.org/10.22214/ijraset.2024.62674.

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Abstract: Modern integrated circuits require level shifters as essential parts to enable communication between circuits running at various voltage levels. Design-wise, the Level Shifter has a minimal silicon footprint due to its limited component count and operates with minimal power usage, making it well-suited for energy-efficient applications. This work implements CMOS voltage level shifter, also known as conventional CMOS level shifter. The level shifter's overall power and area usage are compared. CMOS level shifters simulations are carried out using CADENCE tool. The simulation's outcome

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25

Li, Mingzhe. "A Method for Reducing Offset in CMOS Operational Amplifiers." Applied and Computational Engineering 128, no. 1 (2025): 37–42. https://doi.org/10.54254/2755-2721/2025.20230.

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In the development of integrated circuits, operational amplifiers are indispensable basic units CMOS operational amplifiers are the core components in analog integrated circuits, which are widely used in signal acquisition, data processing, communications and other fields. components in analog integrated circuits, which are widely used in signal acquisition, data processing, communications and other fields, and their performance has a direct impact on the accuracy and stability of the entire system. With the continuous development of electronic technology, CMOS operational amplifiers play a vi

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26

Rakús, Matej, Viera Stopjaková, and Daniel Arbet. "Design techniques for low-voltage analog integrated circuits." Journal of Electrical Engineering 68, no. 4 (2017): 245–55. http://dx.doi.org/10.1515/jee-2017-0036.

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AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or

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27

Thakur, Randhir P. S., Yuanning Chen, Edward H. Poindexter, and Rajendra Singh. "Silicon-Based Ultrathin Dielectrics." Electrochemical Society Interface 8, no. 2 (1999): 20–23. http://dx.doi.org/10.1149/2.f05992if.

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The phenomenal sustained growth of the electronics industry in the last three decades is primarily due to the success of silicon integrated circuit technology. As compared to any other technology, complementary metal-oxide silicon (CMOS) transistor based integrated circuits have dominated the field of semiconductor manufacturing.

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Yang, Yuntao. "Basic Failure Modes of CMOS Devices and the Improvements." Applied and Computational Engineering 128, no. 1 (2025): 13–17. https://doi.org/10.54254/2755-2721/2025.20228.

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Mosfets are the most important and basic part of integrated circuits, which the modern information network relies on. Combing a great number of mosfets, most integrated circuits would require the constituent part of themselves work in a stable and reliable state. Though, having been improved both in materials and constructures for tens of years, various types of mosfets still face the great danger of failure. This article would generally introduce this important issue of integrated circuit both on the issue and the methods of improvements, based on former researches, first making the classific

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Amgoth Laxman, Et al. "Design and Implementation of Hybrid Multiplier for DSP Applications." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 10 (2023): 623–28. http://dx.doi.org/10.17762/ijritcc.v11i10.8556.

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In recent decades, there has been a consistent reduction in feature sizes in integrated circuit (IC) technology, leading to the need for increased placement of functional circuits on each chip. When it comes to the design of digital circuits, there is a significant focus on hybrid logic. Hybrid logic is highly regarded due to its ability to consume less power while achieving higher efficiency. Hybrid logic circuits have similarities to complementary metal-oxide-semiconductor (CMOS) transistors, yet possess a reduced transistor count while offering enhanced performance and reliability capabilit

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Rohit, Kumar *. Sachin Tyagi. "DESIGN OF LOW-POWER FULL ADDER IN 0.18 µm CMOS TECHNOLOGY." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 8 (2016): 446–56. https://doi.org/10.5281/zenodo.59758.

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With the increase in device integration level and the growth in complexity of Integrated circuits, small delay and low power dissipation become important parameters as these increases performance and portability. Battery storage is limited, to extend battery life; low power operation is the primary requirement in integrated circuits. Furthermore, high speed and multiple parallel applications need high computing power, placing greater demands on energy storage elements within the system. Large power dissipation in high performance digital systems requires large size heat sinks. These off chip c

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31

SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C KHN FILTER USING VOLTAGE OP AMP, CFOA, OTRA AND DCVC." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 733–69. http://dx.doi.org/10.1142/s021812660900523x.

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MOS-C realizations of the Kerwin–Huelsman–Newcomb (KHN) circuit using the commercially available Voltage Operational Amplifier (VOA) and the Current Feedback Operational Amplifier (CFOA) are reviewed in this paper. Additional MOS-C KHN realizations using the Operational Transresistance Amplifier (OTRA) and the Differential Current Voltage Conveyor (DCVC) are also included. MOS-C realizations of the KHN circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS tech

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Lv, Hongming, Huaqiang Wu, Jinbiao Liu, et al. "Inverted process for graphene integrated circuits fabrication." Nanoscale 6, no. 11 (2014): 5826–30. http://dx.doi.org/10.1039/c3nr06904d.

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SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C TOW-THOMAS FILTER USING VOLTAGE OP AMP, CURRENT FEEDBACK OP AMP AND OPERATIONAL TRANSRESISTANCE AMPLIFIER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 151–79. http://dx.doi.org/10.1142/s0218126609004995.

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Several MOS-C realizations of the Tow-Thomas circuit using the commercially available voltage operational amplifier and the current feedback operational amplifier are reviewed in this paper. Additional MOS-C Tow-Thomas realizations using the operational transresistance amplifier and the differential current voltage conveyor are also included. MOS-C realizations of the Tow-Thomas circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS

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Iwai, Hiroshi, Kuniyuki Kakushima, and Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING." International Journal of High Speed Electronics and Systems 16, no. 01 (2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.

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The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In

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Mahnoor Maghroori and Mehdi Dolatshahi. "Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms." World Journal of Advanced Research and Reviews 12, no. 1 (2021): 215–24. http://dx.doi.org/10.30574/wjarr.2021.12.1.0427.

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This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed an

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Mahnoor, Maghroori, and Dolatshahi Mehdi. "Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms." World Journal of Advanced Research and Reviews 12, no. 1 (2021): 215–24. https://doi.org/10.5281/zenodo.5594256.

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This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully desig

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37

Sikder, Urmita, Kelsey Horace-Herron, Ting-Ta Yen, et al. "Toward Monolithically Integrated Hybrid CMOS-NEM Circuits." IEEE Transactions on Electron Devices 68, no. 12 (2021): 6430–36. http://dx.doi.org/10.1109/ted.2021.3122404.

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Mourey, Devin A., Sung Kyu Park, Dalong A. Zhao, et al. "Fast, simple ZnO/organic CMOS integrated circuits." Organic Electronics 10, no. 8 (2009): 1632–35. http://dx.doi.org/10.1016/j.orgel.2009.08.021.

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Graham, Anthony H. D., Chris R. Bowen, Jon Robbins, Georgi Lalev, Frank Marken, and John Taylor. "Nanostructured electrodes for biocompatible CMOS integrated circuits." Sensors and Actuators B: Chemical 147, no. 2 (2010): 697–706. http://dx.doi.org/10.1016/j.snb.2010.03.030.

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Cristea, Dana, F. Craciunoiu, M. Modreanu, M. Caldararu, and I. Cernica. "Photonic circuits integrated with CMOS compatible photodetectors." Optical Materials 17, no. 1-2 (2001): 201–5. http://dx.doi.org/10.1016/s0925-3467(01)00045-3.

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Delmas-Bendhia, S., F. Caignet, E. Sicard, and M. Roca. "On-chip sampling in CMOS integrated circuits." IEEE Transactions on Electromagnetic Compatibility 41, no. 4 (1999): 403–6. http://dx.doi.org/10.1109/15.809837.

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Barlow, M., A. M. Francis, and J. Holmes. "Operation of Silicon Carbide Integrated Circuits under High Temperature and Pressure." International Symposium on Microelectronics 2017, no. 1 (2017): 000526–30. http://dx.doi.org/10.4071/isom-2017-tha22_152.

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Abstract Silicon carbide integrated circuits have demonstrated the ability to function at temperatures as high as 600 °C for extended periods of time. Many environments where high temperature in-situ electronics are desired also have large pressures as well. While some validation has been done for high pressure environments, limited information on the parametric impact of pressure on SiC integrated circuits is available. This paper takes two leading-edge SiC integrated circuit processes using two different classes of devices (JFET and CMOS), and measures the performance through temperature and

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Abbas, b. NOORI. "Exploring Terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR Integrated Circuits: Advancements and Obstacles." INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY RESEARCH AND ANALYSIS 07, no. 03 (2024): 1238–43. https://doi.org/10.5281/zenodo.10851659.

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The text provides a description of the characteristics of several NMOS and CMOS circuit approaches, as well as an explanation of the limitations associated with each technology. Next, the CMOS domino circuit, a novel form of circuit, is explained. This entails interconnecting dynamic CMOS gates in a manner that enables the activation of all gates in the circuit simultaneously using a single clock edge. Consequently, there is no need for intricate clocking methods, allowing the dynamic gate to operate at its maximum speed. This circuit features a basic mode voltage-controlled oscillator operati

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Lee, Han Cheol, Eun Kyo Jung, Hwarim Im, and Yong-Sang Kim. "63‐1: Integrated Scan/Emission/Sweep Driver Circuit Based on CMOS LTPS TFTs for Micro‐LED Displays." SID Symposium Digest of Technical Papers 55, no. 1 (2024): 857–59. http://dx.doi.org/10.1002/sdtp.17667.

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We proposed a CMOS LTPS TFT‐based integrated driver circuit to generate the control signals for micro light‐emitting diode pixel circuits. The proposed circuit enables to generation of five output signals by sharing core logic without capacitors. We verified that the output signals remain stable through the simulation.

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Elmezayen, Mohamed R., Wei Hu, Amr M. Maghraby, Islam T. Abougindia, and Suat U. Ay. "Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits." Journal of Low Power Electronics and Applications 10, no. 3 (2020): 21. http://dx.doi.org/10.3390/jlpea10030021.

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Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used compleme

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Patel, Ambresh, and Ritesh Sadiwala. "Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 14, no. 02 (2022): 202–5. http://dx.doi.org/10.18090/samriddhi.v14i02.13.

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With the advancement of technology, small and handy electronic devices are built with low supply voltage and lower power dissipation in designing deep submicron static CMOS circuits. Small devices scaling down with burst-mode type integrated circuits have two major challenges: area and power dissipation. This paper presents a method for decreasing dynamic power, area, and leakage of application-specific integrated circuits without sacrificing performance. The High Threshold Leakage Control Transistor, TG-Based Technique, Supply Voltage Scaling, Sleep Transistor approaches are covered, and a dy

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Oliver Ava, Muhammad Oscar, and Tommy George. "The Impact and Prevention of Latch-up in CMOS in VLSI Design." Fusion of Multidisciplinary Research, An International Journal 1, no. 01 (2020): 1–13. https://doi.org/10.63995/vgrd5263.

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Latch-up in CMOS (Complementary Metal-Oxide-Semiconductor) technology is a significant reliability concern in VLSI (Very Large Scale Integration) design. Latch-up is a parasitic, unintended creation of a low-impedance path between the power supply rails due to the triggering of parasitic thyristor structures inherent in CMOS processes. This phenomenon can lead to device malfunction, excessive current flow, and potential permanent damage to the integrated circuit. The impact of latch-up is profound, as it compromises the stability and functionality of electronic systems, especially in high-perf

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Mark, Andrew G., Emmanuel Suraniti, Jérôme Roche, et al. "On-chip enzymatic microbiofuel cell-powered integrated circuits." Lab on a Chip 17, no. 10 (2017): 1761–68. http://dx.doi.org/10.1039/c7lc00178a.

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Lan, Zihan. "On the propagation delay of CMOS inverters." Applied and Computational Engineering 84, no. 1 (2024): 163–72. http://dx.doi.org/10.54254/2755-2721/84/20240876.

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This research study delves into the propagation delay analysis in Complementary Metal-Oxide-Semiconductor (CMOS) inverters, aiming to uncover the factors contributing to it and exploring strategies to mitigate its impact. CMOS inverters, as pivotal constituents within digital integrated circuits, play a foundational role, making a thorough understanding of their propagation delay characteristics indispensable for the design of high-performance circuit. The research encompasses a comprehensive examination of propagation delay in CMOS inverters, addressing three key factors affecting it: load ca

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Schmidt, Alexander, Holger Kappert, Wolfgang Heiermann, and Rainer Kokozinski. "A Cyclic RSD Analog-Digital-Converter for Application Specific High Temperature Integrated Circuits up to 250°C." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (2012): 000214–19. http://dx.doi.org/10.4071/hitec-2012-wp13.

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Silicon-on-Insulator (SOI) CMOS is the most commonly used technology for integrated circuits suitable for high temperatures and harsh environmental conditions. Data acquisition circuitry operating at these conditions has to consider the impact of wide temperature range operation. Therefore, the accurate operation of elementary building blocks is essential for proper system performance. To overcome the accuracy limitations set by channel leakage and performance degradation of NMOS and PMOS transistors, advanced circuit design methods are necessary. By introducing advanced leakage compensation,

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