Relevant bibliographies by topics / CMOS inverter

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'CMOS inverter'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "CMOS inverter"

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Surwadkar, Prof Tushar. "Comparison of CNTFET Inverter with CMOS Inverter." International Journal for Research in Applied Science and Engineering Technology 8, no. 6 (June 30, 2020): 2565–72. http://dx.doi.org/10.22214/ijraset.2020.6413.

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Machowski, Witold, Stanisław Kuta, Jacek Jasielski, and Wojciech Kołodziejski. "Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS Inverters." International Journal of Electronics and Telecommunications 56, no. 4 (November 1, 2010): 381–86. http://dx.doi.org/10.2478/v10177-010-0050-z.

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Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS InvertersThe paper presents quarter-square analog four-quadrant multipliers, based on proprietary architecture using four CMOS inverters. The most important upgrade on already published own circuit implementation is the use of the same inverter "core" of the circuit with completely redesigned auxiliary and steering blocks. Two variants of new driving peripherals are considered: one with differential pair, the second with CMOS inverters. The proposed circuit solutions are suitable for RF applications in communication systems due to simple architecture comprising building blocks with RF CMOS transistors having sufficiently large biasing currents. Postlayout simulation results done on the basis of 180nm CMOS UMC Foundry Design Kit are also presented.
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Kuroki, Shinichiro, Tatsuya Kurose, Hirofumi Nagatsuma, Seiji Ishikawa, Tomonori Maeda, Hiroshi Sezaki, Takamaro Kikkawa, et al. "4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics." Materials Science Forum 897 (May 2017): 669–72. http://dx.doi.org/10.4028/www.scientific.net/msf.897.669.

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For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.
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Zingg, R. P., B. Hofflinger, and G. W. Neudeck. "High-quality stacked CMOS inverter." IEEE Electron Device Letters 11, no. 1 (January 1990): 9–11. http://dx.doi.org/10.1109/55.46914.

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Bae, Woorham. "CMOS Inverter as Analog Circuit: An Overview." Journal of Low Power Electronics and Applications 9, no. 3 (August 20, 2019): 26. http://dx.doi.org/10.3390/jlpea9030026.

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.
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KABBANI, ADNAN. "COMPLEX CMOS GATE COLLAPSING TECHNIQUE AND ITS APPLICATION TO TRANSIENT TIME." Journal of Circuits, Systems and Computers 19, no. 05 (August 2010): 1025–40. http://dx.doi.org/10.1142/s021812661000658x.

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In this paper we present a technique to collapse a CMOS gate into an equivalent inverter. This technique considers deep submicron effects such as mobility degradation and velocity saturation as well as operation regions of both the NMOS and PMOS networks of the considered CMOS gate. In addition, the model accounts for the effect of the gate's internodal capacitances on the behavior of the equivalent Series Connected MOSFET Structure. Depending on the CMOS inverter transition time model presented in Ref. 1, the developed model has accurately predicted the transition time of different CMOS gates. Considering various loads, input switching, and transistor sizes, the model shows an average error of 6%, including the error introduced by the inverter model, as compared to BSIM3v3 using Spectre.
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Mun, Hye Jin, Min Su Cho, Jun Hyeok Jung, Won Douk Jang, Sang Ho Lee, Jaewon Jang, Jin-Hyuk Bae, and In Man Kang. "Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary." Journal of Nanoscience and Nanotechnology 20, no. 11 (November 1, 2020): 6616–21. http://dx.doi.org/10.1166/jnn.2020.18769.

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In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.
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KUMAR, K. KEERTI, and N. BHEEMA RAO. "POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 08 (June 18, 2014): 1450109. http://dx.doi.org/10.1142/s0218126614501096.

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In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.
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Chun-Teh Lee. "Pseudocollector effect in a CMOS inverter." IEEE Transactions on Electron Devices 34, no. 10 (October 1987): 2212–14. http://dx.doi.org/10.1109/t-ed.1987.23219.

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Talkhan, E. A. "New capabilities of the CMOS inverter." IEEE Journal of Solid-State Circuits 23, no. 3 (June 1988): 872–75. http://dx.doi.org/10.1109/4.333.

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Dissertations / Theses on the topic "CMOS inverter"

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Hafed, Mohamed M. "CMOS inverter current and delay models incorporating interconnect effects." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0025/MQ50614.pdf.

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Zhang, Duo. "DYNAMIC CMOS MIMO CIRCUITS WITH FEEDBACK INVERTER LOOP AND PULL-DOWN BRIDGE." Wright State University / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=wright1377210272.

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Šťastná, Hilda. "Simulace CMOS VLSI obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363732.

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This diploma thesis deals with processes of electrical circuits calculations in the last years' worldwide standards like Dymola, MATLAB, Maple or SPICE applications. Circuits calculations are linked with methods for solving linear differential equations, used in this work also by verification of functionality of designed models for CMOS inverter, CMOS NAND, CMOS NOR. Numerical integration method in combination with Taylor series is a suitable method also for parallel calculations of CMOS VLSI circuits. CMOS circuits simulation was implemented with this method in applications in MATLAB language, solving circuits, represented by differential equations. Functionality of the applications was verified by some real examples. Significant acceleration of calculations using Taylor series compared to other methods is an important factor in choosing methods used in circuit simulations.
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Figueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.

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Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering of the Faculdade de Ciências e Tecnologia of Universidade Nova de Lisboa
More and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, which means that, in nanotechnologies, to enhance energy and area efficiency, we can not simply depend on the benefits of this scaling. Although, a share of the efficiency can be obtained from the technology, new circuit architectures and techniques have to be developed to really push the limits of efficiency. In data converters, more specifically analog-to-digital converters (ADCs), a decision can be made: research energy and area efficient analog circuit techniques and architectures that cope with technological scaling issues, or design algorithms that use digital circuitry to assist the poor analog technological performance. The former option is the premise for the work developed in this thesis. The work reported in this thesis explores various design techniques with the purpose of enhancing the power and area efficiency of building blocks mainly to be used in multiplying digital-to-analog converter based ADCs. Therefore, novel analog techniques are developed for the three main blocks of an MDAC-based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. These techniques include self-biasing and inverter-based design for the flash quantizer and amplifier. Regarding the MDAC, it combines three techniques: unity feedback factor, insensitivity to capacitor mismatch, and current-mode reference shifting. In the second part of this work, the designed amplifier is implemented and experimentally characterized demonstrating its practical feasibility and performance. The final part of this work explores the design and implementation of a medium-low resolution high speed pipeline ADC incorporating all the developed circuits. Experimental results validate the feasibility of the techniques and demonstrate the attractiveness in terms of power dissipation and reduced area.
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Thabet, Hanen. "Validation de la chaîne d'émission pour la conception d'un capteur RF autonome." Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4314.

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Ce travail s’inscrit dans un projet consistant à développer un prototype de capteur RF autonome et intelligent permettant la réalisation d’un réseau de capteurs sans fil dans un environnement industriel. Cette thèse traite de l’étude, la conception et la réalisation de la partie radiofréquence de la chaîne d’émission sans fils du capteur RF dans la bande ISM 863-870 MHz en technologie CMOS AMS 0.35µm. Cette chaîne inclut toutes les fonctions depuis l’oscillateur local jusqu’à l’amplificateur de puissance. L’émetteur occupe une surface de 0.22mm² et consomme environ 27mA sous une tension d’alimentation de 3.3V. De nombreux principes innovants ont été mis en œuvre et validés. Tous ces principes peuvent être facilement transposés à d’autres standards de communication et dans d’autres bandes de fréquences. Les résultats de simulations du dessin des masques vérifient complètement les spécifications et confirment les simulations. Une caractérisation expérimentale partielle valide les nouvelles architectures proposées
This work joins in a project consisting in developing prototype of an autonomous and smart RF sensor allowing the realization of a wireless sensor network in an industrial environment. This thesis deals with the study, the design and the realization of the radio-frequency part of the transmitter using the 863-870 MHz ISM band and the CMOS AMS 0.35µm technology. This transmitter includes all the functions from the local oscillator to the power amplifier. The integrated circuit occupies a surface of 0.22mm² and consumes approximately 27mA under a supply voltage of 3.3V. Numerous innovative principles were implemented and validated. All these principles can be easily transposed into other standards of communication and in other frequency bands. The results of the post-layout simulation completely satisfy the specifications and confirm the simulations. Partial experimental characterization validates new architectures proposed
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Bisiaux, Pierre. "Etude et conception de CAN haute résolution pour le domaine de l’imagerie." Thesis, Université Paris-Saclay (ComUE), 2018. http://www.theses.fr/2018SACLC030/document.

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Cette thèse porte sur la conception et la réalisation de convertisseurs analogique/numérique (ADC) haute résolution dans le domaine de l’imagerie spatiale en technologie 0.18 μm.Un imageur CMOS est un système destiné à acquérir des informations lumineuses et les convertir en données numériques afin que cellesci soient traitées. Ce système est composé d’une matrice de pixels, d’ADC, de registres et de blocs de signaux de commande afin de rendre toutes ces données disponibles. Avec la taille grandissante de la matrice de pixels et la cadence d’image par seconde croissante, l’ADC doit réaliser de plus en plus de conversions en moins de temps et est donc devenu l’un des « bottleneck » les plus importants dans les systèmes d’imagerie. Une solution adaptée a donc été le développement d’ADC colonne situé en bout de colonnes de pixels afin de réaliser des conversions en parallèles et c’est ce sujet qui va m’intéresser.Dans une première partie, n’ayant pas de contraintes sur l’architecture d’ADC à utiliser, une étude de l’état de l’art des ADC pour l’imagerie est réalisée ainsi que les spécifications visées pour notre application. Une architecture sigma-delta incrémental à deux étapes semble la plus prometteuse et va être développée. Ensuite, une étude théorique de l’ADC choisi, et plus particulièrement du modulateur sigma-delta à utiliser est effectuée, afin notamment de déterminer l’ordre de ce modulateur, mais également le nombre de cycles de cette conversions. Une fois les paramètres de modélisation définis, un schéma transistor est réalisé au niveau transistor, avec une particularité au niveau de l’amplificateur utilisé. En effet, afin de gagner en surface qui est l’un des points importants dans les systèmes d’imagerie, un inverseur est utilisé. Une étude de cette inverseur, afin de choisir le plus adapté à notre besoin est effectuée avec des simulations montecarlo et aux « corners ». Pour finir, un routage global de l’ADC est réalisé afin de pouvoir comparer ces performances à l’état de l’art
This thesis deals with the conception and design of high resolution analog-to-digital converters (ADC) for CMOS image sensor (CIS) applications with the 0.18 μm technology. A CIS is a system able to convert light to digital data to be processed. This system includes a pixel array, ADCs, registers and a set of clocks to acquire and transport the data. At the beginning, a single ADC was used for the whole matrix of pixels, converting the pixel value in a sequential way. With the growing size of the pixel array and the increasing frame rate, the ADC became one of the bottleneck of these system. A solution was found to use column ADC, located at the bottom of each column in order to parallelize the conversions. These column ADC are going to be my point of interest in this thesis.First of all, a state of the art of the ADC for CIS is realized in order to determine the best architecture to use. A two-step incremental sigma-delta is chosen and investigated. A theoretical analysis is done, especially on the modulator in order to determine the order of this modulator and the oversampling ratio of the conversion. Then a schematic is realized, with a special feature on the amplifier. Indeed, an inverter is used as amplifier in order to reduce the size of the ADC. A montecarlo and corner studies are then realized on the ADC, a layout is proposed and the ADC is compared to the state of the art of the ADC for CIS
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Heinzig, André. "Entwicklung und Herstellung rekonfigurierbarer Nanodraht-Transistoren und Schaltungen." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-202082.

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Die enorme Steigerung der Leistungsfähigkeit integrierter Schaltkreise wird seit über 50 Jahren im Wesentlichen durch eine Verkleinerung der Bauelementdimensionen erzielt. Aufgrund des Erreichens physikalischer Grenzen kann dieser Trend, unabhängig von der Lösung technologischer Probleme, langfristig nicht fortgesetzt werden. Diese Arbeit beschäftigt sich mit der Entwicklung und Herstellung neuartiger Transistoren und Schaltungen, welche im Vergleich zu konventionellen Bauelementen funktionserweitert sind, wodurch ein zur Skalierung alternativer Ansatz vorgestellt wird. Ausgehend von gewachsenen und nominell undotierten Silizium-Nanodrähten wird die Herstellung von Schottky-Barrieren-Feldeffekttransistoren (SBFETs) mit Hilfe etablierter und selbst entwickelter Methoden beschrieben und die Ladungsträgerinjektion unter dem Einfluss elektrischer Felder an den dabei erzeugten abrupten Metall–Halbleiter-Grenzflächen analysiert. Zur Optimierung der Injektionsvorgänge dienen strukturelle Modifikationen, welche zu erhöhten ambipolaren Strömen und einer vernachlässigbaren Hysterese der SBFETs führen. Mit dem rekonfigurierbaren Feldeffekttransistor (RFET) konnte ein Bauelement erzeugt werden, bei dem sich Elektronen- und Löcherinjektion unabhängig und bis zu neun Größenordnungen modulieren lassen. Getrennte Topgate-Elektroden über den Schottkybarrieren ermöglichen dabei die reversible Konfiguration von unipolarer Elektronenleitung (n-Typ) zu Löcherleitung (p-Typ) durch eine Programmierspannung, wodurch die Funktionen konventioneller FETs in einem universellen Bauelement vereint werden. Messungen und 3D-FEM-Simulationen geben einen detaillierten Einblick in den elektrischen Transport und dienen der anschaulichen Beschreibung der Funktionsweise. Systematische Untersuchungen zu Änderungen im Transistoraufbau, den Abmessungen und der Materialzusammensetzung verdeutlichen, dass zusätzliche Strukturverkleinerungen sowie die Verwendung von Halbleitern mit niedrigem Bandabstand die elektrische Charakteristik dieser Transistoren weiter verbessern. Im Hinblick auf die Realisierung neuartiger Schaltungen wird ein Konzept beschrieben, die funktionserweiterten Transistoren in einer energieeffizienten Komplementärtechnologie (CMOS) nutzbar zu machen. Die dafür notwendigen gleichen Elektronen- und Löcherstromdichten konnten durch einen modifizierten Ladungsträgertunnelprozess infolge mechanischer Verspannungen an den Schottkyübergängen erzielt und weltweit erstmalig an einem Transistor gezeigt werden. Der aus einem <110>-Nanodraht mit 12 nm Si-Kerndurchmesser erzeugte elektrisch symmetrische RFET weist dabei eine bisher einzigartige Kennliniensymmetrie auf.Die technische Umsetzung des Schaltungskonzepts erfolgt durch die Integration zweier RFETs innerhalb eines Nanodrahts zum dotierstofffreien CMOS-Inverter, der flexibel programmiert werden kann. Die rekonfigurierbare NAND/NOR- Schaltung verdeutlicht, dass durch die RFET-Technologie die Bauelementanzahl reduziert und die Funktionalität des Systems im Vergleich zu herkömmlichen Schaltungen erhöht werden kann. Ferner werden weitere Schaltungsbeispiele sowie die technologischen Herausforderungen einer industriellen Umsetzung des Konzeptes diskutiert. Mit der funktionserweiterten, dotierstofffreien RFET-Technologie wird ein neuartiger Ansatz beschrieben, den technischen Fortschritt der Elektronik nach dem erwarteten Ende der klassischen Skalierung zu ermöglichen
The enormous increase in performance of integrated circuits has been driven for more than 50 years, mainly by reducing the device dimensions. This trend cannot continue in the long term due to physical limits being reached. The scope of this thesis is the development and fabrication of novel kinds of transistors and circuits that provide higher functionality compared to the classical devices, thus introducing an alternative approach to scaling. The fabrication of Schottky barrier field effect transistors (SBFETs) based on nominally undoped grown silicon nanowires using established and developed techniques is described. Further the charge carrier injection in the fabricated metal to semiconductor interfaces is analyzed under the influence of electrical fields. Structural modifications are used to optimize the charge injection resulting in increased ambipolar currents and negligible hysteresis of the SBFETs. Moreover, a device has been developed called the reconfigurable field-effect transistor (RFET), in which the electron and hole injection can be independently controlled by up to nine orders of magnitude. This device can be reversibly configured from unipolar electron conducting (ntype) to hole conducting (p-type) by the application of a program voltage to the two individual top gate electrodes at the Schottky junctions. So the RFET merges the functionality of classical FETs into one universal device. Measurements and 3D finite element method simulations are used to analyze the electrical transport and to describe the operation principle. Systematic investigations of changes in the device structure, dimensions and material composition show enhanced characteristics in scaled and low bandgap semiconductor RFET devices. For the realization of novel circuits, a concept is described to use the enhanced functionality of the transistors in order to realize energy efficient complementary circuits (CMOS). The required equal electron and hole current densities are achieved by the modification of charge carrier tunneling due to mechanical stress and are shown for the first time ever on a transistor. An electrically symmetric RFET based on a compressive strained nanowire in <110> crystal direction and 12 nm silicon core diameter exhibits unique electrical symmetry. The circuit concept is demonstrated by the integration of two RFETs on a single nanowire, thus realizing a dopant free CMOS inverter which can be programmed flexibly. The reconfigurable NAND/NOR shows that the RFET technology can lead to a reduction of the transistor count and can increase the system functionality. Additionally, further circuit examples and the challenges of an industrial implementation of the concept are discussed.The enhanced functionality and dopant free RFET technology describes a novel approach to maintain the technological progress in electronics after the expected end of classical device scaling
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Mioni, Daniel Pasti. "Amplificador de audio classe D baseado em modulação sigma-delta destinado a aparelhos auditivos." [s.n.], 2007. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259311.

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Orientadores: Jose Antenor Pomilio, Saulo Finco
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-09T03:34:05Z (GMT). No. of bitstreams: 1 Mioni_DanielPasti_M.pdf: 1903299 bytes, checksum: 7343c6fb1cd22aa8df8654d5b9b51852 (MD5) Previous issue date: 2007
Resumo: Desenvolvemos um amplificador de áudio classe D baseado em moduladores S-?, destinado a aparelhos auditivos, a maioria dos quais utiliza baterias de 1,1V e necessita ter baixo consumo de corrente. Neste trabalho os amplificadores e comparadores foram construídos com inversores CMOS, pois um destes inversores, alimentado com uma tensão de 1,1V, pode consumir uma corrente CC tão baixa quanto 400nA, dependendo das dimensões, e proporcionar alto ganho de tensão quando polarizado em sua região linear de operação. Por estes motivos, podem substituir com vantagem amplificadores operacionais e comparadores em algumas aplicações. Um protótipo deste circuito foi implementado com tecnologia CMOS 0,35µm e alcançou um rendimento de 90%
Abstract: This thesis presents the design of a firstorder S-? audioband power amplifier optimized for hearing aid (HA) amplification. The majority of HAs use a 1.1V battery and require very low current consumption to improve battery life. This work made use of amplifiers and comparators based on CMOS inverters because such an inverter, with a 1.1V battery, can operate on a current as low as 400nA, depending on its dimensions, and provide high voltage gain when biased in their linear region. For these reasons, they can substitute with advantage operational amplifiers in some applications. A prototype of this circuit was implemented in a monolithic chip using 0.35µm CMOS technology and achieved 90% of power efficiency
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
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Pop, Eric 1975. "CMOS inverse doping profile extraction and substrate current modeling." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80565.

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Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
Includes bibliographical references (p. 95-101).
by Eric Pop.
S.B.and M.Eng.
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Appaswamy, Aravind. "Operation of inverse mode SiGe HBTs and ultra-scaled CMOS devices in extreme environments." Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/33970.

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The objective of this work is to investigate the performance of SiGe HBTs and scaled CMOS devices in extreme environments. In this work, the inverse mode operation of SiGe HBTs is investigated as a potential solution to the vulnerability of SiGe HBTs to single event effects. The performance limitations of SiGe HBTs operating in inverse mode are investigated through an examination of the effects of scaling on inverse mode performance and optimization schemes for inverse mode performance enhancements are discussed and demonstrated. In addition the performance of scaled MOSFETs, that constitute the digital backbone of any BiCMOS technology, is investigated under radiation exposure and cryogenic temperatures. Extreme environments and their effects on semiconductor devices are introduced in Chapter 1. The immunity of 90nm MOSFETs to total ionizing dose damage under proton radiation is demonstrated. Inverse mode operation of SiGe HBTs is introduced in Chapter 2 as a potential radiation hard solution by design. The effect of scaling on inverse mode performance of SiGe HBTs is investigated and the performance limitations in inverse mode are identified. Optimization schemes for improving inverse mode performance of SiGe HBTs are discussed in Chapter 3. Inverse mode performance enhancement is demonstrated experimentally in optimized device structures manufactured in a commercial third generation SiGe HBT BiCMOS platform. Further, a cascode device structure, the combines the radiation immunity of an inverse mode structure with the performance of a forward mode common emitter device is XIV discussed. Finally, idealized doping profiles for inverse mode performance enhancement is discussed through TCAD simulations. The cryogenic performance of inverse mode SiGe HBTs are discussed in Chapter 4. A novel base current behavior at cryogenic temperature is identified and its effect on the inverse mode performance is discussed. Matching performance of a 90nm bulk CMOS technology at cryogenic temperatures is investigated experimentally and through TCAD simulations in Chapter 5. The effect of various process parameters on the temperature sensitivity of threshold voltage mismatch is discussed. The potential increase of mismatch in subthreshold MOSFETs operating in cryogenic temperatures due to hot carrier effects is also investigated.
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Books on the topic "CMOS inverter"

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Machowski, Witold. Niskonapięciowe układy analogowe bazujące na inwerterach CMOS w scalonych systemach VLSI: Low voltage analog circuits based on CMOS inverters in VLSI systems. Kraków: Wydawnictwa AGH, 2012.

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Book chapters on the topic "CMOS inverter"

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Uyemura, John P. "The CMOS Inverter." In Circuit Design for CMOS VLSI, 79–113. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_3.

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Giebel, Thomas. "Der Inverter." In Grundlagen der CMOS-Technologie, 151–79. Wiesbaden: Vieweg+Teubner Verlag, 2002. http://dx.doi.org/10.1007/978-3-663-07914-9_6.

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Mirmotahari, Omid, and Yngvar Berg. "Ultra Low Voltage High Speed Differential CMOS Inverter." In Lecture Notes in Computer Science, 328–37. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-95948-9_33.

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Custódio, José Rui, Michael Figueiredo, Edinei Santin, and João Goes. "A CMOS Inverter-Based Self-biased Fully Differential Amplifier." In IFIP Advances in Information and Communication Technology, 541–48. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11628-5_60.

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Wu, Yung-Chun, and Yi-Ruei Jhan. "Inverter and SRAM of FinFET with L g = 15 nm Simulation." In 3D TCAD Simulation for CMOS Nanoeletronic Devices, 185–210. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-3066-6_4.

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Tigelaar, Howard. "CMOS Inverter Manufacturing Flow: Part 1 Wafer Start Through Transistors." In How Transistor Area Shrank by 1 Million Fold, 73–102. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40021-7_6.

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Tigelaar, Howard. "CMOS Inverter Manufacturing Flow: Part 2 Transistors Through Single-Level Metal." In How Transistor Area Shrank by 1 Million Fold, 103–21. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40021-7_7.

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Tigelaar, Howard. "CMOS Inverter Manufacturing Flow: Part 3 Additional Levels of Metal Through PO." In How Transistor Area Shrank by 1 Million Fold, 123–36. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40021-7_8.

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Adler, Victor, and Eby G. Friedman. "Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load." In Analog Design Issues in Digital VLSI Circuits and Systems, 29–39. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6101-9_3.

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Bindu Katikala, Hima, and G. Ramana Murthy. "A Design of Current Starved Inverter-Based Non-overlap Clock Generator for CMOS Image Sensor." In Algorithms for Intelligent Systems, 115–23. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-2248-9_12.

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Conference papers on the topic "CMOS inverter"

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Das, Saptarshi, and Andreas Roelofs. "Electrostatically doped WSe2 CMOS inverter." In 2014 72nd Annual Device Research Conference (DRC). IEEE, 2014. http://dx.doi.org/10.1109/drc.2014.6872359.

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Valavala, Likhit, Kalpit Munot, and Karri Babu Ravi Teja. "Design of CMOS Inverter and Chain of Inverters Using Neural Networks." In 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS). IEEE, 2018. http://dx.doi.org/10.1109/ises.2018.00065.

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Ho-Cheng Lin, Dong-Shiuh Wu, Che-Min Kung, Yuh-Shyan Hwang, and Jiann-Jong Chen. "New CMOS inverter-based voltage multipliers." In 2010 IEEE International Conference of Electron Devices and Solid- State Circuits (EDSSC). IEEE, 2010. http://dx.doi.org/10.1109/edssc.2010.5713740.

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Abdul Hadi, Dayanasari, Norhayati Soin, and S. F. Wan Muhamad Hatta. "Reliability study of 90nm CMOS inverter." In 2010 International Conference on Enabling Science and Nanotechnology (ESciNano). IEEE, 2010. http://dx.doi.org/10.1109/escinano.2010.5700968.

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Xu, Peng, and Pamela Abshire. "Stochastic Behavior of a CMOS Inverter." In 2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS '07). IEEE, 2007. http://dx.doi.org/10.1109/icecs.2007.4510939.

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Kiumarsi, H., Y. Mizuochi, H. Ito, N. Ishihara, and K. Masu. "A Stacked Inverter-based CMOS Power Amplifier in 65nm CMOS Process." In 2011 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2011. http://dx.doi.org/10.7567/ssdm.2011.d-1-4.

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Berg, Yngvar, Omid Mirmotahari, Johannes Goplen Lomsdalen, and Snorre Aunet. "High Speed Ultra Low Voltage CMOS inverter." In 2008 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2008. http://dx.doi.org/10.1109/isvlsi.2008.23.

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Chaourani, P., I. Messaris, N. Fasarakis, M. Ntogramatzi, S. Goudos, and S. Nikolaidis. "An analytical model for the CMOS inverter." In 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE, 2014. http://dx.doi.org/10.1109/patmos.2014.6951894.

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Sharroush, Sherif M. "Novel CMOS-Inverter Based VGA and VCRO." In 2018 International Japan-Africa Conference on Electronics, Communications and Computations (JAC-ECC). IEEE, 2018. http://dx.doi.org/10.1109/jec-ecc.2018.8679565.

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Barthelemy, Herve, Stephane Meillere, Jean Gaubert, and Edith Kussener. "Transconductance CMOS inverter based AC coupling amplifier." In 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS). IEEE, 2014. http://dx.doi.org/10.1109/newcas.2014.6933972.

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