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Journal articles on the topic 'CMOS inverter'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Surwadkar, Prof Tushar. "Comparison of CNTFET Inverter with CMOS Inverter." International Journal for Research in Applied Science and Engineering Technology 8, no. 6 (June 30, 2020): 2565–72. http://dx.doi.org/10.22214/ijraset.2020.6413.

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2

Machowski, Witold, Stanisław Kuta, Jacek Jasielski, and Wojciech Kołodziejski. "Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS Inverters." International Journal of Electronics and Telecommunications 56, no. 4 (November 1, 2010): 381–86. http://dx.doi.org/10.2478/v10177-010-0050-z.

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Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS InvertersThe paper presents quarter-square analog four-quadrant multipliers, based on proprietary architecture using four CMOS inverters. The most important upgrade on already published own circuit implementation is the use of the same inverter "core" of the circuit with completely redesigned auxiliary and steering blocks. Two variants of new driving peripherals are considered: one with differential pair, the second with CMOS inverters. The proposed circuit solutions are suitable for RF applications in communication systems due to simple architecture comprising building blocks with RF CMOS transistors having sufficiently large biasing currents. Postlayout simulation results done on the basis of 180nm CMOS UMC Foundry Design Kit are also presented.

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3

Kuroki, Shinichiro, Tatsuya Kurose, Hirofumi Nagatsuma, Seiji Ishikawa, Tomonori Maeda, Hiroshi Sezaki, Takamaro Kikkawa, et al. "4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics." Materials Science Forum 897 (May 2017): 669–72. http://dx.doi.org/10.4028/www.scientific.net/msf.897.669.

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For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.

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4

Zingg, R. P., B. Hofflinger, and G. W. Neudeck. "High-quality stacked CMOS inverter." IEEE Electron Device Letters 11, no. 1 (January 1990): 9–11. http://dx.doi.org/10.1109/55.46914.

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5

Bae, Woorham. "CMOS Inverter as Analog Circuit: An Overview." Journal of Low Power Electronics and Applications 9, no. 3 (August 20, 2019): 26. http://dx.doi.org/10.3390/jlpea9030026.

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Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

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6

KABBANI, ADNAN. "COMPLEX CMOS GATE COLLAPSING TECHNIQUE AND ITS APPLICATION TO TRANSIENT TIME." Journal of Circuits, Systems and Computers 19, no. 05 (August 2010): 1025–40. http://dx.doi.org/10.1142/s021812661000658x.

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In this paper we present a technique to collapse a CMOS gate into an equivalent inverter. This technique considers deep submicron effects such as mobility degradation and velocity saturation as well as operation regions of both the NMOS and PMOS networks of the considered CMOS gate. In addition, the model accounts for the effect of the gate's internodal capacitances on the behavior of the equivalent Series Connected MOSFET Structure. Depending on the CMOS inverter transition time model presented in Ref. 1, the developed model has accurately predicted the transition time of different CMOS gates. Considering various loads, input switching, and transistor sizes, the model shows an average error of 6%, including the error introduced by the inverter model, as compared to BSIM3v3 using Spectre.

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7

Mun, Hye Jin, Min Su Cho, Jun Hyeok Jung, Won Douk Jang, Sang Ho Lee, Jaewon Jang, Jin-Hyuk Bae, and In Man Kang. "Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary." Journal of Nanoscience and Nanotechnology 20, no. 11 (November 1, 2020): 6616–21. http://dx.doi.org/10.1166/jnn.2020.18769.

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In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.

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8

KUMAR, K. KEERTI, and N. BHEEMA RAO. "POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 08 (June 18, 2014): 1450109. http://dx.doi.org/10.1142/s0218126614501096.

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In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.

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9

Chun-Teh Lee. "Pseudocollector effect in a CMOS inverter." IEEE Transactions on Electron Devices 34, no. 10 (October 1987): 2212–14. http://dx.doi.org/10.1109/t-ed.1987.23219.

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10

Talkhan, E. A. "New capabilities of the CMOS inverter." IEEE Journal of Solid-State Circuits 23, no. 3 (June 1988): 872–75. http://dx.doi.org/10.1109/4.333.

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11

BISDOUNIS, LABROS. "ANALYTICAL MODELING OF OVERSHOOTING EFFECT IN SUB-100 nm CMOS INVERTERS." Journal of Circuits, Systems and Computers 20, no. 07 (November 2011): 1303–21. http://dx.doi.org/10.1142/s0218126611007967.

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Modeling of CMOS inverters and consequently, CMOS gates, is a critical task for improving accuracy and speed of simulation in modern sub-100 nm digital circuits. One of the key factors that determine the operation of a CMOS structure is the influence of the input-to-output coupling capacitance, also called overshooting effect. In this paper, an analytical model for this effect is presented, that computes the time period which is necessary to eliminate the extra output charge transferred through the input-to-output capacitance at the beginning of the switching process in a CMOS inverter. In addition, the maximum or minimum output voltage (depending on the considered edge) is analytically computed. The derived model is based on analytical expressions of the CMOS inverter output voltage waveform, which include the influences of both transistor currents and the input-to-output (gate-to-drain) coupling and load capacitances. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100 nm devices, with an extension for varying transistor widths. The resulting model also accounts for the influences of input voltage transition time, transistors' sizes, as well as device carrier velocity saturation and narrow-width effects. The results produced by the presented model for three sub-100 nm CMOS technologies, several input voltage transition times, capacitive loads and device sizes, show very good agreement with BSIM4 HSPICE simulations.

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12

Lee, Sang Ho, Min Su Cho, Jun Hyeok Jung, Won Douk Jang, Hye Jin Mun, Jaewon Jang, Jin-Hyuk Bae, and In Man Kang. "Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances." Journal of Nanoscience and Nanotechnology 20, no. 11 (November 1, 2020): 6632–37. http://dx.doi.org/10.1166/jnn.2020.18768.

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In this paper, we adopt the vertical core–shell nanowire field-effect transistors based on the Silicon-germanium (SiGe)/strained-silicon (strained-Si) layer as a method to improve the performance of the CMOS logic inverter by using technology computer aided design simulation. The lattice constant mismatch between the core region and the shell region causes the global strain of the Si region of the shell, which in turn changes the Si parameters. This phenomenon effects on the improvement the electrical characteristics in the p-type MOSFET (pMOSFET). Through this variation, the asymmetry of the electrical characteristics between n-type MOSFET (nMOSFET) and pMOSFET nanowire is considerably compensated. The inverter using the proposed core–shell structure shows the improved CMOS logic inverter characteristics. For example, the core–shell CMOS logic inverter shows performances such as NML = 0.315 V, NMH = 0.312 V, τPHL of 8.7 ps, and τPHL of 21 ps at an operating voltage of VDD = 0.7 V.

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13

Habib, H., N. G. Wright, and A. B. Horsfall. "Complementary JFET Logic for Low-Power Applications in Extreme Environments." Materials Science Forum 740-742 (January 2013): 1052–55. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.1052.

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The static and dynamic characteristics of Complementary JFET (CJFET) logic inverter are studied across a range of temperatures and supply voltages to assess potential improvements in performance of digital logic functions for operation in extreme environments. The logic inverter is truly the core of all digital designs. The design and analysis of inverter enables the design of more complex structures, such as NAND, NOR and XOR gates. These complex structures in turn form the building blocks for modules, such as adders, multipliers and microprocessors. At 500 deg C and operating at a supply voltage of 1 V, the CJFET inverter have noise margin comparable to that of room temperature silicon and silicon on insulator CMOS inverters. Furthermore, the static power dissipation by CJFET inverter at 500 deg C is 20.6 nW which is six orders of magnitude lower than that by current SiC technologies, making CJFET technology ideal for achieving complex logic functions, far greater than a few-transistors ICs, in the nearer term.

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14

Khan, Shahid. "Design of Ultra Low Power CMOS Inverter." IJIREEICE 5, no. 3 (March 15, 2017): 55–57. http://dx.doi.org/10.17148/ijireeice.2017.5312.

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15

Vlassis, S. "0.5 V CMOS inverter-based tunable transconductor." Analog Integrated Circuits and Signal Processing 72, no. 1 (May 10, 2012): 289–92. http://dx.doi.org/10.1007/s10470-012-9865-0.

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16

Daga, J. M., S. Turgis, and D. Auvergne. "Inverter delay modelling for submicrometre CMOS process." Electronics Letters 32, no. 22 (1996): 2070. http://dx.doi.org/10.1049/el:19961394.

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17

Sharroush, Sherif M. "Analysis of the subthreshold CMOS logic inverter." Ain Shams Engineering Journal 9, no. 4 (December 2018): 1001–17. http://dx.doi.org/10.1016/j.asej.2016.05.005.

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18

Rahayu, Sofitri, and Jaja Kustija. "APLIKASI TRANSISTOR DARLINGTON PADA RANGKAIAN INVERTER PORTABLE." Energi & Kelistrikan 10, no. 2 (January 28, 2019): 119–28. http://dx.doi.org/10.33322/energi.v10i2.229.

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Energi listrik digunakan dalam segala lapangan kehidupan manusia untuk membantu meringankan pekerjaannya. Kebutuhan akan sumber energi listrik AC (arus bolak balik) tidak selamanya tersedia di setiap tempat misalnya ketika kita berada jauh dari supplay energi listrik dari PLN. Untuk mendapatkan sumber energi listrik arus bolak balik (AC) ketika berada jauh dari sumbernya maka di dapat dengan cara mengubah sumber DC menjadi AC menggunakan inverter. Inverter yang dirancang portable menggunakan sumber DC 12 volt dan komponen inverter berbasis IC 555 sebagai pembangkit pulsa dan CMOS 4013 sebagai rangkaian D flip-flop. Karena tegangan yang keluar dari CMOS 4013 ini kecil maka dihubungkan dengan transistor MJ11016 sebagai penguat. Kemudian tegangan yang dihasilkan dinaikkan dengan menggunakan trafo Step Up. Sistem ini dirancang berkemampuan daya sebesar 60 watt.

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19

Geißler, R., and H. J. Pfleiderer. "Analytische Modellierung des Zeitverhaltens und der Verlustleistung von CMOS-Gattern." Advances in Radio Science 1 (May 5, 2003): 273–78. http://dx.doi.org/10.5194/ars-1-273-2003.

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Abstract. In modernen CMOS-Technologien werden die Verzögerungszeit, die Ausgangsflankensteilheit und der Querstrom eines Gatters sowohl durch die Lastkapazität als auch durch die Steilheit des Eingangssignals beeinflusst. Die heute verwendeten Technologiebibliotheken beinhalten Tabellenmodelle mit 25 oder mehr Stützpunkten dieser Abhängigkeiten, woraus durch Interpolation die benötigten Zwischenwerte berechnet werden. Bisherige Versuche, analytische Modelle abzuleiten beruhten darauf, den Querstrom zu vernachlässigen oder Transistorströme als stückweise linear anzunähern. Der hier gezeigte Ansatz beruht auf einer näherungsweisen Lösung der Differentialgleichung, die aus den beiden Transistorströmen und einer Lastkapazität besteht und damit das Schaltverhalten eines Inverters beschreibt. Mit wenigen Technologieparametern können daraus für einen beliebig dimensionierten Inverter die für eine Timing- und Verlustleistungsanalyse notwendigen Größen berechnet werden. Das Modell erreicht bei einem Vergleich zu Referenzwerten aus SPICE Simulationen eine Genauigkeit von typischerweise 5%.In modern CMOS-technologies the gate delay, output transition time and the short-circuit current depend on the capacitive load as well as on the input transition time. Today’s technology libraries use table models with 25 or more samples for these dependencies. Intermediate values have to be calculated through interpolation. Attempts to derive analytical models are based on neglecting the short-circuit current or approximating it by piecewise linear functions. The approach shown in this paper provides an approximate solution for the differential equation describing the dynamic behavor of an inverter circuit. It includes the influence of both transistor currents and a single load capacitance. The required values for timing and power analysis can be calculated with a small set of technology parameters for an arbitrary designed inverter. Compared to reference values extracted from SPICE simulations, the model achieves a typical precision of 5%.

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20

Guo, Benqing, Jing Gong, Yao Wang, and Jingwei Wu. "A 0.2–3.3 GHz 2.4 dB NF 45 dB gain CMOS current-mode receiver front-end." Modern Physics Letters B 34, no. 22 (June 6, 2020): 2050226. http://dx.doi.org/10.1142/s0217984920502267.

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A CMOS fully differential current-mode front-end for SAW-less receivers is proposed. The noise-canceling LNTA has a main path of the common-gate (CG) stage and an auxiliary path of the inverter stage. A current mirror is used to combine the signals from the main and auxiliary paths in current mode. The stacked nMOS/pMOS configurations improve their power efficiency. The traditional stacked tri-state inverter as D-latch replaced by the discrete inverter and transmission gate enables a reduced supply voltage of divider core. LO generator based on the improved divider provides quarter LO signals to drive the proposed LNTA-shared receiver front-end. Simulation results in 180 nm CMOS indicate that the integrated receiver front-end provides an NF of 2.4 dB, and a maximum gain of 45 dB from 0.2 to 3.3 GHz. The in-band (IB) and out-of-band (OB) IIP3 of 2.5 dBm and 4 dBm, are obtained, respectively. With CMOS scaling down continuously, CMOS devices are providing increased transit frequency and reduced intrinsic parasitics which are important for radio frequency (RF) and millimeter-wave applications. As a promising solution, CMOS RF delivers comparable performance to silicon bipolar and GaAs devices but at a much lower cost and higher integration level. Supply voltage reduction with CMOS scaling down also poses a stringent linearity requirement. Avoiding the conventional trade-off between the supply voltage and linearity headroom, the proposed receiver front-end based on the current mode principle is with weak linearity dependency on the supply voltage and provides excellent anti-blocker interference capability.

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21

Tiwari, Ayush. "Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 14, 2021): 962–66. http://dx.doi.org/10.22214/ijraset.2021.35065.

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Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

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22

Srivastava, A., and K. Venkatapathy. "Design and Implementation of a Low Power Ternary Full Adder." VLSI Design 4, no. 1 (January 1, 1996): 75–81. http://dx.doi.org/10.1155/1996/94696.

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In this work, the design and implementation of a low power ternary full adder are presented in CMOS technology. In a ternary full adder design, the basic building blocks, the positive ternary inverter (PTI) and negative ternary inverter (NTI) are developed using a CMOS inverter and pass transistors. In designs of PTI and NTI, W/L ratios of transistors have been varied for their optimum performance. The ternary full adder and its building blocks have been simulated with SPICE 2G.6 using the MOSIS model parameters. The rise and fall times of PTI show an improvement by a factor of 14 and 4, respectively, and that of the NTI by a factor of nearly 4 and 17, respectively over that of earlier designs implemented in depletion-enhancement CMOS (DECMOS) technology. The noise margins improve by a factor of nearly 2 in PTI and NTI, respectively.The ternary full adder has been fabricated in MOSIS two micron n-well CMOS technology. The full adder and its building blocks, NTI and PTI have been tested experimentally for static and dynamic performance, compared with the SPICE simulated behavior, and close agreement is observed.The ternary-valued logic circuits designed in the present work which do not use depletion mode MOSFETS perform better than that implemented earlier in DECMOS technology. The present design is fully compatible with the current CMOS technology, uses fewer components and dissipates power in the microwatt range.

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23

Kulakova, Anastasia A., and Yevgeniy B. Lukyanenko. "Energy-Efficient CMOS-Triggers with Inverter Storage Cell." Proceedings of Universities. Electronics 24, no. 3 (June 2019): 230–38. http://dx.doi.org/10.24151/1561-5405-2019-24-3-230-238.

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24

GUPTA, B. K., and MANISH MISHRA. "Design of CMOS Inverter using SNWFET on Nanohub." Journal of Ultra Scientist of Physical Sciences Section A 30, no. 03 (March 2, 2018): 195–200. http://dx.doi.org/10.22147/jusps-a/300304.

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25

Akturk, Akin, Neil Goldsman, and George Metze. "Increased CMOS inverter switching speed with asymmetrical doping." Solid-State Electronics 47, no. 2 (February 2003): 185–92. http://dx.doi.org/10.1016/s0038-1101(02)00193-4.

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26

ABUELMA'ATTI, MUHAMMAD TAHER. "Improved analysis of distortion in CMOS inverter circuits." International Journal of Electronics 60, no. 4 (April 1986): 505–16. http://dx.doi.org/10.1080/00207218608920809.

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27

Dey, Anil W., Johannes Svensson, B. Mattias Borg, Martin Ek, and Lars-Erik Wernersson. "Single InAs/GaSb Nanowire Low-Power CMOS Inverter." Nano Letters 12, no. 11 (October 8, 2012): 5593–97. http://dx.doi.org/10.1021/nl302658y.

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28

De, Bishnu Prasad, R. Kar, D. Mandal, and S. P. Ghoshal. "Optimal CMOS inverter design using differential evolution algorithm." Journal of Electrical Systems and Information Technology 2, no. 2 (September 2015): 219–41. http://dx.doi.org/10.1016/j.jesit.2015.03.014.

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29

Jurgo, Marijan, and Romualdas Navickas. "Increasing a Resolution of Time to Digital Converter." Mokslas - Lietuvos ateitis 9, no. 3 (July 4, 2017): 318–23. http://dx.doi.org/10.3846/mla.2017.1041.

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Time to digital converter (TDC) is one of the main blocks of all-digital frequency synthesizer (FS), where it is used as phase detector. The output of TDC is digital, therefore it introduces quantization noise to the output of FS. The resolution of TDC has to be increased, to improve phase noise level at the output of FS. It can be achieved by improving CMOS technology or structure of the TDC. The simplest TDC is based on inverter delay line. Its resolution is inversely proportional to the time interval, which can be measured with such TDC, i.e. delay time of the inverter. Decreasing of this delay is essence of technological increasing of TDC’s resolution. In this work the dependency of inverter delay on technological parameters is shown and its value is calculated in 65 nm CMOS technology. Calculations show, that in this technology delay time of the inverter can vary from 7 ps to 54 ps. If the design is restricted to the usage of specific CMOS technology, in which inverter’s delay does not ensure needed noise level at the output of FS, structure of the TDC needs to be improved. The aim of this improvement is to measure time interval smaller than inverter’s delay. Some of the TDC structures, which can measure sub-inverter delay time, are reviewed in this work: TDC – Vernier delay line, TDC – 2D Vernier plane, stochastic, ring and multistage TDCs.

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30

Upadhyay, Shipra, R. K. Nagaria, and R. A. Mishra. "Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic." VLSI Design 2013 (November 7, 2013): 1–9. http://dx.doi.org/10.1155/2013/726324.

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Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL) circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL) family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL)) is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In our proposed (IQSERL) inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.

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31

Kim, Dong-Myeong, Dongmin Kim, Hang-Geun Jeong, and Donggu Im. "A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications." Electronics 9, no. 4 (March 27, 2020): 562. http://dx.doi.org/10.3390/electronics9040562.

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A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (Vth) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load Ropt, resulting in maximum output power with peak power added efficiency (PAE). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × VDD, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show Ropt of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (Psat) of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance condition, a Psat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance condition, and a Psat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration.

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32

Van, Ngoc Huynh, Jae-Hyun Lee, Dongmok Whang, and Dae Joon Kang. "Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors." Nanoscale 8, no. 23 (2016): 12022–28. http://dx.doi.org/10.1039/c6nr01040g.

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33

Chen, Cheng-Po, Reza Ghandi, Liang Yin, Xingguang Zhu, Liangchun Yu, Steve Arthur, and Peter Sandvik. "500°C Silicon Carbide MOSFET-Based Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000072–75. http://dx.doi.org/10.4071/hitec-tp14.

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In this work silicon carbide MOSFET based integrated circuits such as operational amplifier. 27-stage ring oscillator and CMOS-based inverter have been designed, fabricated and successfully tested at high temperatures. Silicon carbide MOSFETs remained fully operational from room temperature to 500°C with stable I-V characteristics. Also 27-stage ring oscillator, operational amplifier and CMOS inverter tested and shown to be functional up to 500°C, with relatively small performance change between 300°C and 500°C. High temperature reliability evaluation of these circuits demonstrate stable operation and both the ring oscillator and OpAmp survived more than 100 hours at 500°C.

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34

Sahani, Jagdeep Kaur, Anil Singh, and Alpana Agarwal. "A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology." Journal of Circuits, Systems and Computers 29, no. 08 (October 14, 2019): 2050130. http://dx.doi.org/10.1142/s0218126620501303.

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A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

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35

Choi, Moon-Ho, and Yeong-Seuk Kim. "A Gm-C Filter using CMFF CMOS Inverter-type OTA." Journal of the Korean Institute of Electrical and Electronic Material Engineers 23, no. 4 (April 1, 2010): 267–72. http://dx.doi.org/10.4313/jkem.2010.23.4.267.

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Bastan, Yasin, and Parviz Amiri. "A Digital-Based Ultra-Low-Voltage Pseudo-Differential CMOS Schmitt Trigger." Journal of Circuits, Systems and Computers 29, no. 04 (June 26, 2019): 2020002. http://dx.doi.org/10.1142/s0218126620200029.

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A digital-based Pseudo-differential Schmitt trigger is proposed in this paper which is suitable for ultra-low voltages and pure digital integrated circuit technologies. The proposed Schmitt trigger is implemented according to the design procedure of an analog Schmitt trigger and only using digital CMOS inverters. It is composed of a differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair positive feedback which has simultaneously two outputs of noninverting and inverting. The proposed circuit is the only digital Schmitt trigger which operates in differential mode and its hysteresis center can be changed by the input voltage. Implementing the circuit in digital-based allows the proposed Schmitt trigger to operate in 0.4[Formula: see text]V ultra-low-voltage. Principle operation of the proposed circuit is discussed theoretically and using formulas and its performance is verified by simulation in TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. The proposed circuit occupies only [Formula: see text][Formula: see text][Formula: see text]m2 chip area due to the very low number of transistors. The hysteresis width of the proposed Schmitt trigger is 205[Formula: see text]mV and consumes only 6.64[Formula: see text]nW power.

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Raikwal, Pushpa, Dr Vaibhav Neema, and Dr Sumant Katiyal. "Low Power High Speed with Improved Noise Margin for Domino CMOS Inverter." Indian Journal of Applied Research 1, no. 7 (October 1, 2011): 86–88. http://dx.doi.org/10.15373/2249555x/apr2012/26.

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Marranghello, Felipe S., André I. Reis, and Renato P. Ribas. "Improving Analytical Delay Modelingfor CMOS Inverters." Journal of Integrated Circuits and Systems 10, no. 2 (December 28, 2015): 123–34. http://dx.doi.org/10.29292/jics.v10i2.414.

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Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

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Lementuev, V. A., and M. S. Sonin. "Linearized wave model of the CMOS-inverter ring oscillator." Russian Microelectronics 42, no. 1 (January 2013): 33–39. http://dx.doi.org/10.1134/s1063739712060042.

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Horishita, Yusuke, and Yoshinori Matsumoto. "Measurement of Low-Voltage CMOS Inverter-Based Differential Amplifier." IEEJ Transactions on Sensors and Micromachines 132, no. 9 (2012): 316–17. http://dx.doi.org/10.1541/ieejsmas.132.316.

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Sachid, Angada B., Sujay B. Desai, Ali Javey, and Chenming Hu. "High-gain monolithic 3D CMOS inverter using layered semiconductors." Applied Physics Letters 111, no. 22 (November 27, 2017): 222101. http://dx.doi.org/10.1063/1.5004669.

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42

Tangel, Ali, and Kyusun Choi. "“The CMOS Inverter” as a Comparator in ADC Designs." Analog Integrated Circuits and Signal Processing 39, no. 2 (May 2004): 147–55. http://dx.doi.org/10.1023/b:alog.0000024062.35941.23.

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SURAKAMPONTORN, WANLOP, KIATTISAK KUMWACHARA, VANCHAI RIEWRUJA, and CHARRAY SURAWATPUNYA. "CMOS-based integrable electronically tunable floating general impedance inverter." International Journal of Electronics 82, no. 1 (January 1997): 33–44. http://dx.doi.org/10.1080/002072197136255.

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SHEN, JIZHONG, and P. DOUGLAS TOUGAW. "Design of symmetric ternary current-mode CMOS Schmitt inverter." International Journal of Electronics 85, no. 4 (October 1998): 477–82. http://dx.doi.org/10.1080/002072198134021.

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Roche, F. M., and L. Salager. "CMOS inverter design-hardened to the total dose effect." IEEE Transactions on Nuclear Science 43, no. 6 (1996): 3097–102. http://dx.doi.org/10.1109/23.556910.

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46

Wagaj, S. C., and S. C. Patil. "Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor." International Journal of Engineering and Advanced Technology 10, no. 6 (August 30, 2021): 1–10. http://dx.doi.org/10.35940/ijeat.e2576.0810621.

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In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

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47

Puhan, Janez, Dušan Raič, Tadej Tuma, and Árpád Bűrmen. "Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/349131.

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A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

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Wu, Xiao Bing, and Wan Quan Peng. "A CMOS Integrated Circuit Parameter Testing Method Using LabVIEW." Applied Mechanics and Materials 443 (October 2013): 53–57. http://dx.doi.org/10.4028/www.scientific.net/amm.443.53.

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Software controlled measurement procedure, designed for testing of inverter integrated circuit voltage parameters, is presented in this paper. Described solution, performed on circuit HCF 4007 UB, is based on data acquisition PCI card NI 6713 and control programming application developed in LabVIEW 8.0 software environment, installed on standard. PC configuration. Designed solutions of virtual instruments performs measurements, chronological recording, graphical presentation and software analysis of measurement results regarding to input and output threshold voltage levels, from inverter transfer characteristic recorded for different circuit supply voltages. LabVIEW software support in the process of recording, measurement and software processing of the integrated circuit basic parameters, provides full software automation of these procedures.

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Kim, Dong-Wook, and Tae-Yong Choi. "Delay Time Estimation Model for Large Digital CMOS Circuits." VLSI Design 11, no. 2 (January 1, 2000): 161–73. http://dx.doi.org/10.1155/2000/18189.

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Delay time estimation in simulation or design verification step during a design cycle has become more and more important as the meaning of performance prediction. This paper proposed a delay estimation model for digital CMOS circuits, which works in gate-level but the modeling process includes the characteristics of MOSFETs. This model can handle the variation according to the kind of gates, input transition time, output load(fan-out), and transistor sizes of a gate. The procedure to find the general model was that, a delay model for CMOS inverter was extracted first, then it was extended to other gate by converting it into an equivalent inverter. The resulting model was evaluated and compared with SPICE simulation, which showed that the proposed model has the accuracy of less than 5% relative error rate to the SPICE results for each case and the speed of about 70 times faster than SPICE.

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Shimo, Yuma, Takahiro Mikami, Hiroto T. Murakami, Shino Hamao, Hidenori Goto, Hideki Okamoto, Shin Gohda, et al. "Transistors fabricated using the single crystals of [8]phenacene." Journal of Materials Chemistry C 3, no. 28 (2015): 7370–78. http://dx.doi.org/10.1039/c5tc00960j.

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Field-effect transistors have been fabricated using [8]phenacene single-crystals, showing the maximumμvalue of 8.2 cm²V⁻¹s⁻¹. The CMOS inverter circuit has also been fabricated.

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