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Journal articles on the topic 'CMOS LC-based oscillator'

Author: Grafiati

Published: 3 June 2025

Last updated: 20 July 2025

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1

Patel, Dhara P., and Shruti Oza-Rahurkar. "CMOS Active Inductor/Resonator Based Voltage Controlled Oscillator." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 12, no. 6 (2019): 500–506. http://dx.doi.org/10.2174/2352096511666181105111852.

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Background: A tunable CMOS active inductor/resonator based Voltage Controlled Oscillator (VCO) has been presented. In the design of LC-VCO, LC resonator (tank) circuit has been substituted with gyrator based CMOS active inductor/resonator. The purity of VCO output signal is defined by the phase noise parameter. Methods: For good spectral purity of VCO output signal, the phase noise should be minimum. Moreover, the quality factor of LC resonator is inversely proportional to the phase noise of VCO output signal. In the presented work, a high-quality active inductor/resonator circuit has been use

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del Pino Suárez, Francisco Javier, and Sunil Lalchand Khemchandani. "A New Current-Shaping Technique Based on a Feedback Injection Mechanism to Reduce VCO Phase Noise." Sensors 21, no. 19 (2021): 6583. http://dx.doi.org/10.3390/s21196583.

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Inductor-capacitor voltage controlled oscillators (LC-VCOs) are the most common type of oscillator used in sensors systems, such as transceivers for wireless sensor networks (WSNs), VCO-based reading circuits, VCO-based radar sensors, etc. This work presents a technique to reduce the LC-VCOs phase noise using a new current-shaping method based on a feedback injection mechanism with only two additional transistors. This technique consists of keeping the negative resistance seen from LC tank constant throughout the oscillation cycle, achieving a significant phase noise reduction with a very low

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3

THANACHAYANONT, APINUNT, and MONAI KRAIRIKSH. "IMPLEMENTATION OF AN RF CMOS QUADRATURE LC VOLTAGE-CONTROLLED OSCILLATOR BASED ON THE SWITCHED TAIL TRANSISTOR TOPOLOGY." Journal of Circuits, Systems and Computers 19, no. 05 (2010): 931–37. http://dx.doi.org/10.1142/s0218126610006530.

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This paper describes the design and implementation of an RF CMOS quadrature LC voltage-controlled oscillator in a 0.35 μm technology. The proposed oscillator employs the switched tail transistor topology and differential switch capacitor tuning to achieve low phase noise operation. A modified series coupling mechanism is used for quadrature signal generation with wide output signal swing. The oscillator core circuit was designed to operate with a 2.5 V power supply voltage with a 4 mA total supply current. Measurement results showed that the prototype oscillator could achieve a nominal oscilla

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Ku, Chen-Chih, and Sen Wang. "Design and Implementation of 24-GHz and 48-GHz VCOs Using Noise Filtering Technique in 90-nm CMOS." Micromachines 16, no. 6 (2025): 682. https://doi.org/10.3390/mi16060682.

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This work proposes two voltage-controlled oscillators using noise-filtering technique. The first one is a 24-GHz voltage-controlled oscillator, and the second one is based on a push–push architecture with a λ/4 transmission line to further increase the frequency up to 48 GHz. The designs are implemented and verified in a standard 90-nm CMOS process. Typically, the current mirror transistor in the tail current has a nonlinear effect. When the transistor operates in the nonlinear region, noise will be introduced. Therefore, a set of LC filters with a resonant frequency at 2f0 are added to the de

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Jang, Sheng-Lyang, Yun-Chien Lee, and Wen-Cheng Lai. "Left-Hand Resonator VCO Using an Orthogonal Transformer." Electronics 14, no. 14 (2025): 2765. https://doi.org/10.3390/electronics14142765.

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Many novel microwave devices have been developed based on the left-handed (LH) structure. This paper studies three CMOS standing-wave oscillators (SWOs) using an LH LC network. The first SWO is a class-B VCO, and the second SWO is a class-C SWO. The SWOs are implemented with the TSMC 0.18 μm 1P6M CMOS process technology. The SWOs utilize two units of an LH LC resonator, and the LC resonator is shunted with a pair of cross-coupled transistors to compensate for the loss in the LC resonator. The first and second SWOs utilize two O-shaped inductors to form a unit cell with capacitors. The third SW

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Chiu, Liu, and Hong. "A Robust Fully-Integrated Digital-Output Inductive CMOS-MEMS Accelerometer with Improved Inductor Quality Factor." Micromachines 10, no. 11 (2019): 792. http://dx.doi.org/10.3390/mi10110792.

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This paper presents the design, fabrication, and characterization of an inductive complementary metal oxide semiconductor micro-electromechanical systems (CMOS-MEMS) accelerometer with on-chip digital output based on LC oscillators. While most MEMS accelerometers employ capacitive detection schemes, the proposed inductive detection scheme is less susceptible to the stress-induced structural curling and deformation that are commonly seen in CMOS-MEMS devices. Oscillator-based frequency readout does not need analog to digital conversion and thus can simplify the overall system design. In this pa

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Nguyen, Nhan Chi, Nghia Hoai Duong, and Anh Van Dinh. "Design and simulation of pulse generator for UWB based on LC-tank differential oscillators topology." Science and Technology Development Journal 18, no. 3 (2015): 225–41. http://dx.doi.org/10.32508/stdj.v18i3.840.

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This paper presents a detailed analysis, design and simulation of pulse generator for Ultra-Wideband (UWB) based on LC-tank differential oscillators topology. The differential oscillators with a cross-coupled NMOS pair and a tail current source are used to achieve more positive gain and generate negative resistance to the LC-tank. Besides, this oscillator is suitable for UWB high frequency and low power applications. The UWB pulse generator is composed of a simple on-off keying (OOK) modulated and LC-tank differential oscillators. The circuit of UWB pulse generator designed and simulated in 0.

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Vert, Dorian, Michel Pignol, Vincent Lebre, Emmanuel Moutaye, Florence Malou, and Jean-Baptiste Begueret. "A 3.2 GHz Injection-Locked Ring Oscillator-Based Phase-Locked-Loop for Clock Recovery." Electronics 11, no. 21 (2022): 3590. http://dx.doi.org/10.3390/electronics11213590.

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An injection-locked ring oscillator-based phase-locked-loop targeting clock recovery for space application at 3.2 GHz is presented here. Most clock recovery circuits need a very low phase noise and jitter performance and are thus based on LC-type oscillators. These excellent performances come at the expense of a very poor integration density. To alleviate this issue, this work introduces an injection-locked ring oscillator-based PLL circuit. The combination of the injection-locking process with the use of ring oscillators allows for the benefit of excellent jitter performance while presenting

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Ghorbel, Imen, Fayrouz Haddad, Wenceslas Rahajandraibe, and Mourad Loulou. "Design Methodology of Ultra-Low-Power LC-VCOs for IoT Applications." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950122. http://dx.doi.org/10.1142/s0218126619501226.

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A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[Formula: see text][Formula: see text]m CMOS process. Measurements present an ultra-low power consumption of only 262[Formula: see text][Formula: see text]W drawn from 1[Formula: see tex

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Ito, Yusaku, Kenichi Okada, and Kazuya Masu. "A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers." Journal of Electrical and Computer Engineering 2011 (2011): 1–7. http://dx.doi.org/10.1155/2011/361910.

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This paper proposes a novel wideband LC-based voltage-controlled oscillator (VCO) for multistandard transceivers. The proposed VCO has a core LC-VCO and a tuning-range extension circuit, which consists of switches, a mixer, dividers, and variable gain combiners with a spurious rejection technique. The experimental results exhibit 0.98 to 6.6 GHz continuous frequency tuning with −206 dBc/Hz of FoMT, which is fabricated by using a 0.18 μm CMOS process. The frequency tuning range (FTR) is 149%, and the chip area is 800 μm × 540 μm.

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Mao, Yuqing, Yoann Charlon, Yves Leduc, and Gilles Jacquemod. "LC Tank Oscillator Based on New Negative Resistor in FDSOI Technology." Journal of Low Power Electronics and Applications 14, no. 1 (2024): 8. http://dx.doi.org/10.3390/jlpea14010008.

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Although Moore’s Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)…, longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing

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Hasan, S. M. Rezaul. "Transition Frequencies and Negative Resistance of Inductively Terminated CMOS Buffer Cell and Application in MMW LC VCO." Active and Passive Electronic Components 2010 (2010): 1–11. http://dx.doi.org/10.1155/2010/542406.

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This paper investigates the transition frequencies () of an inductively terminated CMOS source follower buffer for negative resistance behavior at which the effective shunt resistance looking into the source of the buffer cell changes sign. Possible limiting frequencies of oscillation are determined based on resonators formed by a grounded gate inductor and a parasitic capacitance at the gate of the negative resistance buffer cell. The range of frequencies of oscillation of this negative resistance buffer cell for variations in the different circuit parameters/elements is explored. Following t

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Ishak, S. N., J. Sampe, Z. Yusoff, and M. Faseehuddin. "ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW." Jurnal Teknologi 84, no. 1 (2021): 219–30. http://dx.doi.org/10.11113/jurnalteknologi.v84.17123.

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An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, th

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Monda, Danilo, Gabriele Ciarpi, and Sergio Saponara. "Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications." Sensors 20, no. 16 (2020): 4612. http://dx.doi.org/10.3390/s20164612.

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This work presented a comparison between two Voltage Controlled Oscillators (VCOs) designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) was designed using three Current Mode Logic (CML) stages connected in a loop, while the second one was based on an LC-tank resonator. This analysis aimed to choose a VCO architecture able to be integrated into a rad-hard Phase Locked Loop. It had to meet the requirements of the SpaceFibre protocol, which supports frequencies up to 6.25 GHz, for space applications. The full custom schematic and layout designs are shown, and

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Biereigel, S., S. Kulis, E. Mendes, P. Hazell, P. Moreira, and J. Prinzie. "Radiation-tolerant all-digital clock generators for HEP applications." Journal of Instrumentation 18, no. 01 (2023): C01060. http://dx.doi.org/10.1088/1748-0221/18/01/c01060.

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Abstract The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. Both LC oscillator and ring oscillator-based all-digital PLL/CDR blocks for front-end ASICs were studied, designed, manufactured and characterized. Their design, the hardening conside

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Jurgo, Marijan, та Romualdas Navickas. "Design of Gigahertz Tuning Range 5 GHz LC Digitally Controlled Oscillator in 0.18 μm CMOS". Journal of Electrical Engineering 67, № 2 (2016): 143–48. http://dx.doi.org/10.1515/jee-2016-0020.

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Abstract In this paper design and simulation of a 4.3 - 5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18 μm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fine frequency tuning. Coarse and fine tuning switched capacitor arrays are controlled using 6-bit and 3-bit binary words. To increase available frequency values, frequency divider is used. Struc

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Chen, Jian, Wei Zhang, Qingqing Sun, and Lizheng Liu. "An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology." Electronics 10, no. 14 (2021): 1686. http://dx.doi.org/10.3390/electronics10141686.

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This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area o

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18

Gao, Wanhang, Wei Zhang, and Yanyan Liu. "A Wide Locking Range and Low Power Divide-by-2/3 LC Injection-Locked Frequency Divider." Journal of Circuits, Systems and Computers 25, no. 02 (2015): 1650013. http://dx.doi.org/10.1142/s0218126616500134.

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A direct divide-by-2/3 LC injection-locked frequency divider (ILFD) is presented in this paper. The proposed ILFD circuit is based on a CMOS LC tank oscillator coupled with an injection NMOS transistor in series with an inductor. Together with body-biased technique and current-reused topology, the locking range of the ILFD is improved and the power consumption is reduced. The circuit is implemented in a 0.18[Formula: see text][Formula: see text]m standard RF CMOS process. At the incident power of 0[Formula: see text]dBm, the measured locking range of the divide-by-2 and divide-by-3 modes are f

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Morf, T., M. Kossel, J. Weiss, et al. "Wide tuning range LC-oscillator in 65 nm SOI CMOS, based on switchable secondary inductor." Electronics Letters 43, no. 24 (2007): 1364. http://dx.doi.org/10.1049/el:20072909.

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Wang, Zixuan, Hongyang Wu, Xin Wang, et al. "A 0.5~0.7 V LC Digitally Controlled Oscillator Based on a Multi-Stage Capacitance Shrinking Technique." Electronics 8, no. 11 (2019): 1336. http://dx.doi.org/10.3390/electronics8111336.

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This paper presents a 2.4 GHz LC digitally controlled oscillator (DCO) at near-threshold supplies (0.5~0.7 V). It was a challenge to achieve a low voltage, low power, and high resolution simultaneously. DCOs with metal oxide semiconductor (MOS) varactors consume low power, but their resolution is limited. ΔΣ-DCOs can achieve a high resolution at the cost of high power consumption. A multi-stage capacitance shrinking technique was proposed in this paper to address the tradeoff mentioned above. The unit variable capacitance of the LC tank was largely reduced by the bridging capacitors and the nu

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Chen, Qinan, Qiang Shan, Zihui Wei, Xiaosong Wang, Shuilong Huang, and Yu Liu. "A Low-Power ADPLL with Calibration-Free RO-Based Injection-Locking TDC for BLE Applications." Electronics 11, no. 13 (2022): 1953. http://dx.doi.org/10.3390/electronics11131953.

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This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and the quantization step of TDC is always tracked with the RO period; hence no calibration is needed in this architecture. We adopt RO tuning to lower the injection-locking bandwidth so as to decrease the power consumption of the injection current. Moreover, the fractional part of phase error detection is turned down in the coarse tuning of ADPLL to save power. A

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Hsu, Meng-Ting, Po-Hung Chen, and Yao-Yen Lee. "Design of 5 GHz low-power CMOS LC VCO based on complementary cross-coupled topology with modified tail current-shaping technique." International Journal of Microwave and Wireless Technologies 6, no. 6 (2014): 573–80. http://dx.doi.org/10.1017/s1759078714000300.

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In this paper, a low-power CMOS LC voltage-controlled oscillator (VCO) with body-biasing and low-phase noise with Q-enhancement techniques is presented. A self-body biased circuit is introduced that can reduce power consumption. Some derivations of the Q-enhancement and how to improve the phase noise of the circuit are also discussed. This chip is implemented by the Taiwan Semiconductor Manufacture Company 0.18 µm 1P6M process. The measurement results exhibit a tuning range of 14.7% from 4.92 to 5.7 GHz at a supply voltage of 1.4 V. The power consumption of the core circuit and figure of merit

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Maiellaro, Giorgio, Giovanni Caruso, Salvatore Scaccianoce, Mauro Giacomini, and Angelo Scuderi. "40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors." Electronics 10, no. 17 (2021): 2114. http://dx.doi.org/10.3390/electronics10172114.

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This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38

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Prinzie, Jeffrey, Jorgen Christiansen, Paulo Moreira, Michiel Steyaert, and Paul Leroux. "Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity." IEEE Transactions on Nuclear Science 64, no. 1 (2017): 245–52. http://dx.doi.org/10.1109/tns.2016.2616919.

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Sun, H., Q. Sun, S. Biereigel, et al. "A radiation tolerant clock generator for the CMS endcap timing layer readout chip." Journal of Instrumentation 17, no. 03 (2022): C03038. http://dx.doi.org/10.1088/1748-0221/17/03/c03038.

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Abstract We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizi

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Khatti, Naser, and Massoud Dousti. "A Low Phase Noise LC Quadrature VCO Using Impulse Shaping Based on Gaussian Pulse Generator." Journal of Circuits, Systems and Computers 26, no. 04 (2016): 1750067. http://dx.doi.org/10.1142/s0218126617500670.

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This paper presents a new tail current-shaping technique to improve the phase noise of an LC quadrature VCO (LC-QVCO) based on Gaussian pulse generator (GPG). The GPG makes a narrow pulse from oscillator sinusoidal output and injects it back to gates of tail transistors to reduce the root-mean-square (RMS) value of impulse sensitivity function (ISF) and to improve phase noise. It will be shown that by utilizing a GPG, total phase noise improvement will be as high as 6[Formula: see text]dB. The proposed circuit was designed and simulated by ADS simulator using 0.18[Formula: see text][Formula: s

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Deng, Xiaoying, and Peiqi Tan. "An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique." Electronics 10, no. 8 (2021): 889. http://dx.doi.org/10.3390/electronics10080889.

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An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2.

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Diao, Shengxi, Fujiang Lin, and Yuanjin Zheng. "A Bandwidth and Frequency Calibration Method for OOK UWB-IR Transmitter with High Energy Efficiency." Journal of Circuits, Systems and Computers 29, no. 09 (2019): 2050137. http://dx.doi.org/10.1142/s0218126620501376.

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In this paper, an offline bandwidth and frequency calibration method for an on–off LC oscillator-based ultra-wideband impulse radio (UWB-IR) transmitter is presented. Implemented in 0.18-[Formula: see text]m CMOS, the offline calibration circuits consume very little power. This allows the transmitter to consume an ultra-low average power of 319[Formula: see text][Formula: see text]W over 3–5[Formula: see text]GHz at 2[Formula: see text]Mbps. The calibration is critical to ensure the FCC spectral mask compliance despite the process–voltage–temperature (PVT) variations. The transmitter can deliv

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Matsunaga, Maya, Atsuki Kobayashi, Kazuo Nakazato, and Kiichi Niitsu. "Design trade-off between spatial resolution and power consumption in CMOS biosensor circuit based on millimeter-wave LC oscillator array." Japanese Journal of Applied Physics 57, no. 3S2 (2018): 03EC02. http://dx.doi.org/10.7567/jjap.57.03ec02.

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Almeida, José, P. Mendonça dos Santos, João Caldinhas Vaz, Ricardo A. Marques Lameirinhas, Catarina Pinho Correia Valério Bernardo, and João Paulo N. Torres. "Step-Up DC-DC Converter Supplied by a Thermoelectric Generator for IoT Applications." Energies 17, no. 21 (2024): 5288. http://dx.doi.org/10.3390/en17215288.

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This research work aims to design and prototype a DC-DC converter to step up the low voltage of a small, low-power thermoelectric generator (TEG). The system is based on an inductive boost converter and attains a regulated output voltage of 1.2 V. The design’s optimisation was based on simulation and experimental validation and it was implemented with only ten low-cost commercial off-the-shelf (COTS) components. To reduce complexity, the low-side switch MOSFET of the boost converter is directly driven by an LC oscillator, switching at 1.25 MHz. For loads above 20 kΩ, the converter ensures volt

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Cai, Chen, Xuqiang Zheng, Yong Chen, et al. "A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS." Electronics 10, no. 16 (2021): 1873. http://dx.doi.org/10.3390/electronics10161873.

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This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE)

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HAYASHI, Kenya, Shigeki ARATA, Ge XU, et al. "An FSK Inductive-Coupling Transceiver Using 60mV 0.64fJ/bit 0.0016mm² Load-Modulated Transmitter and LC-Oscillator-Based Receiver in 65nm CMOS for Energy-Budget-Unbalanced Application." IEICE Transactions on Electronics E102.C, no. 7 (2019): 585–89. http://dx.doi.org/10.1587/transele.2018cts0002.

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Bender Machado, Marcio, and Rafael Luciano Radin. "Overview of Sub-100 mV Oscillators." Journal of Integrated Circuits and Systems 17, no. 1 (2022): 1–8. http://dx.doi.org/10.29292/jics.v17i1.577.

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This paper presents a comprehensive review of the state of the art for oscillators operating at reduced supply voltage. The analysis and implementation examples of differ-ent types of oscillators, such as LC oscillators, transformer-based oscillators, and CMOS oscillators are presented. Expres-sions for the oscillation frequency and the minimum supply voltage limit are provided. The characteristics, advantages, and constrains of different topologies are discussed, providing a reference guideline for the choice of the best topology for a given application.

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Chang, Doohwang, Jennifer N. Kitchen, Bertan Bakkaloglu, Sayfe Kiaei, and Sule Ozev. "Monitor-Based In-Field Wearout Mitigation for CMOS LC Oscillators." IEEE Transactions on Device and Materials Reliability 16, no. 2 (2016): 183–93. http://dx.doi.org/10.1109/tdmr.2016.2557624.

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Molavi, Reza, Hormoz Djahanshahi, Rod Zavari, and Shahriar Mirabbasi. "Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration." Journal of Electrical and Computer Engineering 2013 (2013): 1–8. http://dx.doi.org/10.1155/2013/364982.

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Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance. This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner. Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a contin

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Roy, Ankur Guha, Kartikeya Mayaram, and Terri S. Fiez. "Analysis and design optimization of enhanced swing CMOS LC oscillators based on a phasor based approach." Analog Integrated Circuits and Signal Processing 82, no. 3 (2015): 691–703. http://dx.doi.org/10.1007/s10470-015-0490-6.

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Perticaroli, Stefano, and Fabrizio Palma. "Design criteria based on Floquet eigenvectors for the class of LC-CMOS pulsed bias oscillators." Microelectronics Journal 44, no. 1 (2013): 58–64. http://dx.doi.org/10.1016/j.mejo.2011.07.018.

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Ryndin, Konoplev, Lysenko, Kulikova, and Popov. "Highly Sensitive Signal Processing Devices for Capacitive Transducers of Micromechanical Accelerometers." Electronics 8, no. 9 (2019): 932. http://dx.doi.org/10.3390/electronics8090932.

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In this paper, the principles of the open-loop frequency-based signal processing devices for capacitive MEMS accelerometers are used to develop three CMOS IP-core (Intellectual Property core) projects of highly sensitive signal processing devices with frequency output. Signal processing devices designed in accordance with the considered method form an output of rectangular pulses whose frequencies equal a difference of signal frequencies from two identical generators with micromechanical accelerometer capacitive transducers in their frequency control circuits. First, the analog project scheme

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Karmakar, Arijit, Valentijn De Smedt, and Paul Leroux. "TID Sensitivity Assessment of Quadrature LC-Tank VCOs Implemented in 65-nm CMOS Technology." Electronics 11, no. 9 (2022): 1399. http://dx.doi.org/10.3390/electronics11091399.

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This article presents a comprehensive assessment of the ionizing radiation induced effects on the performance of quadrature phase LC-tank based voltage-controlled-oscillators (VCOs). Two different quadrature VCOs (QVCOs) that are capable of generating frequencies in the range of 2.5 GHz to 2.9 GHz are implemented in a commercial 65 nm bulk CMOS technology to target for harsh radiation environments like space applications and high-energy physics (HEP) experiments. Each of the QVCOs consumes 13 mW power from a 1.2 V supply. The architectures are based on the popular implementation of two differe

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Matsunaga, Maya, Taiki Nakanishi, Atsuki Kobayashi, Kazuo Nakazato, and Kiichi Niitsu. "Design and analysis of a three-dimensional millimeter-wave frequency-shift based CMOS biosensor using vertically stacked spiral inductors in LC oscillators." Analog Integrated Circuits and Signal Processing 98, no. 3 (2018): 453–64. http://dx.doi.org/10.1007/s10470-018-1267-5.

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Novello, Alessandro, Gabriele Atzeni, Giorgio Cristiano, Mathieu Coustans, and Taekwang Jang. "A 2.3-GHz Fully Integrated DC–DC Converter Based on Electromagnetically Coupled Class-D LC Oscillators Achieving 78.1% Efficiency in 22-nm FDSOI CMOS." IEEE Solid-State Circuits Letters 4 (2021): 218–21. http://dx.doi.org/10.1109/lssc.2021.3126736.

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Mahdi, Ebrahimzadeh. "Design of an Ultra Low Power Low Phase Noise CMOS LC Oscillator." March 24, 2011. https://doi.org/10.5281/zenodo.1084756.

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In this paper we introduce an ultra low power CMOS LC oscillator and analyze a method to design a low power low phase noise complementary CMOS LC oscillator. A 1.8GHz oscillator is designed based on this analysis. The circuit has power supply equal to 1.1 V and dissipates 0.17 mW power. The oscillator is also optimized for low phase noise behavior. The oscillator phase noise is -126.2 dBc/Hz and -144.4 dBc/Hz at 1 MHz and 8 MHz offset respectively.

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Mahdi, Ebrahimzadeh. "Design of an Ultra Low Power Low Phase Noise CMOS LC Oscillator." International Journal of Electrical, Electronic and Communication Sciences 4.0, no. 3 (2011). https://doi.org/10.5281/zenodo.1335328.

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In this paper we introduce an ultra low power CMOS LC oscillator and analyze a method to design a low power low phase noise complementary CMOS LC oscillator. A 1.8GHz oscillator is designed based on this analysis. The circuit has power supply equal to 1.1 V and dissipates 0.17 mW power. The oscillator is also optimized for low phase noise behavior. The oscillator phase noise is -126.2 dBc/Hz and -144.4 dBc/Hz at 1 MHz and 8 MHz offset respectively.

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"Design of Beyond Millimeter Wave Oscillator in 22nm Bulk CMOS technology." International Journal of Engineering and Advanced Technology 9, no. 1S3 (2019): 68–72. http://dx.doi.org/10.35940/ijeat.a1014.1291s319.

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This paper presents the design of an LC oscillator using inductive feedback technique in bulk CMOS 22 nm technology using predictive technology models. The core oscillator is based on the popular Cherry Hooper amplifier topology. The development of the oscillator circuit from the standard Cherry Hooper topology is discussed in this paper with detailed analysis. The inductors are modelled by considering the various effects in this frequency range. The broadband technique used in the CH topology enables the circuit to oscillate at frequencies more than millimeter wave regime. By employing MOS va

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Gharbieh, Karam, Mohammed Ranneh, and Khaldoon Abugharbieh. "A wide-range 22-GHz LC-based CMOS voltage-controlled oscillator." International Journal of Electronics, January 2, 2018, 1–18. http://dx.doi.org/10.1080/00207217.2017.1419380.

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Azza, M. Anis, M. Abutaleb M., F. Ragai Hani, and I. Eladawy M. "Design of SiC Capacitive Pressure Sensor with LC-Based Oscillator Readout Circuit." April 21, 2012. https://doi.org/10.5281/zenodo.1055305.

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This paper presents the characterization and design of a capacitive pressure sensor with LC-based 0.35 µm CMOS readout circuit. SPICE is employed to evaluate the characteristics of the readout circuit and COMSOL multiphysics structural analysis is used to simulate the behavior of the pressure sensor. The readout circuit converts the capacitance variation of the pressure sensor into the frequency output. Simulation results show that the proposed pressure sensor has output frequency from 2.50 to 2.28 GHz in a pressure range from 0.1 to 2 MPa almost linearly. The sensitivity of the frequency shif

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Gaurav, Haramkar1. "A 2.4 GHZ FULLY INTEGRATED LC VCO DESIGN USING 130 NM CMOS TECHNOLOGY." October 31, 2016. https://doi.org/10.5281/zenodo.1157304.

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<strong>                          A 2.4 GHZ FULLY INTEGRATED LC VCO DESIGN USING 130 NM CMOS TECHNOLOGY</strong> In this paper, a 2.4 GHz fully integrated LC voltage controlled oscillator (VCO) for RF wireless applications is presented. The VCO circuit is designed using TSMC 130 nm CMOS process. The circuit design is based on differential oscillator structure with cross-coupled NMOS transistors which achieves low power dissipation and low phase noise. Simulation and layout of the VCO is carried out using ADS Tool. The VCO operate

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Son, Hyeon Jin, Dong‐Jun Shin, Ui‐Gyu Choi, and Jong‐Ryul Yang. "K‐band CMOS voltage‐controlled oscillator using switched self‐biasing technique." Microwave and Optical Technology Letters 66, no. 1 (2023). http://dx.doi.org/10.1002/mop.33979.

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AbstractA complementary metal oxide semiconductor (CMOS) voltage‐controlled oscillator (VCO) using a tail current source modulated with the output frequency is presented to achieve low phase noise with low power consumption at the K‐band. Differentially modulated current sources, which reduce flicker noise by the feedback of the VCO outputs, contribute to an overall reduction in the phase noise of the VCO using the electromagnetic‐based fully symmetrical design. The proposed LC VCO with a 3‐bit switched capacitor bank for a wide tuning range was fabricated on the size of 0.4 × 0.57 mm2 using a

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Yong, Wang, Ling Goh Wang, Hyup Lee Jung, T. C. Chai Kevin, and Je Minkyu. "Resonant-Based Capacitive Pressure Sensor Read-Out Oscillating at 1.67 GHz in 0.18." July 24, 2013. https://doi.org/10.5281/zenodo.1086867.

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This paper presents a resonant-based read-out circuit for capacitive pressure sensors. The proposed read-out circuit consists of an LC oscillator and a counter. The circuit detects the capacitance changes of a capacitive pressure sensor by means of frequency shifts from its nominal operation frequency. The proposed circuit is designed in 0.18m CMOS with an estimated power consumption of 43.1mW. Simulation results show that the circuit has a capacitive resolution of 8.06kHz/fF, which enables it for high resolution pressure detection.

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Bilel, Gassara, Abdellaoui Mahmoud, and Masmoud Nouri. "Multi Band Frequency Synthesizer Based on ISPD PLL with Adapted LC Tuned VCO." September 25, 2007. https://doi.org/10.5281/zenodo.1081848.

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The 4G front-end transceiver needs a high performance which can be obtained mainly with an optimal architecture and a multi-band Local Oscillator. In this study, we proposed and presented a new architecture of multi-band frequency synthesizer based on an Inverse Sine Phase Detector Phase Locked Loop (ISPD PLL) without any filters and any controlled gain block and associated with adapted multi band LC tuned VCO using a several numeric controlled capacitive branches but not binary weighted. The proposed architecture, based on 0.35μm CMOS process technology, supporting Multi-band GSM/DCS/DECT/ UM

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