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Relevant bibliographies by topics / CMOS op amp

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Journal articles

Academic literature on the topic 'CMOS op amp'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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Journal articles on the topic "CMOS op amp"

1

SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C TOW-THOMAS FILTER USING VOLTAGE OP AMP, CURRENT FEEDBACK OP AMP AND OPERATIONAL TRANSRESISTANCE AMPLIFIER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 151–79. http://dx.doi.org/10.1142/s0218126609004995.

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Several MOS-C realizations of the Tow-Thomas circuit using the commercially available voltage operational amplifier and the current feedback operational amplifier are reviewed in this paper. Additional MOS-C Tow-Thomas realizations using the operational transresistance amplifier and the differential current voltage conveyor are also included. MOS-C realizations of the Tow-Thomas circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS are included together with detailed comparison tables to demonstrate the differences between MOS-C Tow-Thomas circuits using both of the commercially available active building blocks and CMOS integrated building blocks.

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2

Babanazhad, J. N. "A rail-to-rail CMOS op amp." IEEE Journal of Solid-State Circuits 23, no. 6 (1988): 1414–17. http://dx.doi.org/10.1109/4.90040.

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3

Gupta, Pragati, and Shyam Akashe. "Implementation of an Ultra Low Power Process-Insensitive Two Stage Complementary Metal Oxide Semiconductor Operational Amplifier with Enhanced Direct Current Gain at 45 nm Technology Node." Sensor Letters 18, no. 10 (2020): 770–75. http://dx.doi.org/10.1166/sl.2020.4277.

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This paper presents an ultra low power process-insensitive two stage CMOS OP-AMP employing bulk-biasing technique realised in a standard 45 nm CMOS technology. Bulk-Biasing technique has been employed to augment the DC gain of two stage CMOS OP-AMP without having any impact on its power dissipation and output swing. In this work, high gain-bandwidth product (GBW) with appropriate phase margin is achieved through pseudo-cascode compensation approach which overcomes the drawbacks of Miller compensation technique also. Furthermore, the effect of width scaling on performance metrics of proposed OP-AMP has been analysed. The designed OP-AMP exhibits enhanced DC gain of 94.2 dB, gain-bandwidth product (GBW) of 460 MHz and adequate phase margin of 80°; with fast settling response. Also, the proposed OP-AMP has power dissipation of 27 μW and leakage current of 6.4 pA only. The design and optimisation of proposed OP-AMP is carried out at a power supply of 0.7 V under room temperature in Cadence Virtuoso tool.

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4

AL-Qaysi, Hayder Khaleel, Musaab Mohammed Jasim, and Siraj Manhal Hameed. "Design of very low-voltages and high-performance CMOS gate-driven operational amplifier." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 2 (2020): 670. http://dx.doi.org/10.11591/ijeecs.v20.i2.pp670-679.

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This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

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5

Zarabadi, S. R., F. Larsen, and M. Ismail. "A reconfigurable op-amp/DDA CMOS amplifier architecture." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 39, no. 6 (1992): 484–87. http://dx.doi.org/10.1109/81.153646.

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6

Looby, C. A., and C. Lyden. "Op-amp based CMOS field-programmable analogue array." IEE Proceedings - Circuits, Devices and Systems 147, no. 2 (2000): 93. http://dx.doi.org/10.1049/ip-cds:20000030.

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7

SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C KHN FILTER USING VOLTAGE OP AMP, CFOA, OTRA AND DCVC." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 733–69. http://dx.doi.org/10.1142/s021812660900523x.

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MOS-C realizations of the Kerwin–Huelsman–Newcomb (KHN) circuit using the commercially available Voltage Operational Amplifier (VOA) and the Current Feedback Operational Amplifier (CFOA) are reviewed in this paper. Additional MOS-C KHN realizations using the Operational Transresistance Amplifier (OTRA) and the Differential Current Voltage Conveyor (DCVC) are also included. MOS-C realizations of the KHN circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS are included together with detailed comparison tables to demonstrate the differences between MOS-C KHN circuits using both of the commercially available active building blocks and CMOS integrated building blocks. A comparison with the Gm-C KHN circuit is also included.

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8

Dadashi, Ali, Shamin Sadrafshari, Khayrollah Hadidi, and Abdollah Khoei. "Fast-settling CMOS Op-Amp with improved DC-gain." Analog Integrated Circuits and Signal Processing 70, no. 3 (2011): 283–92. http://dx.doi.org/10.1007/s10470-011-9668-8.

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9

MOTTAGHI-KASHTIBAN, M. "Modified CMOS Op-Amp with Improved Gain and Bandwidth." IEICE Transactions on Electronics E89-C, no. 6 (2006): 775–80. http://dx.doi.org/10.1093/ietele/e89-c.6.775.

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10

Lloyd, J., and Hae-Seung Lee. "A CMOS op amp with fully-differential gain-enhancement." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 41, no. 3 (1994): 241–43. http://dx.doi.org/10.1109/82.279212.

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