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Journal articles on the topic 'CMOS op amp'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C TOW-THOMAS FILTER USING VOLTAGE OP AMP, CURRENT FEEDBACK OP AMP AND OPERATIONAL TRANSRESISTANCE AMPLIFIER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 151–79. http://dx.doi.org/10.1142/s0218126609004995.

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Several MOS-C realizations of the Tow-Thomas circuit using the commercially available voltage operational amplifier and the current feedback operational amplifier are reviewed in this paper. Additional MOS-C Tow-Thomas realizations using the operational transresistance amplifier and the differential current voltage conveyor are also included. MOS-C realizations of the Tow-Thomas circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS are included together with detailed comparison tables to demonstrate the differences between MOS-C Tow-Thomas circuits using both of the commercially available active building blocks and CMOS integrated building blocks.

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2

Babanazhad, J. N. "A rail-to-rail CMOS op amp." IEEE Journal of Solid-State Circuits 23, no. 6 (1988): 1414–17. http://dx.doi.org/10.1109/4.90040.

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3

Gupta, Pragati, and Shyam Akashe. "Implementation of an Ultra Low Power Process-Insensitive Two Stage Complementary Metal Oxide Semiconductor Operational Amplifier with Enhanced Direct Current Gain at 45 nm Technology Node." Sensor Letters 18, no. 10 (2020): 770–75. http://dx.doi.org/10.1166/sl.2020.4277.

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This paper presents an ultra low power process-insensitive two stage CMOS OP-AMP employing bulk-biasing technique realised in a standard 45 nm CMOS technology. Bulk-Biasing technique has been employed to augment the DC gain of two stage CMOS OP-AMP without having any impact on its power dissipation and output swing. In this work, high gain-bandwidth product (GBW) with appropriate phase margin is achieved through pseudo-cascode compensation approach which overcomes the drawbacks of Miller compensation technique also. Furthermore, the effect of width scaling on performance metrics of proposed OP-AMP has been analysed. The designed OP-AMP exhibits enhanced DC gain of 94.2 dB, gain-bandwidth product (GBW) of 460 MHz and adequate phase margin of 80°; with fast settling response. Also, the proposed OP-AMP has power dissipation of 27 μW and leakage current of 6.4 pA only. The design and optimisation of proposed OP-AMP is carried out at a power supply of 0.7 V under room temperature in Cadence Virtuoso tool.

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4

AL-Qaysi, Hayder Khaleel, Musaab Mohammed Jasim, and Siraj Manhal Hameed. "Design of very low-voltages and high-performance CMOS gate-driven operational amplifier." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 2 (2020): 670. http://dx.doi.org/10.11591/ijeecs.v20.i2.pp670-679.

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This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

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5

Zarabadi, S. R., F. Larsen, and M. Ismail. "A reconfigurable op-amp/DDA CMOS amplifier architecture." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 39, no. 6 (1992): 484–87. http://dx.doi.org/10.1109/81.153646.

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6

Looby, C. A., and C. Lyden. "Op-amp based CMOS field-programmable analogue array." IEE Proceedings - Circuits, Devices and Systems 147, no. 2 (2000): 93. http://dx.doi.org/10.1049/ip-cds:20000030.

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7

SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C KHN FILTER USING VOLTAGE OP AMP, CFOA, OTRA AND DCVC." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 733–69. http://dx.doi.org/10.1142/s021812660900523x.

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MOS-C realizations of the Kerwin–Huelsman–Newcomb (KHN) circuit using the commercially available Voltage Operational Amplifier (VOA) and the Current Feedback Operational Amplifier (CFOA) are reviewed in this paper. Additional MOS-C KHN realizations using the Operational Transresistance Amplifier (OTRA) and the Differential Current Voltage Conveyor (DCVC) are also included. MOS-C realizations of the KHN circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS are included together with detailed comparison tables to demonstrate the differences between MOS-C KHN circuits using both of the commercially available active building blocks and CMOS integrated building blocks. A comparison with the Gm-C KHN circuit is also included.

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8

Dadashi, Ali, Shamin Sadrafshari, Khayrollah Hadidi, and Abdollah Khoei. "Fast-settling CMOS Op-Amp with improved DC-gain." Analog Integrated Circuits and Signal Processing 70, no. 3 (2011): 283–92. http://dx.doi.org/10.1007/s10470-011-9668-8.

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9

MOTTAGHI-KASHTIBAN, M. "Modified CMOS Op-Amp with Improved Gain and Bandwidth." IEICE Transactions on Electronics E89-C, no. 6 (2006): 775–80. http://dx.doi.org/10.1093/ietele/e89-c.6.775.

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10

Lloyd, J., and Hae-Seung Lee. "A CMOS op amp with fully-differential gain-enhancement." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 41, no. 3 (1994): 241–43. http://dx.doi.org/10.1109/82.279212.

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11

Mita, R., G. Palumbo, and S. Pennisi. "Low-voltage high-drive CMOS current feedback op-amp." IEEE Transactions on Circuits and Systems II: Express Briefs 52, no. 6 (2005): 317–21. http://dx.doi.org/10.1109/tcsii.2005.849004.

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12

Mandal, P., and V. Visvanathan. "CMOS op-amp sizing using a geometric programming formulation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 1 (2001): 22–38. http://dx.doi.org/10.1109/43.905672.

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13

Palmisano, G., G. Palumbo, and R. Salerno. "A 1.5-V high drive capability CMOS op-amp." IEEE Journal of Solid-State Circuits 34, no. 2 (1999): 248–52. http://dx.doi.org/10.1109/4.743789.

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14

Liang Dai and R. Harjani. "CMOS switched-op-amp-based sample-and-hold circuit." IEEE Journal of Solid-State Circuits 35, no. 1 (2000): 109–13. http://dx.doi.org/10.1109/4.818927.

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15

Bruun, Erik. "A dual current feedback op amp in CMOS technology." Analog Integrated Circuits and Signal Processing 5, no. 3 (1994): 213–17. http://dx.doi.org/10.1007/bf01261413.

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16

Safari, Ali, Massoud Dousti, and Mohammad Bagher Tavakoli. "Monolayer Graphene Field Effect Transistor-Based Operational Amplifier." Journal of Circuits, Systems and Computers 28, no. 03 (2019): 1950052. http://dx.doi.org/10.1142/s021812661950052x.

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Graphene Field Effect Transistor (GFET) is a promising candidate for future high performance applications in the beyond CMOS roadmap for analog circuit applications. This paper presents a Verilog-A implementation of a monolayer graphene field-effect transistor (mGFET) model. The study of characteristic curves is carried out using advanced design system (ADS) tools. Validation of the model through comparison with measurements from the characteristic curves is carried out using Silvaco TCAD tools. Finally, the mGFET is used to design a GFET-based operational amplifier (Op-Amp). The GFET Op-Amp performances are tuned in term of the graphene channel length in order to obtain a reasonable gain and bandwidth. The main characteristics of the Op-Amp performance are compared with 0.18[Formula: see text][Formula: see text]m CMOS technology.

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17

Shi, Jian Ying, Hui Ya Li, and Yan Bin Xu. "A New No Op Amp Full CMOS Voltage Reference Circuit." Applied Mechanics and Materials 519-520 (February 2014): 1067–70. http://dx.doi.org/10.4028/www.scientific.net/amm.519-520.1067.

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A no op amp structure full CMOS reference voltage circuit is designed. The two currents which are proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) are added together to get the reference output voltage which is obtained through a resistance. The characteristics of the new circuit are simulated using 0.5 μm BSIM3V3 spice models in HSPICE. The simulation results show that the output voltage of the circuit is 997mV, the power consumption is 1.12mW, the temperature coefficient is 15.2 ppm/°C in the range from-30°C to 100°C at the supply voltage of 2V.

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18

Hershenson, M. delM, S. P. Boyd, and T. H. Lee. "Optimal design of a CMOS op-amp via geometric programming." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 1 (2001): 1–21. http://dx.doi.org/10.1109/43.905671.

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19

Chachuli, Siti Amaniah Mohd, Puteri Nor Aznie Fasyar, Norhayati Soin, Nissar Mohammad Karim, and Norbayah Yusop. "Pareto ANOVA analysis for CMOS 0.18µm two-stage Op-amp." Materials Science in Semiconductor Processing 24 (August 2014): 9–14. http://dx.doi.org/10.1016/j.mssp.2014.02.035.

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20

Lu, C. W., and C. M. Hsiao. "1 V rail-to-rail constant-gm CMOS op amp." Electronics Letters 45, no. 11 (2009): 529. http://dx.doi.org/10.1049/el.2009.0763.

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21

Masunaga, Masahiro, Shintaroh Sato, Ryoh Kuwana, Isao Hara, and Akio Shima. "Improved Offset Voltage Stability of 4H-SiC CMOS Operational Amplifier by Increasing Gamma Irradiation Resistance." Materials Science Forum 963 (July 2019): 845–48. http://dx.doi.org/10.4028/www.scientific.net/msf.963.845.

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We modified the active layout of an operational amplifier (op-amp) to exhibit high gamma irradiation resistance of over 100-kGy using our 4H-SiC complementary MOS technology, which can be applied for measuring instruments installed in nuclear power plants. The op-amp with the modified active layout features both a thin gate oxide and newly developed gate-electrode structure for suppressing the leakage current. From an experiment we conducted, the leakage current of the p-channel MOSFET with modified active layout remained unchanged from the initial value after irradiation, although that of it with the conventional layout we previously evaluated increased by about two orders of magnitude. The offset voltage of the improved op-amp was maintained below 2.8 mV up to 100-kGy irradiation. The improved op-amp also showed a healthy amplification characteristic without distortion.

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22

CHA, Hyeong-Woo. "A resistance-difference to voltage converter using CMOS linear OTA and op amp." Journal of the Institute of Electronics and Information Engineers 54, no. 12 (2017): 74–80. http://dx.doi.org/10.5573/ieie.2017.54.12.74.

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23

ZHANG, C., A. SRIVASTAVA, and P. K. AJMERA. "NOISE ANALYSIS IN A 0.8 V FORWARD BODY-BIAS CMOS OP-AMP DESIGN." Fluctuation and Noise Letters 04, no. 02 (2004): L403—L412. http://dx.doi.org/10.1142/s0219477504001975.

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Noise model of a MOSFET, which includes the effect of forward-body bias, is proposed. Thermal noise and shot noise are extracted and their variations with the forward body-bias are compared. It is found that the shot noise increases with the forward body-bias and becomes significant above 0.4 V forward bias. A CMOS op-amp is designed utilizing forward body-bias technique combined with a level shift current mirror. The designed amplifier dissipates power of 40 μW and operates at ± 0.4 V to achieve a gain of 77 dB. The noise in this ultra low-power op-amp is also investigated. The total simulated output noise density of 320×10-12 V 2/ Hz in the ultra-low power op-amp design is slightly lower than the calculated 413×10-12 V 2/ Hz value from the proposed model.

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24

Assi, A., M. Sawan, and Jieyan Zhu. "An offset compensated and high-gain CMOS current-feedback op-amp." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 45, no. 1 (1998): 85–90. http://dx.doi.org/10.1109/81.660763.

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25

Giustolisi, G., G. Palmisano, and T. Segreto. "1.2-V CMOS op-amp with a dynamically biased output stage." IEEE Journal of Solid-State Circuits 35, no. 4 (2000): 632–36. http://dx.doi.org/10.1109/4.839923.

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26

SINGH, A. K., R. SENANI, D. R. BHASKAR, and R. K. SHARMA. "A NEW ELECTRONICALLY-TUNABLE ACTIVE-ONLY UNIVERSAL BIQUAD." Journal of Circuits, Systems and Computers 20, no. 03 (2011): 549–55. http://dx.doi.org/10.1142/s021812661100744x.

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A number of configurations for realizing voltage-mode (VM) biquads using op-amps and OTAs have been presented in the literature, however, none of these provide the following desirable properties simultaneously: (i) realizability of all the five standard filters (namely; low pass, high pass, band pass, band stop and all pass), (ii) tunability of all the three filter parameters (namely; ω0, bandwidth or Q0 and gain) and (iii) not requiring any realization condition in any of the five filter responses. This paper presents a new configuration which does possess all the above mentioned desirable properties simultaneously while using only two internally-compensated type op-amps and a reasonable number of OTAs. The workability of the new configuration has been demonstrated by SPICE simulations based upon CMOS Op-amp and CMOS OTAs.

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27

Gheorghe, Alexandru Gabriel, and Mihai Eugen Marin. "A Two Stage Op-Amp Phase Margin Symbolic Expression." MATEC Web of Conferences 210 (2018): 02040. http://dx.doi.org/10.1051/matecconf/201821002040.

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A phase margin symbolic expression of a two stage Miller compensated operational amplifier is computed in this paper. Using this expression, an analysis to evaluate the influence of the Miller and load capacitance on phase margin is performed. This way, a designer can rapidly choose the optimal set of values to fulfil an imposed phase margin. The phase margin expression is based on poles/zeros symbolic expressions obtained using a symbolic LR algorithm able to compute both the numerical values and the approximate symbolic expressions of poles and zeros of a circuit. The numerical values obtained with this algorithm are compared with those computed by SPECTRE. The example is a two stage Miller compensated operational amplifier designed in a 180nm CMOS technology.

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28

Dendouga, Abdelghani, and Slimane Oussalah. "Telescopic Op-Amp Optimization for MDAC Circuit Design." Electronics ETF 20, no. 2 (2017): 55. http://dx.doi.org/10.7251/els1620055d.

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An 8-bit 40-MS/s low power Multiplying Digital-to-Analog Converter (MDAC) for a pipelined-to-Analog to Digital converter (ADC) is presented. The conventional dedicated operational amplifier (Op-Amp) is performed by using telescopic architecture that features low power and less-area. Further reduction of power and area is achieved by using multifunction 1.5bit/stage MDAC arch itecture. The design of the Op-Amp is performed by the elaboration of a program based on multi objective genetic algorithms to allow automated optimization. The proposed program is used to find the optimal transistors sizes (length and width) in order to obtain the best Op-Amp performances for the MDAC. In th is study, six performances are considered, direct current gain, unity-gain bandwidth, phase margin, power consumption, area, slew rate, thermal noise, and signal to noise ratio. The Matlab optimization toolbox is used to implement the program. Simulations were performed by using Cadence Virtuoso Spectre circuit simulator in standard AMS 0.18μm CMOS technology. A good agreement is observed between the results obtained by the program optimization and simulation, after that the Op-Amp is introduced in the MDAC circuit to extract its performances.

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29

Jee, Dong-Woo, Yunjae Suh, Hong-June Park, and Jae-Yoon Sim. "A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC." Journal of Circuits, Systems and Computers 25, no. 12 (2016): 1650155. http://dx.doi.org/10.1142/s0218126616501553.

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A digitally controlled operational amplifier (op-amp) with level-crossing-based approximation is proposed. A high gain is effectively obtained by means of a damping control without a stability problem occurring in the multiple gain stages. Compared to the previous version of the zero-crossing-based algorithmic approximation, the proposed scheme further improves the settling time with the class AB operation obtained by switching of multiple driving paths. For verification, the designed op-amp is applied to a 10-bit pipeline ADC and implemented in a 0.18[Formula: see text][Formula: see text]m CMOS technology. Measured results show that the designed op-amp successfully operates at 10-bit resolution, 10[Formula: see text]MSample/s pipeline ADC and achieves an effective gain of more than 60[Formula: see text]dB.

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30

Ismail, A. M., and A. M. Soliman. "Novel CMOS current feedback op-amp realization suitable for high frequency applications." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 47, no. 6 (2000): 918–21. http://dx.doi.org/10.1109/81.852946.

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31

Steyaert, M., and W. Sansen. "A high-dynamic-range CMOS op amp with low-distortion output structure." IEEE Journal of Solid-State Circuits 22, no. 6 (1987): 1204–7. http://dx.doi.org/10.1109/jssc.1987.1052876.

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32

Bruun, Erik. "Bandwidth optimization of a low power, high speed CMOS current op amp." Analog Integrated Circuits and Signal Processing 7, no. 1 (1995): 11–19. http://dx.doi.org/10.1007/bf01256443.

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33

Chanapromma, Chaiyan, and Jirayuth Mahattanakul. "New method to design feedback amplifier employing two-stage CMOS op amp." AEU - International Journal of Electronics and Communications 132 (April 2021): 153616. http://dx.doi.org/10.1016/j.aeue.2021.153616.

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34

Sahu, Rashmi, Maitraiyee Konar, and Sudip Kundu. "Improvement of Gain Accuracy and CMRR of Low Power Instrumentation Amplifier Using High Gain Operational Amplifiers." Micro and Nanosystems 12, no. 3 (2020): 168–74. http://dx.doi.org/10.2174/1876402912666200123153318.

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Background: Sensing of biomedical signals is crucial for monitoring of various health conditions. These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of a low power INA topology. Objective: The objective of this article is to achieve high gain accuracy and CMRR of low power INA by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs. Methods: For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used. All the designs and implementation were realized in 0.18 μm CMOS technology. Results: Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately, three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized using the other two Op-Amp topologies implemented. Conclusion: Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply of ±0.9V. This makes this INA highly suitable for low power measurement applications.

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35

Sama, Nihar Jouti, and Manash Pratim Sarma. "A High Gain, High BW OP AMP with Frequency Compensation Techniques at 65 nm Technology." WSEAS TRANSACTIONS ON ELECTRONICS 12 (August 10, 2021): 89–92. http://dx.doi.org/10.37394/232017.2021.12.12.

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OP-AMPs finds applications in different domains of electronics engineering including communications. There has been several OP-AMP configurations realized in the last decades for different target applications. But with the evolution of communication standards, to meet the demand for high data rate over the years, requirement for a high frequency and high BW OP-AMP is gaining attention. This makes the design challenge much higher. This paper presents a two-stage CMOS amplifier which uses frequency compensation method to facilitate higher BW. Different parameters like Gain, Gain band width product (GBWP), Phase Margin and Total Power dissipation are considered in this design. A step-by-step procedure for an efficient amplifier design is followed using frequency compensation. We have achieved a gain-bandwidth product (GBWP) of 110 MHz that is capable of driving large capacitive loads. It also achieves 77.7 dB gain with a phase margin of 60o.

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36

Du, Yiheng, Changde He, Guowei Hao, Wendong Zhang, and Chenyang Xue. "Full-Differential Folded-Cascode Front-End Receiver Amplifier Integrated Circuit for Capacitive Micromachined Ultrasonic Transducers." Micromachines 10, no. 2 (2019): 88. http://dx.doi.org/10.3390/mi10020088.

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This paper describes the design of a front-end receiver amplifier for capacitive micromachined ultrasonic transducer (CMUT). The proposed operational amplifier (op amp) consists of a full differential folded-cascode amplifier stage followed by a class AB output stage. A feedback resistor is applied between the input and the output of the op amp to make a transimpedance amplifier. We analyzed the equivalent circuit model of the CMUT element operating in the receiving mode and obtained the static output impedance and center frequency characteristics of the CMUT. The op amp gain, bandwidth, noise, and power consumption trade-oﬀs are discussed in detail. The amplifier was fabricated using GlobalFoundries 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. The open loop gain of the amplifier is approximately 65 dB, and its gain bandwidth product is approximately 29.5 MHz. The measured input reference noise current was 56 nA/√Hz@3 MHz. The amplifier chip area is 325 μm × 150 μm and the op amp is powered by 3.3 V, the static power consumption is 11 mW. We verified the correct operation of our amplifier with CMUT and echo-pulse shown that the CMUT center frequency is 3 MHz with 92% fractional bandwidth.

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37

Idros, Norhamizah, Zulfiqar Ali Abdul Aziz, and Jagadheswaran Rajendran. "A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier." Microelectronics International 37, no. 4 (2020): 205–13. http://dx.doi.org/10.1108/mi-05-2020-0030.

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Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

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38

MAHMOUD, SOLIMAN A. "LOW POWER LOW-PASS FILTER WITH PROGRAMMABLE CUTOFF FREQUENCY BASED ON A TUNABLE UNITY GAIN FREQUENCY OPERATIONAL AMPLIFIER." Journal of Circuits, Systems and Computers 19, no. 08 (2010): 1651–63. http://dx.doi.org/10.1142/s0218126610006979.

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In this paper, a sixth-order reconfigurable low pass filter (LPF) is realized using 0.25 μm TSMC CMOS technology. The filter is based on a cascading connection of bi-quadratic active-Gm-RC cells. The active-Gm-RC cells are realized using compensated op-amps with variable transconductance gain and variable compensation capacitors (variable Gm–Cc op-amp). The tuning range of the filter's cutoff frequency is from 77.4 KHz to 37.78 MHz. The filter operates from a single supply of 1.5 V. Simulations results using PSPICE for the proposed reconfigurable LPF are presented.

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39

Yu, Sang Dae. "Small-Signal Analysis of a Differential Two-Stage Folded-Cascode CMOS Op Amp." JSTS:Journal of Semiconductor Technology and Science 14, no. 6 (2014): 768–76. http://dx.doi.org/10.5573/jsts.2014.14.6.768.

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40

Balaji, M., and N. Padmaja. "Design and analysis of CMOS based Op-Amp for low power biomedical applications." TARU Journal of Sustainable Technologies and Computing 1, no. 1 (2019): 9–23. http://dx.doi.org/10.47974/tjstc.008.2019.v01i01.

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41

Carrillo, Juan M., J. Francisco Duque-Carrillo, Guido Torelli, and José L. Ausı́n. "1-V quasi constant-g input/output rail-to-rail CMOS op-amp." Integration 36, no. 4 (2003): 161–74. http://dx.doi.org/10.1016/j.vlsi.2003.08.002.

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42

Monticelli, D. M. "A quad CMOS single-supply op amp with rail-to-rail output swing." IEEE Journal of Solid-State Circuits 21, no. 6 (1986): 1026–34. http://dx.doi.org/10.1109/jssc.1986.1052645.

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Chakraborty, Subhra, Abhishek Pandey, and Vijay Nath. "Ultra high gain CMOS Op-Amp design using self-cascoding and positive feedback." Microsystem Technologies 23, no. 3 (2016): 541–52. http://dx.doi.org/10.1007/s00542-016-2971-7.

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Opalski, Leszek. "Remarks on Statistical Design Centering." International Journal of Electronics and Telecommunications 57, no. 2 (2011): 159–67. http://dx.doi.org/10.2478/v10177-011-0023-x.

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Remarks on Statistical Design CenteringThe paper overviews optimization based statistical design centering techniques for analog circuits. Emphasis is placed on dependence between formulation of quality indices, problem formulation, and computational complexity of design centering algorithms, executed in single- or multiple-processor environments. For characterization of solution techniques a standard CMOS op-amp design case and a simplified computational complexity analysis are used.

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45

Khatak, Anil, Manoj Kumar, and Sanjeev Dhull. "An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits." Journal of Low Power Electronics and Applications 8, no. 4 (2018): 33. http://dx.doi.org/10.3390/jlpea8040033.

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A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

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Kumar, Kandi Praveen, and D. Vaithiyanathan. "Design and analysis of a three stage CMOS op-amp using indirect feedback compensation." Journal of Physics: Conference Series 1706 (December 2020): 012055. http://dx.doi.org/10.1088/1742-6596/1706/1/012055.

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Liu, Maliang, Dengquan Li, and Zhangming Zhu. "A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 4 (2020): 650–54. http://dx.doi.org/10.1109/tcsii.2019.2926133.

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48

Bult, K., and G. J. G. M. Geelen. "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain." IEEE Journal of Solid-State Circuits 25, no. 6 (1990): 1379–84. http://dx.doi.org/10.1109/4.62165.

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Nagulapalli, Rajasekhar, Khaled Hayatleh, and Steve Barker. "A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications." Journal of Circuits, Systems and Computers 29, no. 14 (2020): 2050220. http://dx.doi.org/10.1142/s0218126620502205.

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A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[Formula: see text]nm CMOS technology. It results in 81[Formula: see text]dB voltage gain, which is 21[Formula: see text]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[Formula: see text]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[Formula: see text]V supply. The circuit draws a total static current of 295[Formula: see text][Formula: see text]A and occupies 5000[Formula: see text][Formula: see text]m2 of silicon area.

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Cui, Lin Hai, Rui Xu, Zhan Peng Jiang, and Chang Chun Dong. "Design of a Low-Voltage Low-Power CMOS Operational Amplifier." Applied Mechanics and Materials 380-384 (August 2013): 3283–86. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3283.

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A low voltage, low power two-stage operational amplifier (op-amp) was proposed in this paper. A folded-cascode structure is used in the input stage of the amplifier to get high gain. Current mirrors are used in the input stage to make the transconduotance constant. A simple push-pull common source amplifier is adopted as the output stage to take the advantages of its high efficiency. The experimental results show that the unity-gain bandwidth is 12.5MHz, the low-frequency open-loop voltage gain is 100dB,the phase margin is 65°, and power dissipation is 98.8μw.

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