Academic literature on the topic 'CMOS power'
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Journal articles on the topic "CMOS power"
GABARA, THAD. "PULSED LOW POWER CMOS." International Journal of High Speed Electronics and Systems 05, no. 02 (June 1994): 159–77. http://dx.doi.org/10.1142/s0129156494000097.
Full textRen, Zhixiong, Kefeng Zhang, Xiaofei Chen, and Zhenglin Liu. "Scalable CMOS power combiner." Electronics Letters 50, no. 6 (March 2014): 431–32. http://dx.doi.org/10.1049/el.2013.3611.
Full textBlair, G. M. "Designing low-power digital CMOS." Electronics & Communication Engineering Journal 6, no. 5 (October 1, 1994): 229–36. http://dx.doi.org/10.1049/ecej:19940505.
Full textNiknejad, Ali M., Debopriyo Chowdhury, and Jiashu Chen. "Design of CMOS Power Amplifiers." IEEE Transactions on Microwave Theory and Techniques 60, no. 6 (June 2012): 1784–96. http://dx.doi.org/10.1109/tmtt.2012.2193898.
Full textChandrakasan, A. P., S. Sheng, and R. W. Brodersen. "Low-power CMOS digital design." IEEE Journal of Solid-State Circuits 27, no. 4 (April 1992): 473–84. http://dx.doi.org/10.1109/4.126534.
Full textFrank, D. J. "Power-constrained CMOS scaling limits." IBM Journal of Research and Development 46, no. 2.3 (March 2002): 235–44. http://dx.doi.org/10.1147/rd.462.0235.
Full textAzeredo Leme, C., I. Filanovsky, and H. Baltes. "CMOS stabilised DC power source." Electronics Letters 28, no. 12 (1992): 1153. http://dx.doi.org/10.1049/el:19920728.
Full textIsmail, A. M., and A. M. Soliman. "Low-power CMOS current conveyor." Electronics Letters 36, no. 1 (2000): 7. http://dx.doi.org/10.1049/el:20000129.
Full textEl-Moursy, Magdy A., and Eby G. Friedman. "Resistive Power in CMOS Circuits." Analog Integrated Circuits and Signal Processing 41, no. 1 (October 2004): 5–11. http://dx.doi.org/10.1023/b:alog.0000038278.71500.0c.
Full textHaldi, P., G. Liu, and A. M. Niknejad. "CMOS compatible transformer power combiner." Electronics Letters 42, no. 19 (2006): 1091. http://dx.doi.org/10.1049/el:20061585.
Full textDissertations / Theses on the topic "CMOS power"
Scholvin, Jörg 1976. "RF power CMOS." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86742.
Full textIncludes bibliographical references (p. 103-105).
by Jörg Scholvin.
M.Eng.and S.B.
Fritzin, Jonas. "Power Amplifier Circuits in CMOS Technologies." Licentiate thesis, Linköping : Department of Electrical Engineering, Linköpings universitet, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-21030.
Full textWang, Chengzhou. "CMOS power amplifiers for wireless communications /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3112826.
Full textGogineni, Usha 1975. "Performance limits of RF power CMOS." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/63070.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (p. 131-136).
Wireless and mobile communication systems have become ubiquitous in our daily life. The need for higher bandwidth and thus higher speed and data rates in wireless communications has prompted the exploration of millimeter-wave frequencies. Some of the applications in this regime include high-speed wireless local area networks and high data rate personal area networks at 60 GHz, automotive collision avoidance radar at 77 GHz and millimeter-wave imaging at 94 GHz. Most of these applications are cost sensitive and require high levels of integration to reduce system size. The tremendous improvement in the frequency response of state-of-the-art deeply scaled CMOS technologies has made them an ideal candidate for millimeter-wave applications. A few research groups have already demonstrated single chip CMOS radios at 60 GHz. However, the design of power amplifiers in CMOS still remains a significant challenge because of the low breakdown voltage of deep submicron CMOS technologies. Power levels from 60 GHz power amplifiers have been limited to around 15 dBm with power-added efficiencies in the 10-20% range, despite the use of multiple gain stages and power combining techniques. In this work, we have studied the RF power potential of commercial 65 nm and 45 nm CMOS technologies. We have mapped the frequency, power and efficiency limitations of these technologies and identified the physical mechanisms responsible for these limitations. We also present a simple analytical model that allows circuit designers to estimate the maximum power obtainable from their designs for a given efficiency. The model uses only the DC bias point and on-resistance of the device as inputs and contains no adjustable parameters. We have demonstrated a record output power density of 210 mW/mm and power-added efficiency in excess of 75% at VDs = 1.1 V and f = 2 GHz on 45 nm CMOS devices. This record power performance was made possible through careful device layout for minimized parasitic resistances and capacitances. Total output power approaching 70 mW was measured on 45 nm CMOS devices by increasing the device width to 640 gm. However, we find that the output power scales non-ideally with device width because of an increase in normalized on-resistance in the wide devices. PAE also decreases with increasing device width because of degradation in f. in the wide devices. Additionally PAE decreases as the measurement frequency increases, though the output power remains constant with increasing frequency. Small-signal equivalent circuit extractions on these devices suggest that the main reason for the degradation in the normalized output power and PAE with increasing device width is the non-ideal scaling of parasitic gate and drain resistances in the wide devices.
by Usha Gogineni.
Ph.D.
Aloui, Sofiane. "Design of 60ghz 65nm CMOS power amplifier." Thesis, Bordeaux 1, 2010. http://www.theses.fr/2010BOR14165/document.
Full textTelecommunication industry claims for increasing data rate in wireless communication systems. The major demand of high data rate applications concerns a large panel of home multimedia exchanging data especially for the uncompressed HD data transfer. The 7GHz band around 60GHz is free of use and fulfils the short range gigabit communication requirements. CMOS technology is most appropriate since it drives a fast time to market with a low cost for high integration volume. However, the use of CMOS technology is challenging to satisfy loss and performance trade-off under power constraints. This thesis aims at designing power amplifiers operating at 60GHz with 65nm CMOS technology from STMicroelectronics. This approach is progressive because it is necessary to analyze and optimize the performance of passive and active components constituting the power amplifier using electromagnetic and microelectronics software. Finally, power amplifiers have been made. Their performances met specifications originally defined
Guimarães, Gabriel Teófilo Neves. "CMOS linear RF power amplifier with fully integrated power combining transformer." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/169084.
Full textThis work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.
Rabe, Dirk. "Accurate power analysis of integrated CMOS circuits on gate level." [S.l.] : [s.n.], 2001. http://deposit.ddb.de/cgi-bin/dokserv?idn=962733520.
Full textYeh, David Alexander. "Multi-gigabit low-power wireless CMOS demodulator." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41168.
Full textFritzin, Jonas. "CMOS RF Power Amplifiers for Wireless Communications." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71852.
Full textJörgensen, Sofie. "Modelling of Power Dissipation in CMOS DACs." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1329.
Full textIn this master thesis work, the power dissipation in a current-steering digital- to-analog converter, DAC, has been studied. The digital as well as the analog power dissipation have been modelled in MATLAB and it is shown that the MATLAB models agrees well with simulation results from the circuit simulator (Spectre).
A case study on a DAC designed at Ericsson Microelectronics AB in Linköping has also been done. The DAC is a thermometer-coded current-steering DAC suitable for telecommunications applications. The telecommunication standards that have been studied are asymmetric digital subscriber line, ADSL, very high speed data digital subscriber line, VDSL, and, wireless local area network, WLAN. The conlusion of the study is that the power dissipation of the specific DAC, used in ADSL applications, 75mW, is far from optimized. It can theoretically be lowered to 3.5mW.
Books on the topic "CMOS power"
1945-, Brodersen Robert W., ed. Low power digital CMOS design. Boston: Kluwer Academic Publishers, 1995.
Find full textChandrakasan, Anantha P. Low Power Digital CMOS Design. Boston, MA: Springer US, 1995.
Find full textChandrakasan, Anantha P., and Robert W. Brodersen. Low Power Digital CMOS Design. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3.
Full textVillar Piqué, Gerard, and Eduard Alarcón. CMOS Integrated Switching Power Converters. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8843-0.
Full textSolar Ruiz, Hector, and Roc Berenguer Pérez. Linear CMOS RF Power Amplifiers. Boston, MA: Springer US, 2014. http://dx.doi.org/10.1007/978-1-4614-8657-2.
Full textSheng, Samuel, and Robert Brodersen. Low-Power CMOS Wireless Communications. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5457-8.
Full textSoudris, Dimitrios, Christian Piguet, and Costas Goutis, eds. Designing CMOS Circuits for Low Power. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-3530-7.
Full textItoh, Kiyoo, Thomas Lee, Takayasu Sakurai, Willy M. C. Sansen, and Doris Schmitt-Landsiedel, eds. Low Power VCO Design in CMOS. Berlin/Heidelberg: Springer-Verlag, 2006. http://dx.doi.org/10.1007/3-540-29256-x.
Full textJoão, Goes, and Steiger-Garção Adolfo, eds. Low power UWB CMOS radar sensors. [Dordrecht]: Springer, 2008.
Find full textBook chapters on the topic "CMOS power"
Saini, Sandeep. "CMOS Buffer." In Low Power Interconnect Design, 33–54. New York, NY: Springer New York, 2015. http://dx.doi.org/10.1007/978-1-4614-1323-3_2.
Full textAthas, William C. "Energy-Recovery CMOS." In Low Power Design Methodologies, 65–100. Boston, MA: Springer US, 1996. http://dx.doi.org/10.1007/978-1-4615-2307-9_4.
Full textSolar Ruiz, Hector, and Roc Berenguer Pérez. "CMOS Performance Issues." In Linear CMOS RF Power Amplifiers, 57–73. Boston, MA: Springer US, 2013. http://dx.doi.org/10.1007/978-1-4614-8657-2_4.
Full textBhushan, Manjul, and Mark B. Ketchen. "IDDQ and Power." In CMOS Test and Evaluation, 125–57. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4939-1349-7_4.
Full textMarcon, Denis, and Steve Stoffels. "GaN-on-Silicon CMOS-Compatible Process." In Power Electronics and Power Systems, 53–68. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-43199-4_3.
Full textBellaouar, Abdellatif, and Mohamed I. Elmasry. "VLSI CMOS Subsystem Design." In Low-Power Digital VLSI Design, 409–87. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2355-0_7.
Full textSolar Ruiz, Hector, and Roc Berenguer Pérez. "Power Amplifier Design." In Linear CMOS RF Power Amplifiers, 101–51. Boston, MA: Springer US, 2013. http://dx.doi.org/10.1007/978-1-4614-8657-2_6.
Full textWang, Zhihua, Xiang Xie, Xinkai Chen, and Xiaowen Li. "Design Considerations of Low-Power Digital Integrated Systems for Implantable Medical Applications." In CMOS Biomicrosystems, 119–62. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2011. http://dx.doi.org/10.1002/9781118016497.ch5.
Full textKim, Hyejung, and Hoi-Jun Yoo. "Low Power Bio-Medical DSP." In Bio-Medical CMOS ICs, 191–215. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6597-4_6.
Full textVeendrick, H. J. M. "Low power, a hot topic in IC design." In Nanometer CMOS ICs, 447–509. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8333-4_8.
Full textConference papers on the topic "CMOS power"
Jaejune Jang, Jaehyeon Jung, Hoon Chang, Yongdon Kim, Seoin Park, Hyunju Kim, Jaehwan Kim, and Sangbae Yi. "Mobility enhanced power CMOS." In 2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2013. http://dx.doi.org/10.1109/ispsd.2013.6694452.
Full textAparicio, Hernan, Pablo Ituero, and Marisa Lopez-Vallejo. "2.64 pJ reference-free power supply monitor with a wide temperature range." In 2015 6th International Workshop on CMOS Variability (VARI). IEEE, 2015. http://dx.doi.org/10.1109/vari.2015.7456555.
Full textHuang, Yu-Chun, and Zhi-Ming Lin. "High Power CMOS Power Amplifier for WCDMA." In APCCAS 2006. 2006 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/apccas.2006.342366.
Full textSakphrom, Siraporn, and Apinunt Thanachayanont. "A low-power CMOS RF power detector." In 2012 19th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2012). IEEE, 2012. http://dx.doi.org/10.1109/icecs.2012.6463771.
Full textSchoebinger, Matthias, and Tobias G. Noll. "Low power CMOS design strategies." In the 31st annual conference. New York, New York, USA: ACM Press, 1994. http://dx.doi.org/10.1145/196244.196574.
Full textChen, An. "Low-power beyond-CMOS devices." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021204.
Full textZhang-Jie and Hong-Qi. "A 1GHz low power CMOS LNA." In 2007 International Conference on Microwave and Millimeter Wave Technology. IEEE, 2007. http://dx.doi.org/10.1109/icmmt.2007.381466.
Full textMendoza, R., A. Ferre, L. Balado, and J. Figueras. "CMOS leakage power at cell level." In International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. IEEE, 2006. http://dx.doi.org/10.1109/dtis.2006.1708658.
Full textLee, Chan-Soo, Munkhsuld Gendensuren, Zhi-Yuan Cui, Kie-Young Lee, and Nam-Soo Kim. "High power CMOS circuit with LDMOSFET." In 2011 International Semiconductor Device Research Symposium (ISDRS). IEEE, 2011. http://dx.doi.org/10.1109/isdrs.2011.6135373.
Full textFu, Jian, Shilei Hao, Yumei Huang, and Zhiliang Hong. "A 2.4G-Hz CMOS Power Amplifier." In 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2010. http://dx.doi.org/10.1109/icsict.2010.5667289.
Full textReports on the topic "CMOS power"
Nguyen, Du Van. An ASIC Power Analysis System for Digital CMOS Design. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.7249.
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