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Fritzin, Jonas. "Power Amplifier Circuits in CMOS Technologies." Licentiate thesis, Linköping : Department of Electrical Engineering, Linköpings universitet, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-21030.
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Aloui, Sofiane. "Design of 60ghz 65nm CMOS power amplifier." Thesis, Bordeaux 1, 2010. http://www.theses.fr/2010BOR14165/document.
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Le développement d'objets communicants dédiés aux applications Wireless Personal Area Network (WPAN) à 60GHz vise des débits de l'ordre du GBit/sec. Pour satisfaire la contrainte de faible coût, la technologie CMOS silicium est la plus adaptée. L'utilisation de cette technologie est un challenge en soi afin de concilier les aspects « pertes & rendement » vis à vis des contraintes de puissance. Le but de la thèse est de concevoir des amplificateurs de puissance opérant à 60GHz avec la technologie CMOS 65nm de STMicroelectronics. Cette démarche est progressive car il convient d'analyser puis d'optimiser les performances des composants passifs et actifs constituant l'amplificateur de puissance à l'aide des logiciels de simulations électromagnétique et microélectronique. Finalement, des amplificateurs de puissance ont été réalisés et leurs performances répondent au cahier des charges initialement défini<br>Telecommunication industry claims for increasing data rate in wireless communication systems. The major demand of high data rate applications concerns a large panel of home multimedia exchanging data especially for the uncompressed HD data transfer. The 7GHz band around 60GHz is free of use and fulfils the short range gigabit communication requirements. CMOS technology is most appropriate since it drives a fast time to market with a low cost for high integration volume. However, the use of CMOS technology is challenging to satisfy loss and performance trade-off under power constraints. This thesis aims at designing power amplifiers operating at 60GHz with 65nm CMOS technology from STMicroelectronics. This approach is progressive because it is necessary to analyze and optimize the performance of passive and active components constituting the power amplifier using electromagnetic and microelectronics software. Finally, power amplifiers have been made. Their performances met specifications originally defined
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Sjöholm, Olof. "Integrated CMOS Doppler Radar : Power Amplifier Mixer." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129105.
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This thesis is based on a paper by V. Issakov, presented 2009, where a circuit of a merged power amplifier mixer solution was demonstrated. This work takes that solution and simplifies it for the use at a lower frequency. The implementation target is a Doppler radar application in CMOS that can detect humans in a range of 5 to 15 meters. This could be used as a burglar alarm or an automatic light switch. The report will present the background of Issakov’s work, basic theory used and the implementation of the final design. Simulations will show that the solution presented work, with a 15 dB conversion loss. This design performs well compared to reference mixers. With this report it will be shown that it is possible to make a simple and compact Doppler radar system in CMOS.<br>Denna avhandling bygger på en artikel av V. Issakov, presenterad 2009, där en lösning för att sammanslå en effektförstärkare med en mixer till en krets visades. Detta arbete tar denna lösning och förenklar det för användning vid en lägre frekvens. Målet är att implementera en dopplerradar i CMOS som kan detektera människor inom ett avstånd på 5 till 15 meter. Denna radar skulle kunna användas som ett inbrottslarm eller en automatisk strömbrytare. Rapporten kommer att presentera bakgrunden från Issakov’s arbete, grundläggande teori som används och genomförandet av det slutliga kretsschemat. Simuleringar visar att den presenterade lösningen fungerar, med en 15 dB konverteringsförlust. Denna konstruktion presterar väl jämfört med referens mixrar. Med denna rapport visas det att det är möjligt att göra ett enkelt och kompakt dopplerradarsystem i CMOS.
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Lee, Ockgoo. "High efficiency switching CMOS power amplifiers for wireless communications." Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/37145.
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High-efficiency performance is one of the most important requirements of power
amplifiers (PAs) for wireless applications. However, the design of highly efficient CMOS
PAs for watt-level applications is a challenging task. This dissertation focuses on the
development of the design method for highly efficient CMOS PAs to overcome the
fundamental difficulties presented by CMOS technology.
In this dissertation, the design method and analysis for a high-power and highefficiency
class-E CMOS PA with a fully integrated transformer have been presented.
This work is the first effort to set up a comprehensive design methodology for a fully
integrated class-E CMOS PA including effects of an integrated transformer, which is
very crucial for watt-level power applications. In addition, to improve efficiency of
cascode class-E CMOS PAs, a charging acceleration technique is developed. The method
accelerates a charging speed to turn off the common-gate device in the off-state, thus
reducing the power loss. To demonstrate the proposed cascode class-E PA, a prototype
CMOS PA was implemented in a 0.18-μm CMOS process. Measurements show an
improvement of approximately 6% in the power added efficiency. The proposed cascode
class-E PA structure is suitable for the design of high-efficiency class-E PAs while it
reduces the voltage stress across the device.
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Chan, Chung-Kei Thomas. "CMOS class E power amplifier for mobile communications." Thesis, Imperial College London, 2003. http://hdl.handle.net/10044/1/8524.
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Guimarães, Gabriel Teófilo Neves. "CMOS linear RF power amplifier with fully integrated power combining transformer." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/169084.
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Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais.<br>This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.
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Jose, Sajay. "Design of RF CMOS Power Amplifier for UWB Applications." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/36391.
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Ever since the FCC allocated 7.5 GHz (from 3.1 GHz to 10.6 GHz) for ultra wideband (UWB) technology, interest has been renewed in both academic and industrial circles to exploit this vast spectrum for short range, high data rate wireless applications. The great potential of UWB lies in the fact that it can co-exist with the already licensed spectrum users and can still pave the way for a wide range of applications.
However, this wide bandwidth complicates the circuit level implementation of key RF blocks like the power amplifier (PA), transmit/receive switch, low noise amplifier (LNA) and mixers in an UWB transceiver. Though expensive technologies like SiGe or GaAs have been used for transceiver realizations, the ultimate goal is to have a single-chip, low-cost solution which can only be achieved by using CMOS technology. Nevertheless, some of the inherent limitations of CMOS like lower fT of transistors make the design of UWB circuits in CMOS an extremely challenging task.
Two proposals- Multi-Band OFDM and Direct-Sequence CDMA have been put before the IEEE 802.15.3a task group to decide on the industry standard for the commercial deployment of this technology. Though the debate on which standard is better has not been resolved, proponents of both the groups have already begun to develop prototypes of their respective proposals.
This thesis describes the design of a key RF block in the UWB transceiver - the Power Amplifier. For the first part of this work, a PA suitable for MB-OFDM specifications was designed and fabricated in TSMC 0.18um CMOS technology. The class-AB PA is able to cover the lower UWB frequency band from 3.1 GHz to 4.75 GHz and delivers an output power of -2 dBm at 4 GHz. Simulated results show a gain of 19±2 dB achieved over the entire band and the PA consumes 36.54 mW from a 1.8V supply.
In the second part of this work, a PA that meets the DS-CDMA specifications was designed and fabricated. This PA operates in the class-AB regime, delivering an output power of -4.2 dBm with input-1dB compression point at -22 dBm. Complete design and implementation was done using TSMC 0.18um CMOS technology and it consumes a very low power of 25 mW, while realizing a flat gain of 19±1 dB across the whole band of operation. All the above mentioned results are from simulations in SpectreRF and measurements are yet to be taken. Additional features like power ON/OFF scheme and output impedance control has also been incorporated in the design.<br>Master of Science
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Tofte, Røislien Nina. "5.8GHz, 1W high efficiency Power Amplifier in 90nm CMOS." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9987.
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<p>PREFACE This masters thesis was written as the final step towards my masters degree, and it thereby marks the ending of my time at NTNU. The masters thesis was developed due to a proposal made by Texas Instruments, under the offered supervision of Oddgeir Fikstvedt. My supervisor at NTNU was Morten Olavsbråten. This report describes the design of a power amplifier in the 90nm CMOS technology. The power amplifier is designed to deliver 1W output power at 5.8GHz with a peak efficiency of 50%. Both the class-E and the inverse class-D amplifier are described and examined, but the final choice in amplifier design is the inverse class-D amplifier. Simulation results on a realistic inverse class-D amplifier model are presented as the final outcome. Trondheim, 2009-07-16 Nina Tofte Røislien ABSTRACT Recently CMOS has been introduced as a technology for RF-front end applications. This results in higher levels of integration, which saves fabrication cost and area. The power amplifier often contributes to the highest power consumption, and the efficiency becomes very important. This masters thesis handles the design of a CMOS power amplifier at 5.8GHz. The design goals were an output power of 30dBm, a Power Added Efficiency of 50% and a gain of 25dB. The main challenge in the CMOS-technology is the low breakdown voltage. This leads to a higher current and a lower load resistance compared to traditionally used RF-technologies. This makes it harder to design a high efficiency amplifier because of more power loss in the parasitic, and a more complex matching network. Two different amplifiers were investigated, both of the switching type; the class-E amplifier and the inverse class-D amplifier (current mode). The class-E amplifier has been studied by others for this kind of use, and has an advantage because of the load network that is synthesized to give non-overlapping voltage and current, even if the device switching time is appreciable fractions of the ac cycle. One can also utilize the high output capacitance of the CMOS-transistor as part of the load network. The inverse class-D amplifier has an advantage of being differential which provides a higher voltage swing across the load, and thereby a higher load resistance and a lower current compared to the class-E. In contrast with conventional voltage-mode class-D amplifiers, the inverse class-D features zero voltage switching which eliminates the output capacitance discharge loss. This output capacitance is also utilized as part of the resonance filter in the load network. No previous work of others that uses the inverse class-D amplifier in a similar configuration (RF, CMOS) was discovered. It was found that the inverse class-D amplifier was the best suited for this application. The load resistance of the class-E amplifier became too low compared to the parasitic losses to achieve the design goals. The ground inductance was also totally destructive for the class-E waveforms because of the single-ended topology. Since the inverse class-D amplifier instantly showed much more promising behavior, no time was used trying to solve this problem. The resulting inverse class-D amplifier design has a peak efficiency of 51%, an output power of 30.04dBm. The gain is 25dB for an output power of 28dBm, but sadly it decreases below the design goal to 20.06dB at the point where Pout=30dBm and PAE=50%. ACKNOWLEDGEMENT I would like to give great thanks to Oddgeir Fikstvedt and Morten Olavsbråten for invaluable support during this time, and for making this thesis possible. I would also like to give great thanks Trond Ytterdal for his help with Cadence, and to Tore Barlindhaug for help with some fatal last minute Cadence problems.</p>
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Ho, Ka Wai. "A 1-V CMOS power amplifier for Bluetooth applications /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20HO.
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An, Kyu Hwan. "CMOS RF power amplifiers for mobile wireless communications." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31717.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.<br>Committee Chair: Laskar, Joy; Committee Member: Cressler, John; Committee Member: Kohl, Paul; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanouil. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Choi, Kiyong. "Parasitic-aware design and optimization of CMOS RF power amplifier /." Thesis, Connect to this title online; UW restricted, 2003. http://hdl.handle.net/1773/6078.
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Kim, Hyun-Woong. "CMOS RF transmitter front-end module for high-power mobile applications." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/47592.
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With the explosive growth of the wireless market, the demand for low-cost and highly-integrated radio frequency (RF) transceiver has been increased. Keeping up with this trend, complimentary metal-oxide-semiconductor (CMOS) has been spotlighted by virtue of its superior characteristics. However, there are challenges in achieving this goal, especially designing the transmitter portion. The objective of this research is to demonstrate the feasibility of fully integrated CMOS transmitter module which includes power amplifier (PA) and transmit/receive (T/R) switch by compensating for the intrinsic drawbacks of CMOS technology.
As an effort to overcome the challenges, the high-power handling T/R switches are introduced as the first part of this dissertation. The proposed differential switch topology and feed-forward capacitor helps reducing the voltage stress over the switch devices, enabling a linear power transmission. With the high-power T/R switches, a new transmitter front-end topology - differential PA and T/R switch topology with the multi-section PA output matching network - is also proposed. The multi-stage PA output matching network assists to relieve the voltage stress over the switch device even more, by providing a low switch operating impedance. By analyzing the power performance and efficiency of entire transmitter module, design methodology for the high-power handling and efficient transmitter module is established. Finally, the research in this dissertation provides low-cost, high-power handling, and efficient CMOS RF transmitter module for wireless applications.
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Gilasgar, Mitra. "Reconfigurable high efficiency class-F power amplifier using CMOS-MEMS technology." Doctoral thesis, Universitat Politècnica de Catalunya, 2017. http://hdl.handle.net/10803/460685.
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The increasing demand for wireless products to be part of our daily lives brings the need for longer battery lifetime, smaller size and lower cost. To increase battery lifetime, high efficiency power amplifiers (PAs) are needed; To make them smaller, integration or reconfiguration is aimed and to reach lower costs, technologies such as CMOS are final goals. However integration of high efficiency PA in CMOS is challenging due to the technology limitations which restricts the achievable output power and efficiency of the PA. In order to bring solutions for the above-mentioned requirements, in this thesis novel reconfigurable class-F PAs, frequency-reconfiguration, CMOS integration, impedance-reconfiguration and CMOS-MEMS implementation are addressed.
Starting with a single frequency operation, a novel class-F PA for mobile applications is proposed in which with a proper harmonic tuning structure the need for extra filtering sections is eliminated, achieving an excellent harmonic-suppression level. This topology uses transmission lines and is developed to cover multiple frequency bands for purpose of global coverage with aim of size reduction. Three novel frequency reconfigurable PAs are proposed using MEMS and semiconductor switches to accomplish class-F operation at two frequencies. The main novelty of this structure is that the reconfiguration is done not only at fundamental frequency but also at harmonics with reduced number of tuning elements. Moreover, by proper placement of the switches in the stubs, the maximum voltages over the switches are minimized. The proposed structure overcomes the narrow band performance of class-F, giving an efficiency more than 60% over a 225 MHz and 175 MHz bandwidth at 900 MHz and 1800 MHz respectively. Measurement results showed high performance at both frequency bands giving 69.5% and 57.9% PAE at 900 MHz and 1800 MHz respectively.
A novel CMOS class-F PA is proposed that controls up to the 3rd harmonic and can adapt to load variations due to the effect of the human body on mobile phones. It enables the integration of the PA with other devices in a single chip leading to better matching, higher performance, lower cost and smaller size. In addition, it achieves load impedance reconfigurability by using impedance tuner in its output network and by proper tuning of the network, effects of load variation on the performance are compensated. Two designs at 2.4 GHz have been done using either MOS varactors or MEMS variable capacitors as tuning devices. The design using MOS varactors show a maximum measured values of 26% PAE and 19.2 dBm output power for 50 load. For loads other than 50 ohm an improvement of 15% for PAE and 4.4 dB for output power is obtained in comparison to non-tuned one. The second design is done using MEMS variable capacitors integrated in CMOS technology through a mask-less post-processing technique. Simulations results for 50 ohm load show a peak PAE of 32.8% while delivering 18.2 dBm output power.<br>La creixent demanda de productes sense fils en la nostra vida diària requereix dispositius de menor grandària, menor cost i amb una gran autonomia. Per reduir la mida i augmentar l'autonomia és necessari utilitzar sistemes integrats multiestàndard o reconfigurables, amb amplificadors de RF d'alta eficiència, mentre que per reduir el cost, és preferible utilitzar tecnologies econòmiques com CMOS. No obstant això, la integració en CMOS d'amplificadors de radiofreqüència, i en especial, d'alta eficiència, és un repte a causa de les limitacions de la tecnologia que restringeixen la potència de sortida realitzable i l'eficiència de l'amplificador. En aquesta tesi es tracten els diferents reptes anteriorment esmentats, proposant una nova topologia d'amplificador classe-F amb reconfiguració de freqüència, i proposant la integració d'un amplificador classe-F que s¿adapta a impedància de càrrega variable, implementat en CMOS i CMOS-MEMS. Inicialment en la tesi es proposa una topologia d'amplificador classe-F en què, gràcies a una estructura adequada a la xarxa d'adaptació, s¿elimina la necessitat de filtrat extra, aconseguint un nivell de rebuig d'harmònics excel·lent. La topologia proposada utilitza línies de transmissió i s'ha desenvolupat per dues bandes diferents, amb el disseny orientat a implementar un sistema reconfigurable. S'han aconseguit PAE de l'ordre del 80 % amb potències properes a 10 W. Un cop descrita i analitzada la topologia, s'han proposat tres amplificadors reconfigurables per doble banda freqüencial. Per a la reconfiguració s'han utilitzat MEMS i commutadors basats en semiconductors. L'estructura proposada permet la reconfiguració no només en la freqüència fonamental sinó també en els harmònics, però mantenint un nombre reduït d'elements d'ajust. A més, gràcies a l'adequada col·locació dels commutadors en les línies de transmissió, s'ha minimitzat la tensió màxima en els mateixos. Així mateix, l'estructura proposada evita la característica de banda estreta a classe-F, proporcionant una eficiència superior al 60% en unes amplades de banda de 225 MHz i de 175 MHz, per a les banda de 900 MHz i 1800 MHz respectivament. En aquestes bandes, la PAE màxima mesurada és del 69,5% i del 57,9% respectivament. Finalment, s'ha proposat un amplificador integrat en CMOS, classe-F amb control fins al tercer harmònic. L'amplificador proposat incorpora un sintonitzador a la sortida, podent així adaptar-se a variacions d'impedància de càrrega, típiques en dispositius sense fil (WLAN), degudes a l'efecte del cos humà sobre l'antena. La implementació en CMOS permet la integració de l'amplificador de potència amb altres dispositius en un únic xip, donant lloc a una millor adaptació, millor rendiment, menor cost i menor grandària del sistema. A més, gràcies a l'adaptació a les variacions de la impedància de càrrega, permet mantenir el rendiment en diferents rangs d'operació. S'han realitzat dos dissenys de l'amplificador a 2,4 GHz, un basat en varactors MOS i un altre en condensadors variables MEMS. El disseny que utilitza varactors MOS mostra una PAE màxima del 26% i una potència de 19,2 dBm per a càrrega adaptada 50 ohm. Per altres càrregues, gràcies a l'adaptació d'impedància, s'obté una millora de PAE del 15% i de 4,4 dB en potència de sortida. El disseny utilitzant condensadors MEMS s'integra en CMOS gràcies a post-processat sense màscares addicionals. Els resultats de simulació per a 50 ohm mostren una PAE del 32,8% per 18,2 dBm de potència de sortida
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Song, Ping. "A 1.0-V CMOS class-E power amplifier for bluetooth applications /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20SONG.
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Zhao, Chao. "Design fully-integrated dual-band two-stage class-E CMOS PA." Thesis, University of North Texas, 2015. https://digital.library.unt.edu/ark:/67531/metadc804916/.
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In retrospect we can see that from the last century, wireless electronic technology has been in a rapid state of development. With the popularity of wireless communication, the power amplifier demand is rising. In general, magnitude, maximum noise figure, minimum noise figure, efficiency, and output power are important indicators of the amplifier. The IC industry is exploring how to reduce the additional cost and improve the high-frequency performance. Therefore, designing a strong adaptability and high cost performance of the PA has become a priority. As these technologies advance, the power amplifiers need to have better integration, lower cost, and lower power dissipation. Also, some special requirements are being asked in some areas, such as multi-mode and multi-band. In general, people have to use several power amplifiers parallel to frame a multifunction chip. Each of them working at different frequencies of interest has to have separate matching network, design, and area; also, the diversity amplifier prices will increase with the number of amplifiers, and its cost is also changed. In this thesis, because Class E power amplifier has lower power dissipation, 100% ideal efficiency, simple circuit structure, and strong applicability, the Class E is used as power amplifier in main stage. Moreover, in order to decrease input power and increase output power, the class A power amplifier is used as driver stage. It can use very small amount of power to provide a larger power. Moreover, we use a switched variable inductor and capacitor to constitute a dual band matching network which can let the PA work at more than one frequency. In fact, we design a Class A PA which is as a driver stage. Then, when we support 1 dBm input power, the driver stage can have 8 dBm output power. Also the output will be the input power for the main stage. When the Class E PA get 8dBm input power, it will export a 15dBm output power. Because the dual band matching network, the PA can work at 2.2 GHz and 2.6 GHz; also, the efficiency is 48% and 51%, and the both gains are 13 dB. In the future, in order to further improve the performance of the power amplifier and better multi-frequencies, more new designs with new structures should be investigated. Moreover, we need further research about design theory. In fact multi-frequencies power amplifier has a great potential in real application. It based on its special structure and design parameters.
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Chang, Shan-En, and 張善恩. "CMOS Wideband Power Amplifier and Pulse Modulated Power Amplifier." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/rm39v7.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>As the development of communication systems, the industry continues to request more frequency bands. Therefore, the FCC releases 900 MHz, 2.4 GHz and 5.8 GHz bands as the industrial scientific medical band（ISM Band）for openly use. In order to simultaneously transmitting signals in multiple frequency bands, there should be a broadband power amplifier in a transmitter.
In the communication systems, there are variety of modulation techniques. The radio frequency power amplifier is an important component of the transmitter and plays a crucial role in communication systems. It dominates about 60% to 90% of the energy consumptions in the RF transceiver. Therefore, the power-added efficiency, affecting the degree of the power consumption, is distinctly important.
This thesis presents the CMOS power amplifiers that are implemented in 0.13 μm CMOS technology. In order to overcome CMOS transistors’ low breakdown voltage and improve the power and efficiency, this thesis adopts the stacked transistors to design power amplifier.
The first wideband PA is one stage with, high power and high efficiency for ISM band. Circuit architecture uses four-stacked transistors and network synthesis broadband matching. From the simulation, this PA achieves a 1-dB bandwidth of 2 to 6 GHz and 3-dB bandwidth of 1.6 to 6.3 GHz. In the 1-dB bandwidth, this PA achieves P1dB of 28.1 to 29.1 dBm and PAE of 35.27 to 48.66 %；Psat of 30.9 to 31.9 dBm and maximum PAE of 46.61 to 50.15 %. The CMOS PA is able to cover ISM Band 2.4 GHz（2400 ~ 2500 MHz）and 5.8 GHz（5725 ~ 5875 MHz）.
The second part of PA is CMOS pulse modulation power amplifier with CMOS pulse modulator, which uses on-off keying technology, and two-stage high efficiency power amplifier. From the simulation, this OOK modulator achieves S11 and S22, less than - 10 dB, with 590 MHz bandwidth. The 3-dB bandwidth of S21 is 500 MHz（1700 ~ 2200 MHz）. This pulse modulated power amplifier achieves a power gain of 34.0, output power of 28.0 dBm and PAE of 58.9 % when frequency is 1.9 GHz and input power is – 6 dBm.
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Guo, Chuen-Zhu, and 郭純助. "2.4GHz CMOS Linearized Power Amplifier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/77729151354106649363.
Full textAbstract:
碩士<br>國立成功大學<br>微電子工程研究所碩博士班<br>91<br>This thesis presents a 2.4GHz ISM-band CMOS linearized power amplifier. Useing two frames of linearization to improve linearity of power amplifier. This thesis consists of two part. Part I introduced the theory and technique of design about power amplifier. Part II are examples of linearized circuit, which will use the frames of linearized bias circuit and auxiliary transistor to compensate nonlinear factors to improve linearity of power amplifier.
In the frames of linearized bias circuit, the linearized bias circuit can increase the voltage of gate form 0.5V to 0.68V. The designed results are 12.5dB in power gain, 28% in PAE, P1dB rising up from 0.7dBm to 12.9dBm, and IMD of 2-oder＆3-order harmonic to improve linearity above 5dB. In the frames of auxiliary transistor to compensate nonlinear factors, the designed results are 20.7dB in power gain, 26% in PAE, P1dB rising up from 0.43dBm to 14.035dBm, and IMD of 2-oder＆3-order harmonic to improve linearity above 6dB~24dB. The improving linearity of circuit is conspicuous.
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Chien, Yuan-Te, and 簡元德. "Research of CMOS Class E Power Amplifier, Adaptive Bias Power Amplifier and Transformer Combined Power Amplifier." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/57723754614600631078.
Full textAbstract:
碩士<br>國立臺灣大學<br>電信工程學研究所<br>100<br>The growth in wireless communication has strong demands in integrated solution to have faster transmission speed, more distance, and more reliable transmission. Power amplifier is one of the bottlenecks. Traditionally, Ⅲ-Ⅴ high electron mobility transistor, ex. GaAs has the high output power and high power added efficiency. It has certain restrictions and difficulties about using complementary metal-oxide semiconductor to design the power amplifiers. For the reason of system integration and small area to cost down, the fabrication of power amplifiers using complementary metal-oxide semiconductor arises attention gradually and more and more researchers study relevant topics.
In this thesis, we design two circuits in Class E Power Amplifier operation using 180nm CMOS processes. The first power amplifier achieves 8-dB small signal gain, 40% PAE, and 15 dBm output saturation power at 5.8GHz. The second power amplifier achieves 20-dB small signal gain, 50% PAE, and 20 dBm output saturation power at 2.4GHz. The third circuit is Adaptive Bias Power Amplifier using 180nm CMOS processes. The fourth circuit is Transformer Combine Power Amplifier using 180nm CMOS processes.
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Lin, Jhen-Hong, and 林振宏. "Design of CMOS Doherty Power Amplifier." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/gmvnxx.
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碩士<br>國立中山大學<br>通訊工程研究所<br>102<br>This thesis presents a fully integrated transformer-based Doherty power amplifier in a standard 90 nm CMOS process. Doherty architecture has been proposed to enhancement the average efficiency of the transmitter, and improve efficiency under the back-off. There are two parts of this thesis, the first part is to introduce a traditional linearly power amplifier, and realize a fully integrated class A power amplifier at 2.4 GHz. The cascode structure is used in the power cells since the power amplifier is a fully differential design, a balun is utilized to convert between single-ended and differential signals, and to serve as an impedance matching network. The second part is to realize a fully integrated 2.4 GHz Doherty power amplifier. A main amplifier and an auxiliary amplifier are integrated to have a combined output power. A asymmetrical series combining transformer is used to achieve uneven Doherty operation. The Doherty architecture demonstrates efficiency enhancement under back-off, which is important for high peak-to-average-power-ratio communication systems.
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Tsai, Chin-Wei, and 蔡智偉. "Development of RF CMOS Power Amplifier." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/r8aca6.
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碩士<br>國立臺北科技大學<br>自動化科技研究所<br>94<br>This thesis presents the development of RF CMOS power amplifier which is implemented by UMC CMOS 0.18-um 1P6M process. A class E power amplifier and a cascode power amplifier are designed to be used in bluetooth system and wireless sensor network system, respectively. In the matching network design, the input matching network is designed for maximum gain transducer by conjugate matching and the output matching is designed for maximum power transducer by load-pull matching.
The simulation results of class E power amplifier whose input matching network and output matching network are on the chip and off the chip respectively are output power of 21.214dBm, PAE of 37.765％ and power gain of 17.214dB at 2.4GHz. And the cascade power amplifier which is a fully chip realized an overall PAE of 20% with output power of 3.583dBm and had power gain of 7.583dB at 2.4GHz.
In general, the effect of layout is not considered in the simulation of circuit level. This thesis considers the parasitic effect after layout to obtain more accurate results of simulation.
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Chang, Che-Kun, and 張哲昆. "77~110GHz 40nm-CMOS Power Amplifier." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/ev83k8.
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碩士<br>國立交通大學<br>電子研究所<br>107<br>In wireless communication system, low noise amplifier and power amplifier is the most front end and the most back end circuits. There are different design cosideration but both of them are important. Output power of power amplifier decide driving ability of amplifier. Low noise amplifier impact SNR of all system. In CMOS power amplifier, low output power of transistor and loss of passive circuit make output power insufficient. To overcome these issues, this thesis provide a 77~110GHz CMOS power amplifier. By in phase power combiner to combine eight way output power of transistor make output power 9dB larger than only one transistor and it can lower the length of power combiner greatly by capacitively load than quarter wave impedance transform to minimize the loss. Entire loss of all output network is only 2.5dB for simulation. Output power will be 6.5dB bigger than only one transistor.
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Tseng-Hsin, Chiu. "A CMOS 2.4GHz Class-E Power Amplifier." 2003. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611295360.
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Wu, Ja-Dai, and 吳家岱. "RF CMOS Class-E Power Amplifier Design." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/02020170093738417342.
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碩士<br>國立交通大學<br>電子工程系所<br>95<br>An on-chip CMOS Class-E Power Amplifier (PA) implemented in 0.13-�慆 CMOS technology is presented. The Class-E PA includes a Class-F driver and replaces a large RF choke with a small finite dc-feed inductor for on-chip integration. The proposed Class-E PA achieves power added efficiency (PAE) of 48.4 % while delivering 21 dBm output power with the input driving power of -3 dBm at 2.5 GHz. In the design band, 2.3GHz~2.7GHz, PAE is still above 44%. In order to improve the simulation time of RF/Baseband co-simulation the behavior model of proposed PA is presented. The simulation time of RF/Baseband co-simulation can be reduced about 93% by the proposed behavior model.
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Wang, Chih-Cheng, and 王志誠. "24 GHz Transformer Based CMOS Power Amplifier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/71322254702245505714.
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碩士<br>元智大學<br>通訊工程學系<br>97<br>This thesis presents a 24 GHz full-integrated power amplifier (PA) which designed and fabricated in the 0.18-μm 1P6M standard CMOS technology. This power amplifier is a 2-stage design using cascode configuration with the broadside transformers. The simulation shows the PA achieves the maximum output power of 20.3 dBm and OP1dB of 16.45 dBm, a power added efficiency (PAE) of 15.3%, and a linear gain of 16.5 dB when VDD is biased at 3.0 V. The measured results shows the maximum output power of 16.4 dBm and OP1dB of 12.68 dBm, a power added efficiency (PAE) of 5.3%, and a linear gain of 5.6 dB when VDD is biased at 3.0 V. The chip size is only 0.59 x 0.47 mm2.
Finally, the differences between simulations and measurement results are addressed with some possible improvement directions.
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Wang, Hsiao-Kang, and 王孝綱. "CMOS Power Amplifier with Wireless Communication Applications." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/79161753158597801530.
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碩士<br>元智大學<br>通訊工程學系<br>95<br>This thesis utilizes TSMC CMOS 0.18 um process to implement radio frequency power amplifier applying in 2.4GHz Bluetooth and WLAN 802.11b/g systems. The circuit design methods for overcoming the low breakdown voltages and the hot carrier phenomena at high power operation in the CMOS devices are presented to achieve the higher output power levels. Furthermore the linear power amplifier design using a linearizer for 802.11b/g applications is demonstrated as well for reducing the third order nonlinear term and improving the 1dB gain compression point. Finally some design difficulties with the CMOS processes including the simulation/measurement discrepancy and the layout problem are addressed.
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Oliveira, Daniel José Azevedo. "CMOS-RF power amplifier for wireless communications." Master's thesis, 2009. http://hdl.handle.net/10216/66786.
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Chiu, Tseng-Hsin, and 邱曾鑫. "A CMOS 2.4GHz Class-E Power Amplifier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/22636927368361578196.
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碩士<br>元智大學<br>電機工程學系<br>91<br>For the last few years, the personal wireless communications system has developed intensively the SOC (system on chip) technologies, and it is becoming clearer that the remarkable amount of growth in the SOC system for the personal wireless communications applications. Now, the overwhelming majority of part element of communication system is implemented in CMOS technology. For this reason, to integrate the whole personal communications system in a chip is very important, and the power amplifier is the key in the integration design. However, the design and implementation a CMOS power amplifier is very difficult due to the characteristics of CMOS. Presently, the RF power amplifiers are mainly implemented in GaAs, HBT, LDMOS, and BiCMOS technologies, but for the SOC, the design is to need for a COMS RF power amplifier. This design is used with a class-E single-end switching power amplifier, which can achieve high efficiencies and low power consumptions.
The power amplifier was designed for the wireless LAN IEEE 802.11b Standard. The frequency of the PA used in Industrial Scientific and Medical (ISM) band at 2.45GHz (in the IEEE802.11b standard, the frequency range is from 2.4GHz to 2.483GHz), and the output power is greater than 23dBm. The PA design utilized high-efficiency Class-E amplifier structure, and the structure used a single-end model in a 0.25um CMOS process. The overall simulation used ADS (Advance design system) tool. To do design The post-layout simulations indicated a PAE of 50.6% in the PA, and which could generate 24.1dBm of output power into a 50Ω load.
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Oliveira, Daniel José Azevedo. "CMOS-RF power amplifier for wireless communications." Dissertação, 2009. http://hdl.handle.net/10216/66786.
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LIN, YUE-SHIANG, and 林岳翔. "Study of Millimeter-Wave CMOS Low-Noise Amplifier and Power Amplifier." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/29n2r4.
Full textAbstract:
碩士<br>國立暨南國際大學<br>電機工程學系<br>105<br>The purpose of this thesis is to design and implement the W-band low-noise amplifiers, W-band of power amplifier which operated in W-band by
CMOS(Complementary Metal-Oxide-Semiconductor) The thesis can be divided into two parts：
In the first part, a 77~81 GHz low noise amplifier is designed for W-band system. In order to achieve the highest values, we design a three stage cascade amplifier. In the three stages we use one cascode circuit which can increase the signal intensity in the low power. Then we use “T-matching” technique at both input and output term. Moreover, we add transmission line at the source of up of NMOS with one PMOS and to obtain flat high gain (S21), low noise figure and better “ S-parameter” performances. Finally, we put bypass capacitances at the “VDD” and “VGS” term to make our circuit more stable.
The second part is on the design and implement of a high added efficiency power amplifier for 94GHz applications in 90nm CMOS technology. In the circuit architecture, which is to achieve this circuit architecture with four stage of the series. The first stage with casecode and two, four stage with device common-source topology.Which have better linearity and high power output. The third stage using Special Y-shaped power divider/combiner architecture which combines two way output power, and uses casecode architecture to enhance the overall circuit gain. The fourth stage using Dual Y-shaped power divider using architecture with four way output power. Achieve output power and power added efficiency improvements. The measured results show that 3-dB bandwidth of this power amplifier is 10GHz(77~86GHz), gain (S21) is 22.02dB, saturation output power (Psat) is 13.37dBm, max power added efficiency (peak PAE) is 15.12%, total power consumption is 120.65mW and the chip
area (including test pads) is 1*0.99764mm2. This circuit performs well in power added efficiency (PAE) and saturated output power.
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Lu, Chun-Wei, and 盧鈞瑋. "Design of 2.4GHz CMOS linearized Power Amplifier with power control." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/51544684000610690090.
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碩士<br>長庚大學<br>電子工程研究所<br>93<br>Today’s power amplifiers are implemented in GaAs, HBT, LDMOS, and BiCMOS technologies. However, more and more communication system is fabricated in CMOS technology. For this reason, a single chip transceiver includes an integrated CMOS power amplifier. In this work, design and implementation of a power amplifier are described.
This paper presents a 2.4GHz CMOS linearized power amplifier with variable output power fabricated in TSMC 0.18μm 1P6M CMOS process. The PA has linear power gain of 17.54dB, output P1dB of 13.64dBm and power added efficiency (PAE) of 32.86%, and linearized with multi-gate auxiliary transistor. And the controllable output power can reduce the effect to human causing by the EM wave.
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Nai, JI-Kang, and 能繼康. "Research of CMOS RF Power Amplifier with Power Efficiency Improvement." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/09750270580288803579.
Full textAbstract:
碩士<br>國立臺灣大學<br>電信工程學研究所<br>104<br>In this thesis, the theory of switchmode power amplifier (PA) is implemented in the design of CMOS RF power amplifier. The aim of the design is to improve the efficiency of power amplifier while keeping high out output power.
A 5 GHz class-F-1 mode power amplifier based on transformer using the TSMC 180-nm CMOS process is presented first. In this design, the conventional output matching networks of LC-tank are replaced by the transformer with a shunt capacitor to increase the power density. The measured result shows 13.2-dB small signal gain, and 25.4-dBm saturation power (Psat) and 41% peak power added efficiency (PAE). While the output power at 1-dB compression point (OP1dB) is 24.6 dBm, and the PAE at OP1dB is 35%.
Then a power amplifier works from 2.8 to 6 GHz is also designed using 180-nm CMOS process. The output matching network of the proposed PA achieves wideband fundamental matching and 2nd and 3rd harmonic impedance matching to improve the efficiency simultaneously. The measured result shows 10.4-to-13.4-dB small signal gain, and 20.8-to-22.1-dBm Psat, and 37-44% peak PAE. In the meanwhile the OP1dB is 20.3-21.4 dBm, and the PAE at OP1dB is 32-38%.
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Lai, Kuan-Ting, and 賴冠婷. "Millimeter-Wave CMOS and GaAs Power Amplifier Design." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/952xfv.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>102<br>The thesis will propose three circuits which are designed in CMOS and GaAs technology, including a 90nm 77 GHz narrow band, a 65nm 77-110 GHz wide band Ｐower Amplifier and a 0.1 um GaAs 77 GHz narrowband power amplifier.
The 90nm CMOS 77 GHz narrow band amplifier has four stages with 1:2:4:8 configuration and a eight-way in-phased combiner at the output stage. There are three stages with 1:2:4 configuration and a four-way in-phased combiner at the output stage in the 65nm CMOS 77-110 GHz wideband amplifier. The 0.1 um GaAs 77 GHz narrow band power amplifier has three stages with 1:2:4 configuration. The input DC-blocking is used by a couple line instead of a capacitance, and the output stage is used a four-way in-phased combiner.
The design approach and the behavior of these circuits will be well discussed and clearly illustrated.
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Chun-Lin, Ko, and 柯鈞琳. "Design and Implementation of CMOS RF Power Amplifier." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/82299907393575645342.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>88<br>In last few years, the remarkable growth in the personal wireless communications has motivated great interests in monolithic CMOS transceivers. Therefore, to implement a high efficiency power amplifier in a standard CMOS technology is one of the important challenges in the transceiver integration. In this thesis, the design and implementation of a power amplifier are described.
However, the implementation of CMOS power amplifiers suffers from many disadvantages of the intrinsic CMOS characteristics. The handicaps include insufficiency driving capability, low breakdown voltage, large parasitic capacitors, and lossy substrate. Therefore, we have to introduce a different approach from the standard way, which is used to design GaAs or bipolar power amplifiers.
We have investigated a switching class E approach, which can achieve higher efficiency than traditional classification of power amplifiers. A fully differential topology and the composite switch technique are presented to alleviate the problems of CMOS. A facile power control node is also created for the linearization system. In addition, a low insertion loss and broad bandwidth lumped element hybrid is implemented to convert the signal between signal-ended and differential. The thesis is successful to design and implement a 1-GHz, 162-mW power amplifier in TSMC 0.35-mm CMOS technology. The simulation and measurement results are also detailed in this thesis.
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LEE, NENG CHIA, and 李能嘉. "RF CMOS power amplifier Integrated with MEMS components." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/79890756757873169684.
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碩士<br>國立臺北科技大學<br>機電整合研究所<br>92<br>With the development of RF communication technology, wireless communication devices need being much more precise and efficient in circuit design. Conventional GaAs based devices are high efficiency, low loss and low noise in high frequency and commonly applied in RF circuit. The HBT RF power amplifier could deliver power 29dBm and PAE 45%, is adequate for high power and long-distance wireless communication system. However, for low power and low move rate communication system, the CMOS technology will effectively reduce cost and exceed GaAs in integration. Fortunately, the progress of "Nano CMOS" technology enhances transistor characteristics and "RF-MEMs" technology ameliorate lumped element characteristics therefore current commercial developed power amplifiers have built in output / input matching network and include Peak-detector inside the same chip. The circuit proposed in this thesis integrating MEMs components with 2.4GHz and 5.2GHz RF CMOS power amplifier, were fabricated by standard TSMC 0.25 1P5M and UMC 0.18 1P6M CMOS process technology. The RF power amplifiers contain the power control, the peak detector and the impedance tuner to provide excursion compensation of temperature, process and load impedance. This circuit is simulated and analysed with Agilent's ADS, implemented layout with Springsoft's Laker, verified with Mentor's Calibre. This RF CMOS Power amplifier could deliver power 20dBm, PAE> 35% and power control technology could make delivered power change range from 20mW to 91mW (11dBm~19.6dBm). The impedance tuner has adjustable loading range 14<Re[ZL]<146 and -57<Im[ZL]<122. The measurement adopts on-wafer machines and FR4-PCB test boards. The whole chip area containing bond-wire pads is less than 1.1x1.1 mm2.
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Syu, Jin-Yan, and 徐金言. "CMOS Supply Modulator for Envelope Tracking Power Amplifier." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/42168061564452468619.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>104<br>Nowadays, handheld devices are very popular, such as smartphone and Tablet.Because the handset devices use battery as the power source, customers are concerned about the battery life. Power amplifiers consume a significant portion of the total power of the RF Transmitters of the handheld devices. If power amplifiers can’t use power efficiently, the overall efficiency of RF Transmitters will become very poor.
Envelope tracking is one of the techniques to improve the efficiency of the power amplifiers. Unlike a fixed-supply-voltage power amplifier, envelope tracking is a
technique which the supply voltage of the power amplifier is dynamically adjusted by the supply modulator to track the envelope of the RF signal.
In this thesis, the supply modulator includes two parts. One is the switching DC-DC converter which provides low frequency content of the envelope waveform, and the other is the linear amplifier which provides high frequency content of the envelope waveform. The supply modulator applied to envelope tracking not only has high bandwidth, but also has high slew rate. If we request the linear amplifier has both high bandwidth and high slew rate, it will consume a lot of power. This thesis proposes the circuits which can improve the slew rate of the linear amplifier. When needing high slew rate, the circuits can provide another charging or discharging path. With the method, the linear amplifier can reduce the power consumption.
The chip is fabricated in a 0.13 μm CMOS with LDMOS process, and its size is 1.72*1.28 mm^2. The tracking signals are 1/5/10/15/20 MHz sine wave and 20 MHz LTE
envelope. The output voltage range and the efficiency are 0.5~3.6 V and 77.3 %, respectively.
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Yang, Li-Yuan. "Doherty CMOS RF Power Amplifier for Wireless Applications." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2702200815212200.
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Chi, Ping-Sung, and 紀秉松. "Research of HEMT and CMOS Microwave Power Amplifier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/54246413391705305002.
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碩士<br>臺灣大學<br>電信工程學研究所<br>98<br>The goal of this thesis is to design and implement four power amplifiers, two in pHEMT and two in CMOS processes, including two X-band high efficiency power amplifiers, a 24 GHz balanced amplifier, and a K-band power amplifier.
The first part of the thesis presents a harmonic tuned power amplifier at X-band. Adding harmonic loading circuits at the output and the input of the transistor can improve the overall output power and power added efficiency of the power amplifier. The circuit is designed in 0.15-μm low-noise pHEMT technology and has a measured maximum PAE of 48.5% at 10.5 GHz. An abrupt flush of the drain current is obtained in measuring this amplifier, and the measurement phenomenon and mechanism of the abrupt flush of the drain current due to reverse gate current are also investigated in this part.
The second part focuses on the design of high power amplifier at 24 GHz using 0.15-μm power pHEMT technology. Two 8 finger 800-μm devices are combined in a current method in the two-stage PA, and then using the balanced configuration combines two same two-stage PAs again. Considering the process variation of small capacitors in the circuit design, re-simulation results show good agreement with measurements. The re-design results indicate that the odd mode oscillation is illuminated and process variation only has less effect on the circuit.
The third part shows an X-band power amplifier with the high PAE and the small chip size using 0.18-μm CMOS process. In order to obtain wide bandwidth at power and PAE performance, broadband output and input matching network are adopted in this power amplifier. From the measurements, the power amplifier obtained the best PAE of 25.7% and saturation output power of 23.8dBm at 9.5 GHz. Besides, this PA demonstrates the 1-dB power bandwidth from 7.8 to 11 GHz and the PAE insides this bandwidth all exceed 20%. To our knowledge, this is a power amplifier with the highest PAE, the smallest chip size to date in CMOS process at X-band.
The final part presents a K-bnad high power amplifier with the wide power bandwidth implemented by 0.13-μm CMOS technology. Broadband output power matching and broadband input conjugate matching lead to good power and PAE performances at the designed band. This PA achieves a measurement saturation output power of 18.6 dBm at 24 GHz with a power bandwidth of 6.5 GHz, and the PAE all exceeds 10% at this bandwidth. To our knowledge, this is a power amplifier with the widest power bandwidth and high saturation output power to date in CMOS process at K-band.
Index Terms—power amplifier (PA), X-band, K-band, pHEMT, CMOS, monolithic microwave integrated circuit (MMIC), high efficiency, high power, reverse gate current, wide power bandwidth.
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Hsu, Yu-Chung, and 許譽鐘. "Research on Linearization Technique for CMOS Power Amplifier." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/19111639359958109173.
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碩士<br>臺灣大學<br>電信工程學研究所<br>98<br>In this dissertation, a modified cold-FET pre-distortion linearizer is proposed to improve the linearity of the millimeter-wave CMOS power amplifiers. The previous reported cold-FET linearizer as applied to a 40 GHz power amplifier with a low-loss built-in linearizer in GaAs HEMT technology [6]. However, the effect of the linearizer is not good enough when we try to transplant the technique to 60 GHz using CMOS technology. Therefore, we investigate the operation detail of the linearizer and propose a modified linearizer by adding a delay line. Besides, a bias optimization method that can effectively guarantee the linearity of specific cascode device for power amplifier application is also presented.
A 60GHz cascode power amplifier with modified linearizer is then fabricated under 90-nm LP CMOS technology and fully characterized to enhance its linearity which demonstrated by its extremely well OP1dB. The measurement results of the power amplifier show a power-added-efficiency at OP1dB up to 14% while maintaining 15 dB small signal gain, 13.7 dBm OP1dB and 15.4 dBm Psat. It is the highest power-added-efficiency at OP1dB for millimeter-wave CMOS power amplifiers which ever been published.
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Jiao, Weishing, and 焦偉信. "Low-Power Two-Stage CMOS Operational Transconductance Amplifier." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/11329314256451004703.
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碩士<br>國立高雄海洋科技大學<br>微電子工程研究所<br>100<br>Two-stage operational transconductance amplifiers (OTA) operated in the ±1.5V power supply range were designed and fabricated using the TSMC 0.35um technology. Both NMOS and PMOS differential input topologies were designed and its circuit characteristics were compared and analyzed. HSPICE simulated results showed following characteristics for both NMOS and PMOS OTA circuits: Power consumption, 0.19mW, 0.28mW; Phase margin, 53°, 45°; Unity gain band width, 4.4MHz, 1.6MHz; Open loop gain, 76.6dB, 73.2dB; Input common mode range, ±1.3V, ±1.3V and Output swing, 2.64V, 2.57V, respectively.
To decrease mismatch (due to process variations) effect and reduce the offset voltage, the “Common Centroid" method with multi-finger structures were employed throughout the layout and floorplan. Moreover, both NMOS and PMOS devices were proper isolated with guard rings to avoid noise coupling effects.
On chip measurement show that despite basic NMOS OTA circuit functioned properly, there are still room for improvements. For example, when the close loop gain = 10 and the input signal large than 0.04V, some devices in the circuit were turned off. Furthermore, due to limitation of slew rate, the output signal started to show signs of distortion when the input signal large than 17KHz.
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Chu, Fang Hsien, and 朱芳賢. "The Design and Implementation of CMOS low noise amplifier and power amplifier." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/3264q2.
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Chen, He-Ming, and 陳和銘. "High-Power and High-Efficiency CMOS Power Amplifier With Ramping Circuit." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/xcewz8.
Full textAbstract:
碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>98<br>During the past year in the fast growing market in wireless communication component industry, using CMOS process enhance lowering of manufacturing cost has become the future trend for companies, CMOS power amplifiers performance is limited because of its low breakdown voltage between source and drain as well as low gate-oxide breakdown voltage, and high substrate loss.
The first part using cascode structure to alleviate the breakdown voltage problem and employs power combining technique to achieve impedance transformation on chip for the purpose of increasing the output power and efficiency, Based on the simulation results,the PA delivers power gain of 33 dB of 1dB compression point, and maximum output power of 33dBm and an associated 47.58% power added efficiency (PAE).
Another focus of this thesis is to design a Vramping circuit, the ramping circuit sets the PA’s control voltage to the level necessary to produce the desired output power level and burst transmission.
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Fu, Tzu-Chien, and 傅子謙. "5GHz Power Amplifier Using Silicon Technology and CMOS Logarithmic Power Detector." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/05657126266670861377.
Full textAbstract:
碩士<br>國立交通大學<br>電信工程研究所<br>104<br>This thesis consists of two parts, including silicon-based 5GHz power amplifiers and CMOS logarithmic power detectors.
In the first part, Dual-mode 5GHz power amplifiers implemented with TSMC 0.18-um SiGe BiCMOS and TSMC 0.18-um CMOS technology are presented. The efficiency enhancement is achieved by switching the operation modes. Furthermore, to overcome the effect of temperature variations on the performance of power amplifiers, a temperature insensitive PA bias circuit with digital control interface is proposed. The bias circuits are applied to 5GHz power amplifiers using TSMC 0.18-um SiGe BiCMOS and TSMC 0.18-um CMOS process, respectively.
The second part introduces a logarithmic power detector from its fundamental principle. Broadband logarithmic amplifiers for RF power detection are
implemented in TSMC 0.18-um CMOS,TSMC 0.18-um SiGe BiCMOS and
UMC 0.18-um CMOS, and their features are wide dynamic range and linear-in- decibel power detection.
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Huang, Guan-Jie, and 黃冠傑. "Research on CMOS Power Amplifier with Transformer Power Combining for WLAN System Applications and K-band Active Antenna Power Amplifier Using CMOS and IPD Process." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/48193187199374037384.
Full textAbstract:
碩士<br>國立臺灣大學<br>電信工程學研究所<br>105<br>In wireless communication system, when the microwave signal transmits in the air, the receiver could encounter the signal distortion which causes the decoding error due to the noise interference. Therefore, if we can strengthen the transmitting signal and make better signal-to-noise ratio (SNR) of the signal, we can improve the probability of correct decoding for the reason that how to make the power amplifier deliver more output power in wireless transmitter. Besides the high output power, the demand for high efficiency of the power amplifier in wireless communication system has increased because power amplifier consumes the most dc power in the transmitter. Therefore, the optimization of the efficiency becomes a key issue. Several new structures of power amplifier are proposed recently in order to achieve good linearity and efficiency.
In this thesis, two circuits are designed and implemented, which are respectively an active antenna integrated with adaptive-bias power amplifier and a high Psat power amplifier with transformer power combining. The former is implemented on 0.18-μm CMOS and IPD technology operated at 24 GHz while the latter is realized by 0.18-μm CMOS technology operated at 5.2-5.7 GHz.
In Chapter 2, a K-band active antenna integrated with CMOS adaptive-bias PA is proposed to improve the efficiency of the PA. This circuit includes a CMOS adaptive-bias PA and a dipole antenna; the power amplifier is realized by 0.18-µm CMOS technology and the antenna is implemented on IPD technology. The circuit design is extended version of [1]. The traditional transformer balun is selected as input bulun. And on-wafer near-field antenna measurement system using probe station is applied to the measurement of the radiation pattern of antenna under test.
In Chapter 3, a high Psat power amplifier with transformer power combining is designed, and how to make the lower loss of power combiner to achieve high Psat is our focus of discussion. In this thesis, we would discuss why we select transformer as our power combiner and the analysis of how the parameters affect the characteristic of the transformer to optimize the efficiency of the transformer. In the measurement, we set up the measurement as cool as possible because the performance of the circuit will be worse as the temperature increases. And we implement the second version of layout for more heat dissipation to make better power performance.
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Zhuang, Wen-Te, and 莊文德. "A Class E CMOS Power Amplifier for Bluetooth Applications." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/18561983004382088415.
Full textAbstract:
碩士<br>逢甲大學<br>電子工程所<br>92<br>With recent advance in CMOS process, many essential building blocks for wireless transceivers, such as low-noise amplifier (LNA), mixer, frequency synthesizer, channel selection filter and digital-to-analog converter, have been demonstrated using CMOS technology. However, not much work has been done or reported a CMOS power amplifier (PA) in particular Class E at 2.4GHz.
In this thesis, two power amplifiers are designed for Bluetooth application. Each power amplifier includes driver and power stages. The first circuit, its power stage has been implemented in a standard 0.25�慆 CMOS technology and shown to deliver 16dBm output power to 50Ω load with 20% power added efficiency(PAE) from a 2.5V supply. The second circuit has been simulated in a standard 0.18�慆 CMOS technology. It is a controllable driver stage power amplifier. The driver stage was designed to controllable power gain. Simulation results are shown to deliver 20dBm output power to 50Ω load with 20% PAE. The output power can be controlled from 9dBm to 20dBm.
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Chen, Ting-Jui, and 陳廷睿. "CMOS RF Power Amplifier with Adaptive Bias Linearization Technology." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/6qktjk.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>With increasing popularity of the mobile communication system which evolves from the second generation, third generation to the fourth generation, smartphones have become one of the must-have Electronics products. Since the Long Term Evolution (LTE) technology has been proposed by the 3rd Generation Partnership Project (3GPP), the LTE standard covers a range of many different bands. According to the different LTE bands in the different countries, and in response to the increase of the LTE data rates and the increase of the bandwidth, the challenge of the radio-frequency power amplifier (RF PA) design in the mobile communication devices is high efficiency, high linearity, and support for multi-mode and multi-band.
This thesis proposed a way to improve the linearity of the RF PAs which are implemented in Complementary Metal-Oxide-Semiconductor (CMOS) technology. The stacked-FET structure PA is used in this work and the linearity of the RF PA is improved by the adaptive bias circuit which the gate bias voltage of the transistor can be changed according to different input signal level. The first part implemented a single-stage RF PA using 0.13 m CMOS technology and the second part implemented a two-stage RF PA using 0.13 m CMOS technology.
The single-stage RF PA is implemented in 0.13 m CMOS technology, including the adaptive bias circuit. The Chip size is 0.98 × 1.23 mm2. The PA was tested under a continuous-wave (CW) input at 1.95 GHz and a supply voltage of 4.8 V. The measured small-signal gain is 16.09 dB, At the 1-dB compression point, the output power (P1dB) is 21.84 dBm with a 19.41 % power-added efficiency (PAE). A maximum PAE is 20.96 % with a 23.51 dBm output power.
The two-stage RF PA is implemented in 0.13 m CMOS technology, including the adaptive bias circuit, the gain compensation circuit and the improved output matching network. The Chip size is 0.99 × 1.25 mm2. The PA was simulated under a CW input at 1.95 GHz and a supply voltage of 4.8 V. The simulated small-signal gain is 32.69 dB. The P1dB is 28.41 dBm with a 46.37 % PAE.A maximum PAE is 47.92 % with a 29.08 dBm output power.
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Lee, Po-Chen, and 李柏辰. "A Wideband Class-AB Power Amplifier in 65nm CMOS." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/67935160782026903172.
Full textAbstract:
碩士<br>國立清華大學<br>電機工程學系<br>102<br>In this thesis, there is a wideband class-AB power amplifier (PA) had been designed, simulated, analyzed, and taped out with TSMC 65nm CMOS technology. The thesis is organized into five chapters. The first two chapters are the applications, related parameters, and design theories of the PA. The other chapters are about the design flow, circuit simulation and results analysis. The complete circuit is a radio-frequency transmitter, which includes an input buffer stage, a power stage, and a balance to unbalance transformer to connect with the output port.
The wideband class-AB PA is applied to the impulse radio-frequency transmitter. There will be two opposite phase clock signal through the switchable clock buffer to the PA, and the frequency of the clock signal will be the operation frequency of the PA. After the signal through the buffer, it will become a 1ns impulse with 100ns period, and then the PA will increase the power of the output signal for antenna measurements. The power supply of the transmitter is 1.0V, and the power consumption is about 33mW when turn on. The main operation frequency of the PA is 7.5GHz with 9dBm saturation power, 13dBm IIP3, and 25％ PAE. The operational bandwidth of the circuit is 3.2GHz to 8.6GHz. The definition of the bandwidth in this design is 3dB decrease of S21 and S22 should be smaller than -6dB to avoid the formation of standing wave on the PCB.
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Lin, Yi-shu, and 林義書. "High Power CMOS RF Amplifier Module Expandable in parallel." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/67083195040898293205.
Full textAbstract:
碩士<br>國立成功大學<br>電機工程學系專班<br>97<br>In this thesis, high-power CMOS power amplifier modules are investigated. In radio-frequency (RF) transmitter front-end, power amplifiers are an important component. Power amplifiers can amplify base-band signals and then transport them into an antenna for wireless communication system.
The integration of wireless communication systems has taken a long journey into the modern world. The feature of CMOS processing technology is fully integrated with base-band system and the cost is cheaper. It is designed to operate in the application of Mobile WiMAX 802.16e band, which has the operation frequency ranging from 2400MHz to 2700MHz.
In this thesis, a differential push-pull topology is used to suppress even-order harmonics, and an adopting substrate bias topology can greatly reduce the body effect, the efficiency and linearization can be improved. We design three circuits of CMOS power amplifier with differ power combing topology.
In the first design, 3.5GHz transformer-integrated RF power amplifier, we designed the on-chip transformer to split input signal and combine output signal. The circuit is capable of delivering 23.6dBm of maximum output power with an 28% power-added efficiency and 20.5dBm of linear output power with 17% PAE. The power gain is 11.6dB, and the output third-order intercept point is 32dBm.
In the second design, a power module is like as the first circuit except that the output on-chip transformer is replaced by LC resonators. The circuit is capable of delivering 25dBm of maximum output power with an 41.8% power-added efficiency and 22.4dBm of linear output power with 30% PAE. The power gain is 11.6dB, and the output third-order intercept point is 30dBm.
At last, we have simulated and tested high-power CMOS RF power amplifier by combining with two power modules in parallel for mobile WiMAX application. This power amplifier is capable of delivering 28.4dBm of linear output power with 33.6% power-added efficiency and fit in with specification of mobile WiMAX.
With EM simulation of Aglient ADS, the influence of lines in the layout can be considered. The circuits are implemented by TSMC 0.18um CMOS process. These chips have also been fabricated and measured by the support of CIC in Taiwan.
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Kuo, Jing-Lin, and 郭京霖. "Research of CMOS Microwave and Millimeter-wave Power Amplifier." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/87220161599352559817.
Full textAbstract:
碩士<br>國立臺灣大學<br>電信工程學研究所<br>96<br>The goal of the thesis is to design and implement three power amplifiers (PAs) in CMOS process. The thesis consists of three parts. The first part introduces the basic of power amplifier theory, then introduces the design consideration and the design challenge of the CMOS power amplifier.
In the second part, the first PA is implemented in a standard 0.18-μm CMOS technology. The major challenge of this circuit is that the breakdown voltage is about 1.8 V. Proper design of matching networks leads to good power and gain performances. The measured output power is 19.1 dBm and the small signal gain is 18.8 dB at 24 GHz. The chip size is only 0.56 x 0.58 mm2.
In the third part, two PAs are designed and measured for 60 GHz systems. Thin-film microstrip lines (TFMS) used as matching elements to reduce the effect of lossy substrate on these two circuits. The first PA fabricated in 0.13-μm CMOS process. This PA achieves a measurement Psat of 14.3 dBm, P1dB of 11.2 dBm, PAE of 8 %, and linear gain of 15.5 dB at the frequency of 55 GHz, with a chip size of 0.66 x 0.5 mm2, when VDD is biased at 3 V. The second PA fabricated in a more advanced 90-nm CMOS process. The circuit is designed to have a wide-band frequency response to tolerate process variation. The MMIC PA has a wide 3-dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 x 0.5 mm2. When VDD is biased at 2.4 V, this PA achieves a measurement Psat of 16.2 dBm, P1dB of 12 dBm, PAE of 15 %, and linear gain of 33 dB at the frequency of 60 GHz.
The simulations agree with the measurements very well in these PAs, also, three PAs demonstrated high output power compared with the previously works of CMOS PAs operating at frequencies around 24 GHz and 60 GHz.
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Liu, Yi-Chung, and 劉沂娟. "A 2.4GHz CMOS RF Power Amplifier with Linear Compensation." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/78610684281473840509.
Full textAbstract:
碩士<br>國立交通大學<br>電子工程系<br>91<br>This thesis is proposed for designing a CMOS power amplifier with linear compensation. All designs are targeted on the standard of Bluetooth v1.0b. Three power amplifiers are conventional power amplifier, power amplifier with PMOS compensation and common-mode cancellation, and improved gm3 power amplifier. Two of these power amplifiers are designed, proposed, and measured. The improved gm3 power amplifier is in process. All are fabricated in a standard 0.25μm single-poly-five-metal CMOS process. The conventional power amplifier chip can provide 20.39dBm output power with 24% drain efficiency at 2.7GHz. The operating dc current of conventional one is 156mA from 2.5V power supply. At output power equal 20dBm, the IM3 under two-tone test is about -16.26dBc. The ACPR is about 21dB at 550kHz bandwidth. Through measured results, the performance of the proposed CMOS RF power amplifier has been verified to be well suitable for short-range communication applications and can meet Bluetooth output power level class 1(20dBm) and linearity specifications. Unfortunately, the chip with PMOS compensation and common-mode cancellation has oscillation phenomena since the design consideration non-proper. Although it still can measure out the output power and power gain, but the results are not correct enough.
From post-simulation results it can be found that these two types of power amplifier with linear compensation circuit would decrease 1~3dB output third-order intermodulation distortion at output power level equal 20dBm. When a common-mode signal exists, these two types of PA can increase 3dB IM3 values because of high CMRR value.
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Tsen, Chia-Hung, and 岑嘉宏. "THE DESIGN OF A 5.25GHZ CMOS LINEAR POWER AMPLIFIER." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/07213516821061943274.
Full textAbstract:
碩士<br>國立交通大學<br>電資學院學程碩士班<br>91<br>Two CMOS RF power amplifiers with different compensation schemes to improve the linearity of CMOS PAs for WLAN applications are presented in this thesis. These two proposed chips are fabricated in a standard 0.25um single-poly-five-metal (1P5M) CMOS process.
The proposed PMOS compensation PA consumes 156mA DC quiescent current from a 3.3V supply voltage. The two-stage PMOS compensation PA can provide up to 20.94dBm output power with 14.2% drain efficiency at 4.5GHz. The output P1dB is 15.2dBm and the output IP3 can achieve 24.6dBm. The proposed varactor compensation PA consumes the same DC quiescent current as PMOS compensation PA. The two-stage varactor compensation PA can provide up to 21.65dBm output power with 17% drain efficiency at 4.5GHz. The output P1dB is 15.8dBm and the output IP3 can achieve 26.13dBm.
In these two different compensation schemes of PA designs, the varactor compensation PA has better linearity, efficiency and output power. From measured results, the performance of these two proposed CMOS RF power amplifiers have been verified to achieve output power level over 20dBm at the frequency range near 5GHz and the best output IP3 is over 26dBm.