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Journal articles on the topic 'CMOS power amplifier'

Author: Grafiati

Published: 3 June 2025

Last updated: 23 June 2025

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1

Shukla, Sachchidanand, Syed Shamroz Arshad, Kavita Thakur, and Geetika Srivastava. "Issues and Challenges in Small-Signal Low-Power Amplifiers: A Review." Indian Journal Of Science And Technology 17, no. 36 (2024): 3787–99. http://dx.doi.org/10.17485/ijst/v17i36.2171.

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Background: Contemporary linear electronic circuit designs frequently include small-signal low-power amplifiers as a fundamental building block. These amplifiers are widely used as LNAs (Low Noise Amplifiers) in the pre-amplifier stages of both low-frequency and high-frequency featured electronic circuits. Objectives: To review the recent advances in the design of small-signal low-power amplifiers based on device configuration of BJTs, JFETs and MOSFETs for low (≤1KHz) and high frequencies (≥1MHz) at smaller input voltage (<1 Volt). Methods: The articles published between 2010 to 2024 are shortlisted from IEEE Xplore, Springer, Science Direct Elsevier, Google Scholar, and MDPI databases and the outcomes of the different techniques are compared on various parameters. Findings: It is found that four-stage CMOS amplifier at TSMC 40nm process technology emerges with highest 84.59dB gain, InP (Indium Phosphide) Distributed Amplifier Using 3-D Interdigital Capacitors carries widest bandwidth of 160 GHz, two stage darlington pair amplifier at 0.18μm under dual input and dual output topologies and four stage CMOS amplifier at 40nm technology realizes lower power consumption of 0.5mW and 0.00086 mW respectively. Small Signal Amplifier based on single stage BJT-JFET Sziklai pair operates at lowest frequency of 11.36 Hz, single stage LNA at 180nm CMOS technology using inductive degenerate topology works at very low supply voltage at +0.5V and, recently reported complementary sziklai based small signal amplifier under CC mode works at lowest -15V supply voltage. Novelty: The review proposed on ‘Small Signal Low Power Amplifier’ is first time reported in this paper. Moreover, it discusses low power small signal amplifiers at both low (≤1KHz) and high (≥MHz) frequencies considering gain enhancement technique, power dissipation reduction technique, and noise reduction technique whereas other review papers emphasize on the general discussion of different topologies only at high frequencies. Keywords: Small-Signal Amplifiers, Low Power Amplifiers, BJTs, JFETs, MOSFETs

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2

Gangadharan, Shaina, Ruqaiya Khanam, and Veeraiyah Thangasamy. "A Study of RF Power Amplifiers for 5G and Future Generation Mobile Communication: Can FinFET Replace CMOS?" International Journal of Experimental Research and Review 46 (December 30, 2024): 222–39. https://doi.org/10.52756/ijerr.2024.v46.018.

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A low-power strategy that can manage analogue, digital, and RF functionalities on a similar chip is crucial for wireless systems. Various difficulties restrict the widespread adoption of CMOS power amplifiers despite the fact that they provide highly integrated, low-cost wireless communication. Some of the main issues with CMOS power amplifiers include non-linearity, low breakdown voltage, a lack of high-voltage capacitors, and incorrect RF models. The RF signal is amplified without distortions using a linear power amplifier (LPA), which is less effective whenever driven by constant voltage. In order to significantly enhance the effectiveness of the power amplifiers, three frequently utilised techniques—Doherty, envelope elimination and restoration (EER), and envelope tracking (ET) techniques are reviewed in this work. Results point towards ET approach as the one that is ideally suited for future mobile communication systems. The essential component of ET systems, the envelope tracking power source, is what determines how effectively the system functions. It also lists the benefits of FinFET technology over CMOS and looks at three well-liked techniques for increasing power amplifier efficiency. Considering the advent of mobile communications systems, the frequency band and peak-to-average power ratio (PAPR) are quickly growing, posing significant design issues. FinFET as an alternative may considerably reduce the chip area.

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3

Zhao, Wenzhuo. "Comparison Of Three CMOS Amplifiers Used in Communication." Highlights in Science, Engineering and Technology 111 (August 19, 2024): 18–23. http://dx.doi.org/10.54097/pkmmt761.

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With the rapid development of wireless communication technology, the low power consumption, low cost, and high efficiency of wireless communication equipment have become the development trend. Because of the increasing problems caused by power consumption, to meet the needs of people and the market, people should first understand the principle of low-power amplifiers and scientific research results to get inspiration. This paper summarizes the advantages and disadvantages of three kinds of amplifiers and draws some conclusions to better understand the low-power amplifier. Ultra-low power low noise amplifier circuit with high gain and low voltage operating at 5.2GHz. The folded cascade structure and forward substrate bias technology are used to reduce the operating voltage of LNA, and the input impedance matching of the first amplifier is achieved by the source inductance negative feedback technology. The second stage amplifier introduces the transformer negative feedback Transconductance enhancement technique. The second amplifier is 5.8GHz CMOS power amplifier. A computer-aided method for calculating device values in an RC feedback network is used to improve the stability of a power amplifier. The single-ended power amplifier is designed by using Shanghai 0.18μm CMOS technology. The lase one is ultra-low noise, high linear ultra-wideband low noise amplifier circuit operating at 3.1-10.6GHz. It mainly consists of two stages: the first stage is the input matching stage, which adopts the common gate structure to realize the broadband input matching; The second stage is an amplifier stage, which is composed of an improved common source common gate structure.

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4

Tiwari, Nitendra kumar. "Low Power Reduction Techniques Implementation and Analysis in Sense Amplifier Circuit Configurations." Journal of Futuristic Sciences and Applications 5, no. 2 (2022): 31–37. http://dx.doi.org/10.51976/jfsa.522205.

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MTCMOS (Multi-Threshold CMOS), sleepy stack, sleepy keeper, and footer stack are examples of low power saving techniques incorporated into the core gpdk 90nm technology papers used in the proposed study using Cadence. The main focus of these tests is the power consumption of various sense amplifier circuits. The simulation results show that the charge-transfer sense amplifier uses much less energy than voltage and current sense amplifiers. The present mode detecting amplifier’s power consumption can be decreased by up to 98 percent by using MTCMOS technology.

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5

Sachchidanand, Shukla, Shamroz Arshad Syed, Thakur Kavita, and Srivastava Geetika. "Issues and Challenges in Small-Signal Low-Power Amplifiers: A Review." Indian Journal of Science and Technology 17, no. 36 (2024): 3787–99. https://doi.org/10.17485/IJST/v17i36.2171.

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Abstract <strong>Background:</strong> Contemporary linear electronic circuit designs frequently include small-signal low-power amplifiers as a fundamental building block. These amplifiers are widely used as LNAs (Low Noise Amplifiers) in the pre-amplifier stages of both low-frequency and high-frequency featured electronic circuits.<strong> Objectives:</strong> To review the recent advances in the design of small-signal low-power amplifiers based on device configuration of BJTs, JFETs and MOSFETs for low (≤1KHz) and high frequencies (≥1MHz) at smaller input voltage (<1 Volt). Methods: The articles published between 2010 to 2024 are shortlisted from IEEE Xplore, Springer, Science Direct Elsevier, Google Scholar, and MDPI databases and the outcomes of the different techniques are compared on various parameters.<strong> Findings:</strong> It is found that four-stage CMOS amplifier at TSMC 40nm process technology emerges with highest 84.59dB gain, InP (Indium Phosphide) Distributed Amplifier Using 3-D Interdigital Capacitors carries widest bandwidth of 160 GHz, two stage darlington pair amplifier at 0.18μm under dual input and dual output topologies and four stage CMOS amplifier at 40nm technology realizes lower power consumption of 0.5mW and 0.00086 mW respectively. Small Signal Amplifier based on single stage BJT-JFET Sziklai pair operates at lowest frequency of 11.36 Hz, single stage LNA at 180nm CMOS technology using inductive degenerate topology works at very low supply voltage at +0.5V and, recently reported complementary sziklai based small signal amplifier under CC mode works at lowest -15V supply voltage.<strong> Novelty:</strong> The review proposed on ‘Small Signal Low Power Amplifier’ is first time reported in this paper. Moreover, it discusses low power small signal amplifiers at both low (≤1KHz) and high (≥MHz) frequencies considering gain enhancement technique, power dissipation reduction technique, and noise reduction technique whereas other review papers emphasize on the general discussion of different topologies only at high frequencies. <strong>Keywords:</strong> Small-Signal Amplifiers, Low Power Amplifiers, BJTs, JFETs, MOSFETs

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6

Lee, Milim, Junhyuk Yang, Jaeyong Lee, and Changkun Park. "Design Techniques for Wideband CMOS Power Amplifiers for Wireless Communications." Electronics 13, no. 9 (2024): 1695. http://dx.doi.org/10.3390/electronics13091695.

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In this study, we designed a wideband CMOS power amplifier to support multi-band and multi-standard wireless communications. First, an input matching technique through LC network and a wideband design technique using a low Q-factor transformer were proposed. In addition, a design technique was proposed to improve output matching using RC feedback. To verify the feasibility of the proposed design methodology for wideband CMOS power amplifiers, the designed power amplifier was fabricated using a 180 nm RFCMOS process. The size including all of the matching network and test pads was 1.38 × 0.90 mm2. In addition, the effectiveness of the proposed power amplifier was verified through the measured results using modulated signals of WCDMA, LTE, and 802.11n WLAN.

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7

Grujic, Dusan, and Lazar Saranovac. "Broadband power amplifier limitations due to package parasitics." Serbian Journal of Electrical Engineering 12, no. 3 (2015): 275–91. http://dx.doi.org/10.2298/sjee1503275g.

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Limitations of CMOS broadband power amplifiers due to package parasitics have been explored in this paper. The constraints of power amplifier matching network, realized as a third-order Chebyshev filter, have been derived, and a new power amplifier design flow has been proposed. As an example of a proposed design flow, an UWB power amplifier has been designed. Transistor level large signal simulation results are in excellent agreement with theoretical predictions.

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8

Cancelli, Roberto, Gianfranco Avitabile, and Antonello Florio. "Designing and Optimizing a 2.4 GHz Complementary Metal–Oxide-Semiconductor Class-E Power Amplifier Combining Standard and High-Voltage Metal–Oxide-Semiconductor Field-Effect Transistors." Electronics 14, no. 6 (2025): 1135. https://doi.org/10.3390/electronics14061135.

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The advent of CMOS power amplifiers has enabled compact and cost-effective solutions for RF applications. Among the available options, switching amplifiers are the most competitive due to their superior efficiency. In this paper, we present the design of a fully integrated 130 nm CMOS class-E RF power amplifier optimized for 2.4 GHz ISM band operations that is compliant with the Bluetooth Low Energy (BLE) standard. The amplifier is based on a cascode configuration with charging acceleration capacitance and a combination of standard and high-voltage (HV) MOSFETs, ensuring optimal performance while maintaining device reliability. To identify the best configuration for the proposed circuit, we first provide an overview of basic class-E amplifier operations and critically review optimization techniques proposed in the scientific literature. This review is complemented by a numerical analysis of the potential advantages of using a combined standard-HV MOSFET structure. Post-layout simulations with parasitic parameter extraction demonstrated that the amplifier achieves 40.85% Power Added Efficiency and 20.52 dBm output power.

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9

Ma, Huijia. "CMOS Embedded High-Efficiency Cardiac Pacemakers Design." Highlights in Science, Engineering and Technology 15 (November 26, 2022): 252–60. http://dx.doi.org/10.54097/hset.v15i.2642.

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With the increasing incidence of sudden cardiac death in recent years, the importance of pacemakers has become particularly important. This paper study CMOS circuit design in pacemakers so that they can stay for a long time without charging. Firstly, compared with class A and B amplifier which has low efficiency and high distortion respectively, class AB amplifiers act as a balance between linearity and efficiency, achieving high current drive capability with very low static power consumption. A current mirror based on transduction multiplication to achieve ultra-low current consumption confirms the usefulness of AB amplifiers in pacemakers. This paper design a low power consumption circuit. Firstly, we compare the circuit diagrams of different A, B class amplifiers and analyze their characteristics. Secondly, we analyzed the principle of Class AB amplifier and verified its efficient characteristics. Finally, we studied the effect of this amplifier on a cardiac pacemaker.

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10

Oki, Daiki, Satoru Kawauchi, Cong Bing Li, et al. "A Power-Efficient Noise Canceling Technique Using Signal-Suppression Feed-Forward for Wideband LNAs." Key Engineering Materials 643 (May 2015): 109–16. http://dx.doi.org/10.4028/www.scientific.net/kem.643.109.

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This paper presents a power-efficient noise-canceling technique based on the feed-forward amplifiers, considering a fundamental tradeoff between noise figure (NF) and power consumption in the design of wide-band amplifiers. By suppressing the input signal of the noise cancellation amplifier, the nonlinear effect on the amplifier can be reduced, as well as the power consumption can be smaller. Furthermore, as a lower gain of the noise-canceling sub-amplifier can be achieved simultaneously, further reduction of the power consumption becomes possible. The verification of the proposed technique is conducted with Spectre simulation using 90nm CMOS process.

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11

Kumar, Sunil, and Arun Kr Chatterjee. "Comparative study of different Sense Amplifiers in 0.18um technology." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 3 (2013): 615–19. http://dx.doi.org/10.24297/ijct.v7i3.3440.

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A comparative study of different types of sense amplifiers [1] using 0.18um technology is presented. The sense amplifiers under considerations are used in SRAM and DRAM cells.The sensing delay of different types of sense amplifiersÂ are evaluated with respect to variation of bitline capacitance. Comparative results are also provided for the variation in delay with respect to power supply. Extensive results based on 0.18um CMOS technology using CADENCE Spectre simulation tools are presented for different architectures of sense amplifiers. From these results it has been proven that if the output of sense amplifier is isolated from the bitline parasitic capacitance then the sensing delay of sense amplifier reduces.

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12

Liu, Ling, Song Ye, Weimin Wang, and Wenying Ma. "A Compact 60GHz Power Amplifier in 65nm CMOS Technology." Journal of Physics: Conference Series 2221, no. 1 (2022): 012037. http://dx.doi.org/10.1088/1742-6596/2221/1/012037.

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Abstract A compact 60GHz power amplifier chip in 65nm CMOS technology of three-stage common source structure is presented. The first two amplifiers offer sufficient gain to pre-amplify the small input power. The third stage amplifier uses two sets of differential pairs to achieve power synthesis. On-chip transformer coupling is adopted to realize inter-stage impedance matching as well as input and output matching. The compact structure of on-chip transformer can reduce the chip size and improve the integration degree. The measured small signal gain at 60GHz of 22.3dB, the saturation power of 20.2dBm, the output P-1dB of 17.3dBm, the PAE of 14%, and the core area is 0.19mm2. The power amplifier can be used in high-speed short-range wireless communication system to enhance communication data transmission capacity.

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13

Sapawi, Rohana. "Review of Efficiency CMOS Class AB Power Amplifier Topology in Gigahertz Frequencies." ASM Science Journal 17 (May 17, 2022): 1–11. http://dx.doi.org/10.32802/asmscj.2022.1224.

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This paper reviewed the efficiency of CMOS class AB power amplifier topology especially in gigahertz frequencies. CMOS class AB power amplifier is a compromise between class A and class B in terms of linearity and efficiency between 50% to 78.5%. However, CMOS class AB power amplifier cannot have good linearity and efficiency simultaneously due to the breakdown in gate-oxide voltage and effects from hot carrier. The breakdown of oxide prevents optimum drain signal and the effect from hot carrier will reduce the quality of the overall PA design. Several works from year 1999 to 2019 with different topology such as multiple gated transistor, cascode, feedforward linearization, differential circuit, transformer combining method with common source harmonic termination and combination of a dual-switching transistor with a third harmonic tuning technique are discussed and the performances of the power amplifier are compared. The best three CMOS class AB power amplifier topologies were chosen in terms of high efficiency. The topologies are two stages with integrated input and interstage matching, Doherty amplifier combined with drain modulation based architectures and self-biased cascode topology that obtained power added efficiency of 45%, 43% and 42%, respectively. Key performance indicators for class AB power amplifier include frequency, power added efficiency, gain and output power are also discussed in this paper.

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14

Zamora, Iván, Eyglis Ledesma, Arantxa Uranga та Núria Barniol. "Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays". Sensors 20, № 4 (2020): 1205. http://dx.doi.org/10.3390/s20041205.

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This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.

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15

Kwak, Joon Young, and Sung-Yun Park. "Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers." Electronics 10, no. 2 (2021): 145. http://dx.doi.org/10.3390/electronics10020145.

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A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

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Kwak, Joon Young, and Sung-Yun Park. "Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers." Electronics 10, no. 2 (2021): 145. http://dx.doi.org/10.3390/electronics10020145.

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A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

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17

Schmucker, Landon, Payman Zarkesh-Ha, Luke Emmert, Wolfgang Rudolph, and Vitaly Gruzdev. "Design of a Low-Noise Subthreshold CMOS Inverter-Based Amplifier with Resistive Feedback." Electronics 14, no. 5 (2025): 902. https://doi.org/10.3390/electronics14050902.

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The recent trend in analog design to replace typical analog circuits with digital implementations has led to the use of resistive feedback to pull a CMOS inverter into the switching threshold region to achieve gain, which is ideal for analog operations. Here, we report a three-transistor (3T) CMOS resistive-feedback inverter-based amplifier capable of achieving high gain paralleled with reduced noise, low power consumption, and enhanced stability. Unlike conventional resistive-feedback inverter-based amplifiers, the transistors are operated in the subthreshold region, which allows for a lower supply voltage and current, leading to lower power consumption. Subthreshold conduction also reduces typical amplifier noise sources. This design provides a novel approach to resistive feedback in the inverter amplifier, allowing for a large gain while occupying minimal layout area. The reported amplifier design facilitates unique capabilities, e.g., detection of ultra-low (fC) charges or sub-pA currents for newly emerging PHz electronic and optoelectronic devices driven by few-cycle laser pulses. As proof of concept, the specifications of the proposed amplifier are successfully measured and verified by multiple test chips designed and fabricated in TSMC’s 180 nm CMOS process. The fabricated amplifier operates at a 1.35 V power supply with a measured voltage gain of 53.61 dB (or 480 V/V), a bandwidth of 94 kHz, and an equivalent input voltage noise of 6.4 nV/Hz, consuming only 13.5 µW.

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18

Nagham, Gamal El-Feky, Mohamed Ellaithy Dina, and Hassan Fedawy Mostafa. "Ultra-wideband CMOS power amplifier for wireless body area network applications: a review." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 3 (2023): 2618–31. https://doi.org/10.11591/ijece.v13i3.pp2618-2631.

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A survey on ultra-wideband complementary metal-oxide semiconductor (CMOS) power amplifiers for wireless body area network (WBAN) applications is presented in this paper. Formidable growth in the CMOS integrated circuits technology enhances the development in biomedical manufacture. WBAN is a promising mechanism that collects essential data from wearable sensors connected to the network and transmitted it wirelessly to a central patient monitoring station. The ultra-wideband (UWB) technology exploits the frequency band from 3.1 to 10.6 GHz and provides no interference to other communication systems, low power consumption, low-radiated power, and high data rate. These features permit it to be compatible with medical applications. The demand target is to have one transceiver integrated circuit (IC) for WBAN applications, consequently, UWB is utilized to decrease the hardware complexity. The power amplifier (PA) is the common electronic device that employing in the UWB transmitter to boost the input power to the desired output power and then feed it to the antenna of the transmitter. The advance in the design and implementation of ultra-wideband CMOS power amplifiers enhances the performance of the UWB-transceivers for WBAN applications. A review of recently published CMOS PA designs is reported in this paper with comparison tables listing wideband power amplifiers' performance.

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19

Bae, Jongsuk, Junghyun Ham, Haeryun Jung, Wonsub Lim, Sooho Jo, and Youngoo Yang. "Design of Two-Stage CMOS Power Amplifier." Journal of Korean Institute of Electromagnetic Engineering and Science 25, no. 9 (2014): 895–902. http://dx.doi.org/10.5515/kjkiees.2014.25.9.895.

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20

Fisher, J. A. "A high-performance CMOS power amplifier." IEEE Journal of Solid-State Circuits 20, no. 6 (1985): 1200–1205. http://dx.doi.org/10.1109/jssc.1985.1052459.

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21

Lee, Changhyun, and Changkun Park. "Design methodology for a switching-mode RF CMOS power amplifier with an output transformer." International Journal of Microwave and Wireless Technologies 8, no. 3 (2015): 471–77. http://dx.doi.org/10.1017/s1759078715001415.

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In this study, we propose a design methodology for a switching-mode RF CMOS power amplifier with an output transformer. For a given supply voltage, output power, and target efficiency, the initial values of the transistor size, output inductance, and capacitance can be sequentially determined during the design of the power amplifier. The breakdown voltage of the power transistor is considered in the design methodology. To prove the feasibility of the proposed design methodology, we provide the design example of a 2.4-GHz switching-mode CMOS power amplifier with 180-nm RF CMOS technology. From the measured results, the feasibility of the proposed design methodology is proved.

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22

Ryu, Hyunsik, Ilku Nam, Dong-Ho Lee, and Ockgoo Lee. "CMOS Power Amplifier Using Mode Changeable Autotransformer." Journal of the Institute of Electronics and Information Engineers 51, no. 4 (2014): 59–65. http://dx.doi.org/10.5573/ieie.2014.51.4.059.

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23

El-Feky, Nagham Gamal, Dina Mohamed Ellaithy, and Mostafa Hassan Fedawy. "Ultra-wideband CMOS power amplifier for wireless body area network applications: a review." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 3 (2023): 2618. http://dx.doi.org/10.11591/ijece.v13i3.pp2618-2631.

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<span lang="EN-US">A survey on ultra-wideband complementary metal-oxide semiconductor (CMOS) power amplifiers for wireless body area network (WBAN) applications is presented in this paper. Formidable growth in the CMOS integrated circuits technology enhances the development in biomedical manufacture. WBAN is a promising mechanism that collects essential data from wearable sensors connected to the network and transmitted it wirelessly to a central patient monitoring station. The ultra-wideband (UWB) technology exploits the frequency band from 3.1 to 10.6 GHz and provides no interference to other communication systems, low power consumption, low-radiated power, and high data rate. These features permit it to be compatible with medical applications. The demand target is to have one transceiver integrated circuit (IC) for WBAN applications, consequently, UWB is utilized to decrease the hardware complexity. The power amplifier (PA) is the common electronic device that employing in the UWB transmitter to boost the input power to the desired output power and then feed it to the antenna of the transmitter. The advance in the design and implementation of ultra-wideband CMOS power amplifiers enhances the performance of the UWB-transceivers for WBAN applications. A review of recently published CMOS PA designs is reported in this paper with comparison tables listing wideband power amplifiers' performance.</span>

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24

Dina, M. Ellaithy. "A 3.8–8.4 GHZ 0.13 µM CMOS POWER AMPLIFIER FOR ULTRA-WIDEBAND APPLICATIONS." International Journal of Advances in Engineering & Technology 16, no. 6 (2023): 468–76. https://doi.org/10.5281/zenodo.10516429.

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<em>Implementation of highly power-efficient transceivers has thus become a crucial research area with the move to wideband technologies. CMOS power amplifiers (PAs) are becoming an essential component of the technology mix for RF front-end devices. However, their properties could be limiting for complete system efficiency. Decreased power dissipation and less area are considered the main design challenges for portable and low-cost devices. Therefore, to increase battery lifetime and reduced cost, a high performance integrated CMOS power amplifier (PA) has been proposed in this paper. Our scheme achieves a power gain of 12.7 dB with better gain flatness of ±0.5 dB over the frequency band beginning from 3.8 GHz to 8.4 GHz, and a power dissipation of 24.8 mW with less area of 0.40 mm2, using 130 nm CMOS technology.</em>

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25

Dong, Ruibing, Yiheng Song, and Yang Xing. "A 110 GHz Feedback Amplifier Design Based on Quasi-Linear Analysis." Electronics 12, no. 17 (2023): 3725. http://dx.doi.org/10.3390/electronics12173725.

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The power gain and output power of millimeter-wave (mm-Wave) and terahertz (THz) amplifiers are critical performance metrics, particularly when the operating frequencies of amplifiers are near to the maximum oscillator frequency (fmax) of the transistor. This paper presents the design of a 110 GHz amplifier based on the quasi-linear method. The power gain can be boosted to maximum achievable gain (Gmax) using a linear, lossless, reciprocal feedback network, though this leads to a simultaneous decrease in output power. Based on quasi-linear analysis, for an amplifier with Gmax gain, when the K-factor is equal to 1, the output power is zero. To avoid the very low output power of amplifiers, a new approach is proposed to balance power gain and output power. A 110 GHz six-stage feedback amplifier was designed using the proposed approach and fabricated using 40 nm CMOS technology. The measured power gain is 26.5 dB, and the saturation output power is 13 dBm at 110 GHz.

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26

Al-Kofahi, Idrees S., Zaid Albataineh, and Ahmad Dagamseh. "A two-stage power amplifier design for ultra-wideband applications." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 772. http://dx.doi.org/10.11591/ijece.v11i1.pp772-779.

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In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz based on common source inductive degeneration with an auxiliary amplifier is proposed. In this proposal, an auxiliary amplifier is used to place the 2nd harmonic in the core amplified in order to make up for the gain progression phenomena at the main amplifier output node. Simulation results show a power gain of 16 dB with a gain flatness of 0.4 dB and an input 1 dB compression of about -5 dBm from 3 to 5 GHz using a 1.8 V power supply consuming 25 mW. Power added efficiency (PAE) of around 47% at 4 GHz with 50 Ω load impedance was also observed.

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27

Idrees, S. Al-Kofahi, Albataineh Zaid, and Dagamseh Ahmad. "A two-stage power amplifier design for ultra-wideband applications." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 772–79. https://doi.org/10.11591/ijece.v11i1.pp772-779.

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In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultrawideband (UWB) 3 to 5 GHz based on common source inductive degeneration with an auxiliary amplifier is proposed. In this proposal, an auxiliary amplifier is used to place the 2nd harmonic in the core amplified in order to make up for the gain progression phenomena at the main amplifier output node. Simulation results show a power gain of 16 dB with a gain flatness of 0.4 dB and an input 1 dB compression of about -5 dBm from 3 to 5 GHz using a 1.8 V power supply consuming 25 mW. Power added efficiency (PAE) of around 47% at 4 GHz with 50 Ω load impedance was also observed.

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28

Yoshida, Eiji, Yasufumi Sakai, Kazuaki Oishi, et al. "Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets." Japanese Journal of Applied Physics 53, no. 4S (2014): 04EE19. http://dx.doi.org/10.7567/jjap.53.04ee19.

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R., V. Saranya, and Sureshkumar R. "CMOS INSTRUMENTATION AMPLIFIER FOR BIOMEDICAL APPLICATIONS." International Journal of Engineering Research and Modern Education 3, no. 1 (2017): 116–20. https://doi.org/10.5281/zenodo.802922.

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A low power high performance CMOS instrumentation amplifier is designed through the operational amplifier (op-amp) used for biomedical applications. It consists of a low power operational amplifier with three stage op-amp structure. First two stages consists of input stage and drive stage and the third stage consist of output stage. In biomedical applications, the instrumentation amplifier (IA) requires high gain, CMRR with less noise and low power optimization. The design and analysis of the parasitic effects and the other parameters is taken and the instrumentation amplifier is found to have better performance in all aspects. With the varying width and length of the transistor, we obtain the excepted gain and CMRR. The instrumentation amplifier improves the input signal gain and CMRR to have the excepted outcome of the biomedical signal processing application. The proposed design is implemented in CMOS 180nm technology using cadence Virtuoso and the simulation is obtained through spectre simulator.

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30

Shen, Haoyu, and Bin Wu. "A Fully Integrated High Linearity CMOS Dual-Band Power Amplifier for WLAN Applications in 55-Nm CMOS." Applied Sciences 14, no. 23 (2024): 10768. http://dx.doi.org/10.3390/app142310768.

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This paper presents a dual-band fully integrated high linearity CMOS power amplifier (PA). The PA employs a reconfigurable transformer in the input matching network to achieve low reflection coefficient across both bands, demonstrating significant flexibility in the design of dual-band power amplifiers with high output powers. Additionally, a detailed design methodology for the dual-band matching network is introduced. By utilizing this methodology, the PA has been designed using 55 nm CMOS technology. For continuous-wave operation, the PA achieves a saturated power (Psat) of 28.03 dBm and 27.5–28.2 dBm, with power-added efficiency (PAE) of 33.2% and 24.6–31.1%, in the 2.4 GHz and 5 GHz WLAN bands, respectively. Concurrently, the PA power cells, which employ multi-gate transistor (MGTR) technology, achieve an intermodulation distortion (IMD3) of below 30 dBc at an output power of 15 dBm in both the 2.4 GHz and 5 GHz WLAN bands. The proposed PA outperforms other dual-band or multi-band PAs in terms of output power and exhibits great potential for WLAN applications.

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31

McCune, Earl. "A Technical Foundation for RF CMOS Power Amplifiers: Part 2: Power Amplifier Architectures." IEEE Solid-State Circuits Magazine 7, no. 4 (2015): 75–82. http://dx.doi.org/10.1109/mssc.2015.2474236.

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32

De Lima, Jader A. "A Compact Low-Distortion Low-Power Instrumentation Amplifier." Journal of Integrated Circuits and Systems 5, no. 1 (2010): 33–41. http://dx.doi.org/10.29292/jics.v5i1.308.

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A CMOS instrumentation amplifier based on a simple topology that comprises a double-input Gm-stage and a low-distortion class-AB output stage is presented. Sub-threshold design techniques are applied to attain high figures of differential-gain and rejection parameters. Analyses of input-referred noise and CMRR are comprehensively carried out and their dependence on design parameters determined. The prototype was fabricated in standard n-well CMOS process. For 5V-rail-to-rail supply and bias current of 100nA, stand-by consumption is only 16μW. Low-frequency parameters are ADM=86dB, CMRR=89.3dB, PSRR+=87dB, PSRR-=74dB. For a 6.5pF-damping capacitor, ΦM=73º and GBW=47KHz. The amplifier exhibits a THD of –64.5dB @100Hz for a 1Vpp-output swing. Input-noise spectral density is 5.2μV/ Hz @1Hz and 1.9μV/ Hz @10Hz, which gives an equivalent input-noise of 37.6μV, over 1Hz-200Hz bandwidth. This circuit may be employed for low-frequency, low-distortion signal processing, advantageously replacing the conventional 3-opamp approach for instrumentation amplifiers.

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33

Poojitha, D. Guru. "Low Power Two Stage CMOS Operational Amplifier." International Journal for Research in Applied Science and Engineering Technology 13, no. 4 (2025): 2088–91. https://doi.org/10.22214/ijraset.2025.68650.

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Abstract: Operational amplifier (Op-Amp) circuits play a critical role in computation, instrumentation, and a variety of industrial applications. With the growing demand for precision Op-Amps in automotive and industrial environments, there is an increasing need for designs that offer enhanced accuracy and robust performance across wide temperature ranges. The shift towards integrating both analog and digital circuits on a single chip has made Complementary Metal-Oxide Semiconductor (CMOS) technology the preferred choice over traditional bipolar technologies for analog circuit design in mixed-signal systems. Among various Op-Amp topologies, the two-stage architecture remains one of the most widely adopted due to its favorable gain and output swing characteristics. This paper presents the design and simulation of a CMOS-based two-stage fully differential operational amplifier, optimized for low-power and low-voltage operation. The amplifier is biased with a current of 20 µA and is implemented using both 180 nm and 90 nm CMOS process technologies. Special emphasis is placed on operation in the sub-threshold region, where the unique behavior of MOS transistors facilitates ultra-low-voltage and low-current operation. The proposed Op-Amp is intended for on-chip applications with capacitive load requirements in the picofarad range. Simulation results are obtained using the Cadence Virtuoso design environment and demonstrate the performance of the amplifier across key parameters in both technology nodes

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34

Masoumi, Nasser, and Mohammad Moghaddam Tabrizi. "CMOS linear high performance push amplifier for WiMAX power amplifier." Microelectronics Journal 43, no. 8 (2012): 521–29. http://dx.doi.org/10.1016/j.mejo.2012.05.007.

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35

Kim, Bumman, Byungjoon Park, and Sangsu Jin. "Design of an Advanced CMOS Power Amplifier." Journal of electromagnetic engineering and science 15, no. 2 (2015): 63–75. http://dx.doi.org/10.5515/jkiees.2015.15.2.63.

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36

Anand, Dr Priyanka. "Designing CMOS based Class E Power Amplifier." International Journal for Research in Applied Science and Engineering Technology 7, no. 8 (2019): 889–97. http://dx.doi.org/10.22214/ijraset.2019.8131.

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37

Wang, To-Po. "Performance enhancement techniques for CMOS power amplifier." IEICE Electronics Express 8, no. 12 (2011): 969–77. http://dx.doi.org/10.1587/elex.8.969.

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Lee, Ockgoo, Kyu Hwan An, Juphil Cho, and Jaesang Cha. "A switchless reconfigurable transformer CMOS power amplifier." IEICE Electronics Express 9, no. 9 (2012): 855–60. http://dx.doi.org/10.1587/elex.9.855.

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39

Lehmann, T., and M. Cassia. "1-V power supply CMOS cascode amplifier." IEEE Journal of Solid-State Circuits 36, no. 7 (2001): 1082–86. http://dx.doi.org/10.1109/4.933464.

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40

Kim, Y., C. Park, H. Kim, and S. Hong. "CMOS RF power amplifier with reconfigurable transformer." Electronics Letters 42, no. 7 (2006): 405. http://dx.doi.org/10.1049/el:20060237.

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41

Mistlberger, F., and R. Koch. "Class-AB high-swing CMOS power amplifier." IEEE Journal of Solid-State Circuits 27, no. 7 (1992): 1089–92. http://dx.doi.org/10.1109/4.142606.

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42

Park, Byungjoon, Sangsu Jin, Daechul Jeong, et al. "Highly Linear mm-Wave CMOS Power Amplifier." IEEE Transactions on Microwave Theory and Techniques 64, no. 12 (2016): 4535–44. http://dx.doi.org/10.1109/tmtt.2016.2623706.

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43

Sung, Myeong-U., Geun-Ho Choi, Habib Rastegar, et al. "24GHz CMOS Power Amplifier for Automotive Radar." International Journal of Control and Automation 10, no. 1 (2017): 267–76. http://dx.doi.org/10.14257/ijca.2017.10.1.24.

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44

Oh, Inn-Yeah, Keuk-Hwan Ra, and Chul-Soon Park. "Complementary predistorter in CMOS differential power amplifier." Microwave and Optical Technology Letters 52, no. 4 (2010): 833–36. http://dx.doi.org/10.1002/mop.25062.

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45

El-Sabban, A. A. F., and H. F. Ragai. "Design of power-controlled class1 Bluetooth CMOS power amplifier." International Journal of Electronics 95, no. 3 (2008): 265–74. http://dx.doi.org/10.1080/00207210701828010.

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46

Feng, Wu-Shiung, Chin-I. Yeh, and Min-Zhi Zhou. "3.1–10.6 GHz UWB low-power CMOS power amplifier." International Journal of Electronics Letters 1, no. 2 (2013): 87–95. http://dx.doi.org/10.1080/21681724.2013.817021.

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47

Tap-Beteille, H., D. Roviras, M. Lescure, and A. Mallet. "HIGH POWER AMPLIFIER PREDISTORTER ASIC IN STANDARD DIGITAL CMOS TECHNOLOGY." SYNCHROINFO JOURNAL 7, no. 4 (2021): 35–39. http://dx.doi.org/10.36724/2664-066x-2021-7-4-35-39.

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Satellite communications offer a wide coverage for global communication systems. In order to increase spectral efficiency, non constant modulus constellations are very attractive compared to the classical BPSK and QPSK schemes. A 16-QAM modulation could offer a significant increase in spectral efficiency for satellite communications. Because the available power on board the satellite is strongly limited, High Power Amplifiers (HPA) like Travelling Wave Tubes (TWT) or Solid State Power Amplifiers (SSPA) are generally operated near the saturation point with a low back off. When operated with such low back off, HPA are highly non linear amplifiers. So, the signal to amplify being strongly distorted, a predistorter has been developed. A high power amplifier predistorter has been implemented in 0.6 m CMOS technology. First, the predistorter is briefly described. Then, the implementation of the predistorter is shown. The circuits designed for the neuron first layer are described, as well as the simulation results obtained.

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48

Li, Zhi Yuan, та Xiang Ning Fan. "Design of a 0.7~3.8GHz Wideband Power Amplifier in 0.18-μm CMOS Process". Applied Mechanics and Materials 364 (серпень 2013): 429–33. http://dx.doi.org/10.4028/www.scientific.net/amm.364.429.

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The design of a 0.7~3.8GHz CMOS power amplifier (PA) for multi-band applications in TSMC 0.18-μm CMOS technology is presented. The PA proposed in this paper uses lossy matching network and low Q multistage impedance matching network to improve wideband. To achieve maximum linearity, this PA operates in the Class-A regime. The post-layout simulation results show that the power amplifier achieves 21.9dB of power gain, 22.3dBm of 1dB compression power output at 2GHz. The power adder efficiency (PAE) at gain compression point is 17.8% at 2GHz.

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49

Ahn, Hyunjin, Kyutaek Oh, Se-Eun Choi, et al. "A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications." Nanomaterials 14, no. 3 (2024): 262. http://dx.doi.org/10.3390/nano14030262.

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The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying −45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

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J., Sunil Kumar, Deepthi A., Kaveri U., and Ravalika Sharma N. "Assessment on the Adequacy of Current Supply Testing Methods in CMOS Operational Amplifier." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 5 (2020): 296–99. https://doi.org/10.35940/ijeat.E9313.069520.

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As the CMOS innovation is downsizing, spillage power has gotten one of the most basic structure worries for the chip fashioner. This paper proposes examination on the adequacy of current gracefully testing strategies in cmos operational amplifiers. In this work, a two phase operational amplifier is structured and faults are infused utilizing 250nm innovation. We will assess the viability of current checking systems in distinguishing Bridge and open deformities in CMOS operational amplifiers. We ought to assess the identification capacities by utilizing two current testing strategies. The principal strategy comprises the oversight of the transient flexible current (IDDT) and the subsequent procedure comprises the observing of quiet gracefully current (IDDQ).The most probable resistive and open defects are infused utilizing fault infusion extra transistors. Exhibitions of the CMOS operational amplifier are additionally assessed after each issue infusion. Spice stimulation ought to be done to compare about the proposed test systems and assess the best performing one. We ought to assess the recognition abilities by utilizing two current testing procedures. The primary system comprises the oversight of the transient gracefully current (IDDT) and the subsequent method comprises the checking of quiet flexibly current (IDDQ). The most probable resistive and open deformities are infused utilizing fault infusion extra transistors. Exhibitions of the CMOS operational amplifier are likewise assessed after each fault infusion. Flavor re-enactments ought to be done to look at the proposed test strategies and assess the best performing one.

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