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Scholvin, Jörg 1976. "RF power CMOS." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86742.
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Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (p. 103-105).
by Jörg Scholvin.
M.Eng.and S.B.
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Fritzin, Jonas. "Power Amplifier Circuits in CMOS Technologies." Licentiate thesis, Linköping : Department of Electrical Engineering, Linköpings universitet, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-21030.
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Wang, Chengzhou. "CMOS power amplifiers for wireless communications /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3112826.
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Gogineni, Usha 1975. "Performance limits of RF power CMOS." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/63070.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 131-136).
Wireless and mobile communication systems have become ubiquitous in our daily life. The need for higher bandwidth and thus higher speed and data rates in wireless communications has prompted the exploration of millimeter-wave frequencies. Some of the applications in this regime include high-speed wireless local area networks and high data rate personal area networks at 60 GHz, automotive collision avoidance radar at 77 GHz and millimeter-wave imaging at 94 GHz. Most of these applications are cost sensitive and require high levels of integration to reduce system size. The tremendous improvement in the frequency response of state-of-the-art deeply scaled CMOS technologies has made them an ideal candidate for millimeter-wave applications. A few research groups have already demonstrated single chip CMOS radios at 60 GHz. However, the design of power amplifiers in CMOS still remains a significant challenge because of the low breakdown voltage of deep submicron CMOS technologies. Power levels from 60 GHz power amplifiers have been limited to around 15 dBm with power-added efficiencies in the 10-20% range, despite the use of multiple gain stages and power combining techniques. In this work, we have studied the RF power potential of commercial 65 nm and 45 nm CMOS technologies. We have mapped the frequency, power and efficiency limitations of these technologies and identified the physical mechanisms responsible for these limitations. We also present a simple analytical model that allows circuit designers to estimate the maximum power obtainable from their designs for a given efficiency. The model uses only the DC bias point and on-resistance of the device as inputs and contains no adjustable parameters. We have demonstrated a record output power density of 210 mW/mm and power-added efficiency in excess of 75% at VDs = 1.1 V and f = 2 GHz on 45 nm CMOS devices. This record power performance was made possible through careful device layout for minimized parasitic resistances and capacitances. Total output power approaching 70 mW was measured on 45 nm CMOS devices by increasing the device width to 640 gm. However, we find that the output power scales non-ideally with device width because of an increase in normalized on-resistance in the wide devices. PAE also decreases with increasing device width because of degradation in f. in the wide devices. Additionally PAE decreases as the measurement frequency increases, though the output power remains constant with increasing frequency. Small-signal equivalent circuit extractions on these devices suggest that the main reason for the degradation in the normalized output power and PAE with increasing device width is the non-ideal scaling of parasitic gate and drain resistances in the wide devices.
by Usha Gogineni.
Ph.D.
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Aloui, Sofiane. "Design of 60ghz 65nm CMOS power amplifier." Thesis, Bordeaux 1, 2010. http://www.theses.fr/2010BOR14165/document.
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Le développement d'objets communicants dédiés aux applications Wireless Personal Area Network (WPAN) à 60GHz vise des débits de l'ordre du GBit/sec. Pour satisfaire la contrainte de faible coût, la technologie CMOS silicium est la plus adaptée. L'utilisation de cette technologie est un challenge en soi afin de concilier les aspects « pertes & rendement » vis à vis des contraintes de puissance. Le but de la thèse est de concevoir des amplificateurs de puissance opérant à 60GHz avec la technologie CMOS 65nm de STMicroelectronics. Cette démarche est progressive car il convient d'analyser puis d'optimiser les performances des composants passifs et actifs constituant l'amplificateur de puissance à l'aide des logiciels de simulations électromagnétique et microélectronique. Finalement, des amplificateurs de puissance ont été réalisés et leurs performances répondent au cahier des charges initialement définiTelecommunication industry claims for increasing data rate in wireless communication systems. The major demand of high data rate applications concerns a large panel of home multimedia exchanging data especially for the uncompressed HD data transfer. The 7GHz band around 60GHz is free of use and fulfils the short range gigabit communication requirements. CMOS technology is most appropriate since it drives a fast time to market with a low cost for high integration volume. However, the use of CMOS technology is challenging to satisfy loss and performance trade-off under power constraints. This thesis aims at designing power amplifiers operating at 60GHz with 65nm CMOS technology from STMicroelectronics. This approach is progressive because it is necessary to analyze and optimize the performance of passive and active components constituting the power amplifier using electromagnetic and microelectronics software. Finally, power amplifiers have been made. Their performances met specifications originally defined
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Guimarães, Gabriel Teófilo Neves. "CMOS linear RF power amplifier with fully integrated power combining transformer." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/169084.
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Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais.This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.
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Rabe, Dirk. "Accurate power analysis of integrated CMOS circuits on gate level." [S.l.] : [s.n.], 2001. http://deposit.ddb.de/cgi-bin/dokserv?idn=962733520.
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Yeh, David Alexander. "Multi-gigabit low-power wireless CMOS demodulator." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41168.
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This dissertation presents system and circuit development of the low-power multi-gigabit CMOS demodulator using analog and mixed demodulation techniques. In addition, critical building blocks of the low-power analog quadrature front-ends are designed and implemented using 90 nm CMOS with a targeted compatibility to the traditional demodulator architecture. It exhibits an IF-to-baseband conversion gain of 25 dB with 1.8 GHz of baseband bandwidth and a dynamic range of 23 dB while consuming only 46 mW from a 1 V supply voltage. Several different demodulators using analog signal processor (ASP) are implemented: (1) an ultra-low power non-coherent ASK demodulator is measured to demodulate a maximum speed of 3 Gbps while consuming 32 mW from 1.8 V supply; (2) a mere addition of 7.5 mW to the aforementioned analog quadrature front-end enables a maximum speed of 2.5 Gbps non-coherent ASK demodulation with an improved minimum sensitivity of -38 dBm; (3) a robust coherent BPSK demodulator is shown to achieve a maximum speed of 3.5 Gbps based on the same analog quadrature front-end with only additional 7 mW. Furthermore, an innovative seamless handover mechanism between ASP and PLL is designed and implemented to improve the frequency acquisition time of the coherent BPSK demodulator. These demodulator designs have been proven to be feasible and are integrated in a 60 GHz wireless receiver. The system has been realized in a product prototype and used to stream HD video as well as transfer large multi-media files at multi-gigabit speed.
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Fritzin, Jonas. "CMOS RF Power Amplifiers for Wireless Communications." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71852.
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The wireless market has experienced a remarkable development and growth since the introduction of the first modern mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, the prime goal of the IC manufacturers is to provide low-cost solutions. The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming harder to meet the stringent requirements on linearity, output power, bandwidth, and efficiency at lower supply voltages in traditional PA architectures. This has recently triggered extensive studies to investigate the impact of different efficiency enhancement and linearization techniques, like polar modulation and outphasing, in nanometer CMOS technologies. This thesis addresses the potential of integrating linear and power-efficient PAs in nanometer CMOS technologies at GHz frequencies. In total eight amplifiers have been designed - two linear Class-A PAs, two switched Class-E PAs, and four Class-D PAs linearized in outphasing configurations. Based on the outphasing PAs, amplifier models and predistorters have been developed and evaluated for uplink (terminal) and downlink (base station) signals. The two linear Class-A PAs with LC-based and transformer-based input and interstage matching networks were designed in a 65nm CMOS technology for 2.4GHz 802.11n WLAN. For a 72.2Mbit/s 64-QAM 802.11n OFDM signal with PAPR of 9.1dB, both PAs fulfilled the toughest EVM requirement in the standard at average output power levels of +9.4dBm and +11.6dBm, respectively. The two PAs were among the first PAs implemented in a 65nm CMOS technology. The two Class-E PAs, intended for DECT and Bluetooth, were designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The PAs delivered +26.4 and +22.7dBm at 1.5V and 1.0V supply voltages with PAE of 30% and 36%, respectively. The Bluetooth PA was based on thin oxide devices and the performance degradation over time for a high level of oxide stress was evaluated. The four Class-D outphasing PAs were designed in 65nm, 90nm, and 130nm CMOS technologies. The first outphasing design was based on a Class-D stage utilizing a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5V supply voltage in a 65nm CMOS technology without excessive device voltage stress. Two on-chip transformers combined the outputs of four Class-D stages. At 1.95GHz the PA delivered +29.7dBm with a PAE of 26.6%. The 3dB bandwidth was 1.6GHz, representing state-of-the-art bandwidth for CMOS Class-D RF PAs. After one week of continuous operation, no performance degradation was noticed. The second design was based on the same Class-D stage, but combined eight amplifier stages by four on-chip transformers in 130nm CMOS to achieve a state-of-the-art output power of +32dBm for CMOS Class-D RF PAs. Both designs met the ACLR and modulation requirements without predistortion when amplifying uplink WCDMA and 20MHz LTE signals. The third outphasing design was based on two low-power Class-D stages in 90nm CMOS featuring a harmonic suppression technique, cancelling the third harmonic in the output spectrum which also improves drain efficiency. The proposed Class-D stage creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. A single Class-D stage delivered +5.1dBm at 1.2V supply voltage with a drain efficiency and PAE of 73% and 59%, respectively. Two Class-D stages were connected to a PCB transformer to create an outphasing amplifier, which was linear enough to amplify EDGE and WCDMA signals without the need for predistortion. The fourth outphasing design was based on two Class-D stages connected to an on-chip transformer with peak power of +10dBm. It was used in the development of a behavioral model structure and model-based phase-only predistortion method suitable for outphasing amplifiers to compensate for both amplitude and phase mismatches. In measurements for EDGE and WCDMA signals, the predistorter improved the margin to the limits of the spectral mask and the ACLR by more than 12dB. Based on a similar approach, an amplifier model and predistortion method were developed and evaluated for the +32dBm Class-D PA design using a downlink WCDMA signal, where the ACLR was improved by 13.5dB. A least-squares phase predistortion method was developed and evaluated for the +30dBm Class-D PA design using WCDMA and LTE uplink signals, where the ACLR was improved by approximately 10dB.
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Jörgensen, Sofie. "Modelling of Power Dissipation in CMOS DACs." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1329.
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In this master thesis work, the power dissipation in a current-steering digital- to-analog converter, DAC, has been studied. The digital as well as the analog power dissipation have been modelled in MATLAB and it is shown that the MATLAB models agrees well with simulation results from the circuit simulator (Spectre).
A case study on a DAC designed at Ericsson Microelectronics AB in Linköping has also been done. The DAC is a thermometer-coded current-steering DAC suitable for telecommunications applications. The telecommunication standards that have been studied are asymmetric digital subscriber line, ADSL, very high speed data digital subscriber line, VDSL, and, wireless local area network, WLAN. The conlusion of the study is that the power dissipation of the specific DAC, used in ADSL applications, 75mW, is far from optimized. It can theoretically be lowered to 3.5mW.
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Di, Pede Luigi. "A 1 V low-power CMOS process." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0007/MQ34130.pdf.
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Zuber, Paul. "Wire topology optimisation for low power CMOS." kostenfrei, 2007. http://mediatum2.ub.tum.de/doc/618152/document.pdf.
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Shepherd, Leila Maryam. "Low-power computational interfacing for CMOS ISFETs." Thesis, Imperial College London, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.497646.
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Scholvin, Jörg 1976. "Deeply scaled CMOS for RF power applications." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37904.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 117-140).
The microelectronics industry is striving to reduce the cost, complexity, and form factor of wireless systems through single-chip integration of analog, RF and digital functions. Driven by the requirements of the digital system components, the 90 nm and 65 nm technology nodes are currently emerging as platforms for highly integrated systems. Achieving such integration while minimizing the cost of adding specialized RF modules places high demands on the base CMOS technology. In this regard, the integration of the power amplifier (PA) function becomes an increasing challenge as technology geometries and supply voltages scale down. Gate length (Lg) scaling yields improved frequency response, promising higher power-added efficiency (PAE), a key RF PA consideration. This benefit comes at the cost of a lower drain voltage, which demands a higher output current and thus wider devices in order to produce a given output power level (Po,,). In this work, we have investigated the potential of deeply scaled CMOS for RF power applications, from 0.25 um down to 65 nm. We demonstrate the frequency and power limitations that the different CMOS technologies face, and describe the physical mechanisms that give rise to these limitations.
(cont.) We find that layout considerations, such as splitting a single large device into many smaller parallel devices, become increasingly important as the technology scales down the roadmap, both for power and frequency. We also show that parasitic resistances associated with the back-end wiring are responsible for placing an upper limit on the RF power that can be obtained for a single bond pad. We demonstrate a power density of 31 mW/mm for the 65 nm node, with PAE in excess of 60% at 4 GHz and 1 V. Similar results are obtained in 90 nm, where a peak PAE of 66% was measured at 2.2 GHz and 1 V, with a power density of 24 mW/mm. We find that efficient integrated PA functionality for many applications can be achieved even in a deeply-scaled logic CMOS technology. For low power levels (below 50 mW), we find that the 65 nm CMOS devices offer excellent efficiency (>50%) over a broad frequency range (2-8 GHz). Their RF power performance approaches that of 90 nm devices both in peak PAE and output power density. This is possible without costly PA-specific add-ons, or the use of higher voltage input-output (I/O) device options.
(cont.) However, since I/O devices are often included as part of the process, they represent a real option for PA integration because they allow for higher power densities. The 0.25 /xm I/O device that is available in the 90 nm process, when biased at Vdd = 2.5 V showed excellent results, with a peak PAE of 60% and an output power of 75 mW (125 mW/mm) at 8 GHz.
by Jörg Scholvin.
Ph.D.
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Sjöholm, Olof. "Integrated CMOS Doppler Radar : Power Amplifier Mixer." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129105.
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This thesis is based on a paper by V. Issakov, presented 2009, where a circuit of a merged power amplifier mixer solution was demonstrated. This work takes that solution and simplifies it for the use at a lower frequency. The implementation target is a Doppler radar application in CMOS that can detect humans in a range of 5 to 15 meters. This could be used as a burglar alarm or an automatic light switch. The report will present the background of Issakov’s work, basic theory used and the implementation of the final design. Simulations will show that the solution presented work, with a 15 dB conversion loss. This design performs well compared to reference mixers. With this report it will be shown that it is possible to make a simple and compact Doppler radar system in CMOS.Denna avhandling bygger på en artikel av V. Issakov, presenterad 2009, där en lösning för att sammanslå en effektförstärkare med en mixer till en krets visades. Detta arbete tar denna lösning och förenklar det för användning vid en lägre frekvens. Målet är att implementera en dopplerradar i CMOS som kan detektera människor inom ett avstånd på 5 till 15 meter. Denna radar skulle kunna användas som ett inbrottslarm eller en automatisk strömbrytare. Rapporten kommer att presentera bakgrunden från Issakov’s arbete, grundläggande teori som används och genomförandet av det slutliga kretsschemat. Simuleringar visar att den presenterade lösningen fungerar, med en 15 dB konverteringsförlust. Denna konstruktion presterar väl jämfört med referens mixrar. Med denna rapport visas det att det är möjligt att göra ett enkelt och kompakt dopplerradarsystem i CMOS.
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An, Kyu Hwan. "CMOS RF power amplifiers for mobile wireless communications." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31717.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Laskar, Joy; Committee Member: Cressler, John; Committee Member: Kohl, Paul; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanouil. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Leistad, Tor Erik. "Delay-Fault BIST in Low-Power CMOS Devices." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8877.
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Devices such as microcontrollers are often required to operate across a wide range of voltage and temperature. Delay variation in different temperature and voltage corners can be large, and for deep submicron geometries delay faults are more likely than for larger geometries. This has made delay fault testing necessary. Scan testing is widely used as a method for testing, but it is slow due to time spent on shifting test vectors and responses, and it also needs modification to support delay testing. This assignment is divided into three parts. The first part investigates some of the effects in deep submicron technologies, then it looks at different fault models, and at last different techniques for delay testing and BIST approaches are investigated. The second part suggests a design for a test chip, including a circuit under test (CUT) and BIST logic. The final part investigates how the selected BIST logic can be used to reduce test time and what considerations needs to be made to get a optimal solution. The suggested design is a co-processor with SPI slave interface. Since scan based testing is commonly used today, STUMPS was selected as the BIST solution to use. Assuming that scan already is used, STUMPS will have little impact on the performance of the CUT since it is based on scan testing. During analysis it was found that several aspects of the CUT design affects the maximum obtainable delay fault coverage. It was also found that careful design of the BIST logic is necessary to get the best fault coverage and a solution that will reduce the overall cost. The results shows that a large amount of time can be saved during test by using BIST, but since the area of the circuit increases due to the BIST logic it necessarily dont mean that one will reduce cost on the overall design. Whether or not a BIST solution will result in reduced cost will depend on the complexity of the circuit that is tested, how well the BIST logic fits this circuit, how many internal scan chains can be used, and how fast scan vectors can be applied under BIST. In this case it looks like the BIST logic is not well suited to detect the random hard to detect faults. This results in a large amount of top up patterns. This combined with the large area of the BIST logic makes it unlikely that BIST will reduce cost of this design.
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Rodnunsky, Nelson Lawrence. "Analysis of power dissipations in CMOS circuit designs." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0005/MQ34409.pdf.
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Ardalan, Kasra. "A low-power CMOS fractional-N frequency synthesizer." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0003/MQ40932.pdf.
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Lazaro, Orlando. "CMOS inductively coupled power receiver for wireless microsensors." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51874.
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This research investigates how to draw energy from a distant emanating and alternating (i.e., AC) magnetic source and deliver it to a battery (i.e., DC). The objective is to develop, design, simulate, build, test, and evaluate a CMOS charger integrated circuit (IC) that wirelessly charges the battery of a microsystem. A fundamental challenge here is that a tiny receiver coil only produces mV's of AC voltage, which is difficult to convert into DC form. Although LC-boosted diode-bridge rectifiers in the literature today extract energy from similar AC sources, they can do so only when AC voltages are higher than what miniaturized coils can produce, unless tuned off-chip capacitors are available, which counters the aim of integration. Therefore, rather than rectify the AC voltage, this research proposes to rectify the current that the AC voltage induces in the coil. This way, the system can still draw power from voltages that fall below the inherent threshold limit of diode-bridge rectifiers. Still, output power is low because, with these low currents, small coils can only extract a diminutive fraction of the magnetic energy available, which is why investing battery energy is also part of this research. Ultimately, the significance of increasing the power that miniaturized platforms can output is higher integration and functionality of micro-devices, like wireless microsensors and biomedical implants.
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Alexander, Jins Davis Agrawal Vishwani D. "Simulation based power estimation for digital CMOS technologies." Auburn, Ala, 2008. http://hdl.handle.net/10415/1451.
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Chan, Wai Pan. "Robust low power CMOS methodologies for ISFETs instrumentation." Thesis, Imperial College London, 2010. http://hdl.handle.net/10044/1/6056.
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I have developed a robust design methodology in a 0.18 [Mu]m commercial CMOS process to circumvent the performance issues of the integrated Ions Sensitive Field Effect Transistor (ISFET) for pH detection. In circuit design, I have developed frequency domain signal processing, which transforms pH information into a frequency modulated signal. The frequency modulated signal is subsequently digitized and encoded into a bit-stream of data. The architecture of the instrumentation system consists of a) A novel front-end averaging amplifier to interface an array of ISFETs for converting pH into a voltage signal, b) A high linear voltage controlled oscillator for converting the voltage signal into a frequency modulated signal, and c) Digital gates for digitizing and differentiating the frequency modulated signal into an output bit-stream. The output bit stream is indistinguishable to a 1st order sigma delta modulation, whose noise floor is shaped by +20dB/decade. The fabricated instrumentation system has a dimension of 1565 [Mu] m 1565 [Mu] m. The chip responds linearly to the pH in a chemical solution and produces a digital output, with up to an 8-bit accuracy. Most importantly, the fabricated chips do not need any post-CMOS processing for neutralizing any trapped-charged effect, which can modulate on-chip ISFETs’ threshold voltages into atypical values. As compared to other ISFET-related works in the literature, the instrumentation system proposed in this thesis can cope with the mismatched ISFETs on chip for analogue-to-digital conversions. The design methodology is thus very accurate and robust for chemical sensing.
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Chan, Chung-Kei Thomas. "CMOS class E power amplifier for mobile communications." Thesis, Imperial College London, 2003. http://hdl.handle.net/10044/1/8524.
Full text
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Jose, Sajay. "Design of RF CMOS Power Amplifier for UWB Applications." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/36391.
Full textAbstract:
Ever since the FCC allocated 7.5 GHz (from 3.1 GHz to 10.6 GHz) for ultra wideband (UWB) technology, interest has been renewed in both academic and industrial circles to exploit this vast spectrum for short range, high data rate wireless applications. The great potential of UWB lies in the fact that it can co-exist with the already licensed spectrum users and can still pave the way for a wide range of applications.
However, this wide bandwidth complicates the circuit level implementation of key RF blocks like the power amplifier (PA), transmit/receive switch, low noise amplifier (LNA) and mixers in an UWB transceiver. Though expensive technologies like SiGe or GaAs have been used for transceiver realizations, the ultimate goal is to have a single-chip, low-cost solution which can only be achieved by using CMOS technology. Nevertheless, some of the inherent limitations of CMOS like lower fT of transistors make the design of UWB circuits in CMOS an extremely challenging task.
Two proposals- Multi-Band OFDM and Direct-Sequence CDMA have been put before the IEEE 802.15.3a task group to decide on the industry standard for the commercial deployment of this technology. Though the debate on which standard is better has not been resolved, proponents of both the groups have already begun to develop prototypes of their respective proposals.
This thesis describes the design of a key RF block in the UWB transceiver - the Power Amplifier. For the first part of this work, a PA suitable for MB-OFDM specifications was designed and fabricated in TSMC 0.18um CMOS technology. The class-AB PA is able to cover the lower UWB frequency band from 3.1 GHz to 4.75 GHz and delivers an output power of -2 dBm at 4 GHz. Simulated results show a gain of 19±2 dB achieved over the entire band and the PA consumes 36.54 mW from a 1.8V supply.
In the second part of this work, a PA that meets the DS-CDMA specifications was designed and fabricated. This PA operates in the class-AB regime, delivering an output power of -4.2 dBm with input-1dB compression point at -22 dBm. Complete design and implementation was done using TSMC 0.18um CMOS technology and it consumes a very low power of 25 mW, while realizing a flat gain of 19±1 dB across the whole band of operation. All the above mentioned results are from simulations in SpectreRF and measurements are yet to be taken. Additional features like power ON/OFF scheme and output impedance control has also been incorporated in the design.Master of Science
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Lee, Ockgoo. "High efficiency switching CMOS power amplifiers for wireless communications." Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/37145.
Full textAbstract:
High-efficiency performance is one of the most important requirements of power
amplifiers (PAs) for wireless applications. However, the design of highly efficient CMOS
PAs for watt-level applications is a challenging task. This dissertation focuses on the
development of the design method for highly efficient CMOS PAs to overcome the
fundamental difficulties presented by CMOS technology.
In this dissertation, the design method and analysis for a high-power and highefficiency
class-E CMOS PA with a fully integrated transformer have been presented.
This work is the first effort to set up a comprehensive design methodology for a fully
integrated class-E CMOS PA including effects of an integrated transformer, which is
very crucial for watt-level power applications. In addition, to improve efficiency of
cascode class-E CMOS PAs, a charging acceleration technique is developed. The method
accelerates a charging speed to turn off the common-gate device in the off-state, thus
reducing the power loss. To demonstrate the proposed cascode class-E PA, a prototype
CMOS PA was implemented in a 0.18-μm CMOS process. Measurements show an
improvement of approximately 6% in the power added efficiency. The proposed cascode
class-E PA structure is suitable for the design of high-efficiency class-E PAs while it
reduces the voltage stress across the device.
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Östberg, Gustav. "A Comparative Study of Efficient Power Amplifiers in CMOS." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-17409.
Full textAbstract:
During later years communication schemes for handheld devices have increased in complexity due to the desire to increase the throughput, i.e. the amount of information sent over a medium simultaneously. Increasing throughput can be accomplished, not only by modulating the phase or frequency, but also the amplitude. This leads to tougher requirements on the power amplifier. The conventional power amplifiers, which have the ability to follow the envelope of the carrier, are inefficient. This thesis aims to compare two old but revived architectures which exploit high-efficiency amplifiers and still have a linear relationship between the input and output. The architectures; the Polar Linearization Technique and Outphasing share the same foundation. Based on literature, the polar technique have been more successful of employing examples fufilling communication standards. The polar technique is also more versatile regarding power combiners, distortion correction and alternative implementations. The simulations performed in this thesis results show that the polar amplifier is less sensitive to process variations and has higher maximum efficiency. On the other hand, the outphasing topology have the highest linearity figures.
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Wunderlich, Richard Bryan. "CMOS gate delay, power measurements and characterization with logical effort and logical power." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31652.
Full textAbstract:
Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Paul Hasler; Committee Member: David V Anderson; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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"Adiabatic low power CMOS." 1998. http://library.cuhk.edu.hk/record=b5889728.
Full textAbstract:
by Kelvin Cheung Ka Wai.Thesis submitted in: June 1997.
Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.
Includes bibliographical references.
ACKNOWLEDGEMENTS --- p.i
ABSTRACT --- p.ii
TABLE OF CONTENTS --- p.iii
LIST OF FIGURES --- p.vi
TIST OF TABLES --- p.viii
Chapter 1. --- INTRODUCTION --- p.1-1
Chapter 1.1 --- Introduction --- p.1-1
Chapter 1.2 --- Objective --- p.1-1
Chapter 1.3 --- Static CMOS Logic and Dynamic Logic --- p.1-1
Chapter 1.3.1 --- static CMOS logic circuit --- p.1-1
Chapter 1.3.2 --- Dynamic logic --- p.1-2
Chapter 1.4 --- Power Consumption in Static CMOS Integrated Circuit --- p.1-4
Chapter 1.4.1 --- Static power dissipation --- p.1 -4
Chapter 1.4.2 --- Dynamic power dissipation --- p.1 -6
Chapter 1.4.2.1 --- Short circuit current --- p.1 -6
Chapter 1.4.2.2 --- Charging and discharging of load capacitances --- p.1-6
Chapter 1.4.2.3 --- Total power consumption --- p.1-8
Chapter 1.5 --- Adiabatic Logic --- p.1-8
Chapter 1.5.1 --- Low power electronics --- p.1-8
Chapter 1.5.2 --- History of adiabatic logic --- p.1 -9
Chapter 1.6 --- Resources --- p.1-10
Chapter 1.6.1 --- Computing instrument --- p.1-10
Chapter 1.6.2 --- CAD tools --- p.1-10
Chapter 1.6.3 --- Fabrication --- p.1-11
Chapter 1.7 --- Organisation of the Thesis --- p.1-11
Chapter 2. --- BACKGROUND THEORIES --- p.2-1
Chapter 2.1 --- Limit of energy dissipation --- p.2-1
Chapter 2.2 --- Reversible Electronics --- p.2-1
Chapter 2.2.1 --- Reversibility --- p.2-1
Chapter 2.2.2 --- Adiabatic Switching --- p.2-3
Chapter 2.2.2.1 --- Conventional Charging --- p.2-3
Chapter 2.2.2.2 --- Adiabatic Charging --- p.2-4
Chapter 2.2.3 --- Reversible devices --- p.2-5
Chapter 2.3 --- Compatibility to CMOS Logic --- p.2-6
Chapter 3. --- ADIABATIC QUASI-STATIC CMOS --- p.3-1
Chapter 3.1 --- Swinging between 0 and 1 by Harmonic Motion --- p.3-1
Chapter 3.1.1 --- Starting from a simple pendulum --- p.3-1
Chapter 3.1.2 --- Inductor-capacitor oscillator --- p.3-2
Chapter 3.2 --- Redistribution of Charge --- p.3-3
Chapter 3.3 --- Adiabatic Quasi-static Logic --- p.3-4
Chapter 3.3.1 --- False reversible inverter --- p.3-4
Chapter 3.3.2 --- Adiabatic inverter --- p.3-5
Chapter 3.3.3 --- Effective capacitance --- p.3-7
Chapter 3.3.4 --- Logic alignment --- p.3-8
Chapter 3.3.5 --- Cascading the adiabatic inverters --- p.3-10
Chapter 3.3.5.1 --- Compensated cascading --- p.3-10
Chapter 3.3.5.2 --- Balanced cascading --- p.3-11
Chapter 3.4 --- Frequency Control --- p.3-12
Chapter 3.5 --- Compatibility of AqsCMOS with Static CMOS Logic --- p.3-13
Chapter 4. --- ADIABATIC QUASI-STATIC CMOS INVERTERS --- p.4-1
Chapter 4.1 --- Design --- p.4-1
Chapter 4.1.1 --- Realisation of current direction control device --- p.4-1
Chapter 4.1.2 --- Implementation of AqsCMOS inverter by current direction control device --- p.4-2
Chapter 4.1.3 --- Layout --- p.4-3
Chapter 4.1.3.1 --- Horizontal Transistor Diode --- p.4-3
Chapter 4.1.3.2 --- Transistor pair --- p.4-9
Chapter 4.2 --- Capacitance Calculation --- p.4-9
Chapter 4.2.1 --- Non-switching device --- p.4-10
Chapter 4.2.2 --- Switching device --- p.4-11
Chapter 4.3 --- Clocking Scheme --- p.4-13
Chapter 4.4 --- Energy Loss of AqsCMOS inverter --- p.4-14
Chapter 5. --- ADIABATIC CLOCKS GENERATOR --- p.5-1
Chapter 5.1 --- Introduction --- p.5-1
Chapter 5.2 --- Full Adiabatic Clocks Generator --- p.5-1
Chapter 5.2.1 --- Sizes of the transistors used --- p.5-2
Chapter 5.2.2 --- Energy consumption of full adiabatic clocks generator --- p.5-3
Chapter 5.3 --- Half Adiabatic Clocks Generator --- p.5-4
Chapter 5.3.1 --- Transistor sizing --- p.5-5
Chapter 5.3.2 --- Energy consumption of the half adiabatic clock generator --- p.5-5
Chapter 5.3.3 --- Weakness of the half adiabatic clocks generator --- p.5-6
Chapter 5.4 --- Automatic Adiabatic Clocks Generator --- p.5-6
Chapter 5.4.1 --- Operation of automatic adiabatic clocks generator --- p.5-7
Chapter 5.4.2 --- Energy consumption of automatic adiabatic clocks generator --- p.5-9
Chapter 6. --- EVALUATION --- p.6-1
Chapter 6.1 --- Introduction --- p.6-1
Chapter 6.2 --- Simulation Results --- p.6-1
Chapter 6.2.1 --- Adiabatic clocks generators --- p.6-1
Chapter 6.2.2 --- Adiabatic quasi-static CMOS inverters --- p.6-4
Chapter 6.2.2.1 --- Functional evaluation --- p.6-4
Chapter 6.2.2.2 --- Performance evaluation --- p.6-6
Chapter 6.3 --- Test Circuit - Pendulum --- p.6-8
Chapter 6.3.1 --- Layout --- p.6-8
Chapter 6.3.2 --- Test circuit of pendulum --- p.6-10
Chapter 6.3.3 --- Module 1 - Full adiabatic clocks generator (fclk) --- p.6-11
Chapter 6.3.4 --- Module 2 - Half adiabatic clocks generator (hclk) --- p.6-13
Chapter 6.3.5 --- Module 3 to 5- Adiabatic inverter chains --- p.6-14
Chapter 6.3.5.1 --- DC characteristics --- p.6-14
Chapter 6.3.5.2 --- AC characteristics --- p.6-14
Chapter 6.3.6 --- Power dissipation --- p.6-17
Chapter 7 --- CONCLUSIONS --- p.7-1
Chapter 7.1 --- Introduction --- p.7-1
Chapter 7.2 --- Design --- p.7-1
Chapter 7.2.1 --- Adiabatic quasi-static CMOS logic --- p.7-1
Chapter 7.2.2 --- Adiabatic quasi-static CMOS inverters --- p.7-2
Chapter 7.2.3 --- Adiabatic clocks generator --- p.7-2
Chapter 7.3 --- Function --- p.7-3
Chapter 7.4 --- Power Dissipation --- p.7-3
Chapter 7.5 --- Discussion --- p.7-3
Chapter 7.6 --- Further Development --- p.7-3
Chapter 7.7 --- Conclusion --- p.7-4
Chapter 8. --- REFERENCES --- p.8-1
APPENDIX I TABLE OF PTN LAYOUT PENDULUM --- p.I-1
APPENDIX II PHOTOGRAPHS OF PENDULUM --- p.II-1
29
Machado, Pedro Miguel Silva. "Ultra-Low-Power CMOS Oscillator." Dissertação, 2021. https://hdl.handle.net/10216/135340.
Full textAbstract:
Atualmente, devido ao constante avanço tecnológico e procura de inovação, a grande maioria dos circuitos que compõem dispositivos que utilizamos no nosso dia-a-dia, têm vindo a diminuir o seu tamanho. Estes são inseridos em circuitos integrados, onde a área e o consumo energético são limitações significativas.
Um grande número de aplicações e dispositivos, necessitam de um clock estável para operar corretamente, sendo a solução mais comum para gerar tal frequência um oscilador. Em função da mudança atual, o oscilador convencional teve de sofrer mudanças no seu design de modo a acompanhar a indústria eletrónica. Tais alterações tornaram os osciladores em geral menos precisos comparativamente a osciladores de cristal, mas mais eficientes em termos energéticos, área ocupada e custo.
Nesta tese, é apresentado um oscilador em anel de muito baixo consumo, onde se pretende eliminar qualquer componente externo que envolva custos adicionais. Sendo um dos principais desafios, o trade-off entre a precisão da frequência de saída e o consumo energético. Adicionalmente, osciladores inseridos em circuitos integrados tendem a sofrer desvios de frequência com variações PVT. A estratégia apresentada, passa por contruir blocos que forneçam ao oscilador correntes e tensões estáveis, de modo a compensar tais variações.
Desenhado na tecnologia CMOS 0.18nm, inclui também um circuito de trimming, tornando possível a calibração do processo pós-fabrico.Currently, due to the constant technological advancement and search for innovation, the vast majority of the circuits that compose devices that we use in our day-to-day activities, have been decreasing in size. These are inserted in integrated circuits, where the area and energy consumption are major limitations. Also, a large number of applications and devices require a stable clock to operate correctly, being the use of an oscillator the most common solution to generate such frequency. Due to the current change, the conventional oscillator had to overcome changes in its design in order to keep up with the electronics industry. Such changes made oscillators in general less accurate compared to crystal oscillators, but more efficient in terms of energy, occupied area and cost. In this thesis, a very low consumption ring oscillator is presented, where it is intended to eliminate any external component that involves additional costs. One of the main challenges is the trade-off between the precision of the output frequency and energy consumption. Additionally, oscillators inserted in integrated circuits tend to suffer frequency deviations with PVT variations. The presented strategy involves building blocks that supply the oscillator with stable currents and voltages, in order to compensate for such variations. Designed using CMOS 0.18nm technology, it also includes a trimming circuit, making it possible to calibrate the process in post-fabrication.
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Guo, Chuen-Zhu, and 郭純助. "2.4GHz CMOS Linearized Power Amplifier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/77729151354106649363.
Full textAbstract:
碩士國立成功大學
微電子工程研究所碩博士班
91
This thesis presents a 2.4GHz ISM-band CMOS linearized power amplifier. Useing two frames of linearization to improve linearity of power amplifier. This thesis consists of two part. Part I introduced the theory and technique of design about power amplifier. Part II are examples of linearized circuit, which will use the frames of linearized bias circuit and auxiliary transistor to compensate nonlinear factors to improve linearity of power amplifier. In the frames of linearized bias circuit, the linearized bias circuit can increase the voltage of gate form 0.5V to 0.68V. The designed results are 12.5dB in power gain, 28% in PAE, P1dB rising up from 0.7dBm to 12.9dBm, and IMD of 2-oder＆3-order harmonic to improve linearity above 5dB. In the frames of auxiliary transistor to compensate nonlinear factors, the designed results are 20.7dB in power gain, 26% in PAE, P1dB rising up from 0.43dBm to 14.035dBm, and IMD of 2-oder＆3-order harmonic to improve linearity above 6dB~24dB. The improving linearity of circuit is conspicuous.
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LIN, SHIN-JUNG, and 林欣蓉. "Low-power CMOS multiplier complier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/80826445899773491677.
Full textAbstract:
碩士國立中正大學
電機工程研究所
91
Abstract In recent year，electronic portable devices，such as mobile phones，PDA，and MP3，are commonly used。Therefore，the demands for High speed and low power VLSI arise。Digital signal processors(DSP) are commonly used on these electronic applications。As a result，how to minimize power consumption without losing speed performance is very important。Multiplier plays the most important role on DSP，since it usually organizes the critical path of DSP。Thus，the low power and high speed characteristics of multiplier become more and more important。Minimizing glitches is an suitable method to reduce the power consumption while the speed performance is not sacrificed。 Many papers have mentioned this point。But seldom papers provide efficient and reliable methods to measure glitches。We propose a new way to measure the glitch number，which makes the relation between glitches and power consumption clear and concrete。 We start at Wallace tree compressors first in circuit aspect。We improve the original tree architecture to minimize power consumption by equalizing each path inside the Wallace tree。Next，we propose a new dynamic Booth encoder/decoder to reduce the glitches at partial products。Finally，we replace the final static CPA with dynamic CPA[28] to reduce the glitches produced by static CPA and promote the CPA speed performance。We compare the simulation result of both our new design and paper [2] to prove that new design has a better speed and power performance over [2]。
32
Machado, Pedro Miguel Silva. "Ultra-Low-Power CMOS Oscillator." Master's thesis, 2021. https://hdl.handle.net/10216/135340.
Full textAbstract:
Atualmente, devido ao constante avanço tecnológico e procura de inovação, a grande maioria dos circuitos que compõem dispositivos que utilizamos no nosso dia-a-dia, têm vindo a diminuir o seu tamanho. Estes são inseridos em circuitos integrados, onde a área e o consumo energético são limitações significativas.
Um grande número de aplicações e dispositivos, necessitam de um clock estável para operar corretamente, sendo a solução mais comum para gerar tal frequência um oscilador. Em função da mudança atual, o oscilador convencional teve de sofrer mudanças no seu design de modo a acompanhar a indústria eletrónica. Tais alterações tornaram os osciladores em geral menos precisos comparativamente a osciladores de cristal, mas mais eficientes em termos energéticos, área ocupada e custo.
Nesta tese, é apresentado um oscilador em anel de muito baixo consumo, onde se pretende eliminar qualquer componente externo que envolva custos adicionais. Sendo um dos principais desafios, o trade-off entre a precisão da frequência de saída e o consumo energético. Adicionalmente, osciladores inseridos em circuitos integrados tendem a sofrer desvios de frequência com variações PVT. A estratégia apresentada, passa por contruir blocos que forneçam ao oscilador correntes e tensões estáveis, de modo a compensar tais variações.
Desenhado na tecnologia CMOS 0.18nm, inclui também um circuito de trimming, tornando possível a calibração do processo pós-fabrico.Currently, due to the constant technological advancement and search for innovation, the vast majority of the circuits that compose devices that we use in our day-to-day activities, have been decreasing in size. These are inserted in integrated circuits, where the area and energy consumption are major limitations. Also, a large number of applications and devices require a stable clock to operate correctly, being the use of an oscillator the most common solution to generate such frequency. Due to the current change, the conventional oscillator had to overcome changes in its design in order to keep up with the electronics industry. Such changes made oscillators in general less accurate compared to crystal oscillators, but more efficient in terms of energy, occupied area and cost. In this thesis, a very low consumption ring oscillator is presented, where it is intended to eliminate any external component that involves additional costs. One of the main challenges is the trade-off between the precision of the output frequency and energy consumption. Additionally, oscillators inserted in integrated circuits tend to suffer frequency deviations with PVT variations. The presented strategy involves building blocks that supply the oscillator with stable currents and voltages, in order to compensate for such variations. Designed using CMOS 0.18nm technology, it also includes a trimming circuit, making it possible to calibrate the process in post-fabrication.
33
Lin, Hong-Shang, and 林宏尚. "CMOS and SiGe Power Amplifiers Using Power Combining Transformers." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/786z9x.
Full textAbstract:
碩士國立臺北科技大學
電腦與通訊研究所
99
The paper presented of 1.9GHz full-integrated power amplifiers, which is using CMOS and BiCMOS processes, for WCDMA and TD-SCDMA applications. The power transistors of power amplifier used cascode to enhance breakdown voltage and make the amplifier operated in zero voltage switching condition. The DC power consumption can be reduced to a minimum, so that the efficiency of the power transistor achieves the best state. Last, the power combining transformers is using to improve output power. The CMOS power amplifier using 3x1:2 power combining transformer. The driver stage used self-bias configuration to provide DC bias and input power of the power stage. The BiCMOS power amplifier using 1x1:2 power combining transformer. The driver stage used the single end circuit and through the inter-stage transformer, the differential signal is converted to drive the power stage. Finally, the power combining transformer is using to combine the output power. The amplifier used active temperature compensation circuit to control the temperature to avoid the high temperature lead the power amplifier working abnormally.
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Chang, Shan-En, and 張善恩. "CMOS Wideband Power Amplifier and Pulse Modulated Power Amplifier." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/rm39v7.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
105
As the development of communication systems, the industry continues to request more frequency bands. Therefore, the FCC releases 900 MHz, 2.4 GHz and 5.8 GHz bands as the industrial scientific medical band（ISM Band）for openly use. In order to simultaneously transmitting signals in multiple frequency bands, there should be a broadband power amplifier in a transmitter. In the communication systems, there are variety of modulation techniques. The radio frequency power amplifier is an important component of the transmitter and plays a crucial role in communication systems. It dominates about 60% to 90% of the energy consumptions in the RF transceiver. Therefore, the power-added efficiency, affecting the degree of the power consumption, is distinctly important. This thesis presents the CMOS power amplifiers that are implemented in 0.13 μm CMOS technology. In order to overcome CMOS transistors’ low breakdown voltage and improve the power and efficiency, this thesis adopts the stacked transistors to design power amplifier. The first wideband PA is one stage with, high power and high efficiency for ISM band. Circuit architecture uses four-stacked transistors and network synthesis broadband matching. From the simulation, this PA achieves a 1-dB bandwidth of 2 to 6 GHz and 3-dB bandwidth of 1.6 to 6.3 GHz. In the 1-dB bandwidth, this PA achieves P1dB of 28.1 to 29.1 dBm and PAE of 35.27 to 48.66 %；Psat of 30.9 to 31.9 dBm and maximum PAE of 46.61 to 50.15 %. The CMOS PA is able to cover ISM Band 2.4 GHz（2400 ~ 2500 MHz）and 5.8 GHz（5725 ~ 5875 MHz）. The second part of PA is CMOS pulse modulation power amplifier with CMOS pulse modulator, which uses on-off keying technology, and two-stage high efficiency power amplifier. From the simulation, this OOK modulator achieves S11 and S22, less than - 10 dB, with 590 MHz bandwidth. The 3-dB bandwidth of S21 is 500 MHz（1700 ~ 2200 MHz）. This pulse modulated power amplifier achieves a power gain of 34.0, output power of 28.0 dBm and PAE of 58.9 % when frequency is 1.9 GHz and input power is – 6 dBm.
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"Millimeter-wave CMOS power amplifiers design." UNIVERSITY OF CALIFORNIA, BERKELEY, 2009. http://pqdtopen.proquest.com/#viewpdf?dispub=3353454.
Full text
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Hsieh, Chih-Hsiang, and 謝智翔. "High Linearity RF CMOS Power Amplifiers." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/97599524223775530145.
Full text
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Lin, Jhen-Hong, and 林振宏. "Design of CMOS Doherty Power Amplifier." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/gmvnxx.
Full textAbstract:
碩士國立中山大學
通訊工程研究所
102
This thesis presents a fully integrated transformer-based Doherty power amplifier in a standard 90 nm CMOS process. Doherty architecture has been proposed to enhancement the average efficiency of the transmitter, and improve efficiency under the back-off. There are two parts of this thesis, the first part is to introduce a traditional linearly power amplifier, and realize a fully integrated class A power amplifier at 2.4 GHz. The cascode structure is used in the power cells since the power amplifier is a fully differential design, a balun is utilized to convert between single-ended and differential signals, and to serve as an impedance matching network. The second part is to realize a fully integrated 2.4 GHz Doherty power amplifier. A main amplifier and an auxiliary amplifier are integrated to have a combined output power. A asymmetrical series combining transformer is used to achieve uneven Doherty operation. The Doherty architecture demonstrates efficiency enhancement under back-off, which is important for high peak-to-average-power-ratio communication systems.
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Tsai, Chin-Wei, and 蔡智偉. "Development of RF CMOS Power Amplifier." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/r8aca6.
Full textAbstract:
碩士國立臺北科技大學
自動化科技研究所
94
This thesis presents the development of RF CMOS power amplifier which is implemented by UMC CMOS 0.18-um 1P6M process. A class E power amplifier and a cascode power amplifier are designed to be used in bluetooth system and wireless sensor network system, respectively. In the matching network design, the input matching network is designed for maximum gain transducer by conjugate matching and the output matching is designed for maximum power transducer by load-pull matching. The simulation results of class E power amplifier whose input matching network and output matching network are on the chip and off the chip respectively are output power of 21.214dBm, PAE of 37.765％ and power gain of 17.214dB at 2.4GHz. And the cascade power amplifier which is a fully chip realized an overall PAE of 20% with output power of 3.583dBm and had power gain of 7.583dB at 2.4GHz. In general, the effect of layout is not considered in the simulation of circuit level. This thesis considers the parasitic effect after layout to obtain more accurate results of simulation.
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Gopinath, Anoop. "Low-power hybrid TFET-CMOS memory." Thesis, 2018. https://doi.org/10.7912/C27947.
Full textAbstract:
Indiana University-Purdue University Indianapolis (IUPUI)Gopinath, Anoop. M.S.E.C.E., Purdue University, May 2018. Low-Power Hybrid TFET-CMOS Memory. Major Professor: Maher E. Rizkalla. The power consumption and the switching speed of the current CMOS technology have reached their limits. In contrast, architecture design within computer systems are continuously seeking more performance and e ciency. Advanced technologies that optimize the power consumption and switching speed may help deliver this e ciency. Indeed, beyond CMOS technology may be a viable approach to meeting the ever increasing need for low-power design. These technology includes devices such as Tunnel Field E ect Transistor (TFET), Graphene based devices such as GFET and GRNFET and FinFET. However, the low cross-sectional area of the channel asso- ciated with smaller technology nodes brings with it the challenges associated with leakage current below the threshold. Mitigating these challenges with devices such as TFETs may allow higher levels of integration, faster switching speed and lower power consumption. This thesis investigates the use of Gallium Nitride (GaN) TFET devices at 20nm for memory cells. These cells can be used in the L1 data cache of the Graphic Processing Units (GPU) thereby minimizing the static power and the dynamic power within these memory systems. The TFET technology was chosen since it has a low subthreshold slope of nearly 30mV/decade. This enables the TFET-based cells to function with a 0.6V supply voltage leading to reduced dynamic power consumption and leakage current when compared to the current CMOS technology. The results suggest that there are bene ts in pursuing an integrated TFET-based technology for Very Large Scale Integrated Circuit (VLSI) design. These bene ts are demonstrated using simulation at the schematic-level using Cadence Virtuoso.
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Chang, Che-Kun, and 張哲昆. "77~110GHz 40nm-CMOS Power Amplifier." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/ev83k8.
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碩士國立交通大學
電子研究所
107
In wireless communication system, low noise amplifier and power amplifier is the most front end and the most back end circuits. There are different design cosideration but both of them are important. Output power of power amplifier decide driving ability of amplifier. Low noise amplifier impact SNR of all system. In CMOS power amplifier, low output power of transistor and loss of passive circuit make output power insufficient. To overcome these issues, this thesis provide a 77~110GHz CMOS power amplifier. By in phase power combiner to combine eight way output power of transistor make output power 9dB larger than only one transistor and it can lower the length of power combiner greatly by capacitively load than quarter wave impedance transform to minimize the loss. Entire loss of all output network is only 2.5dB for simulation. Output power will be 6.5dB bigger than only one transistor.
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Tsay, Ruey Wen, and 蔡瑞文. "Power estimation for CMOS VLSI circuits." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/97871619822447698308.
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碩士國立成功大學
電機工程研究所
81
Due to the power dissipation. CMOS technology has been widely appiled to VLSI circuits. During the design of CMOS VLSI circuits. the current flow between power and ground (P/G) leads to the problems of voltage drop and metal migration. To design a reliable CMOS VLSI circuits, it is necessary to adopt an accurate and fast time-domain current simulator. Hence, the analysis of transient current in CMOS circuits is becoming a major concern nowadays. Rouatbi proposed a piece-wise linear current waveform model, and used this model to estimate the amount of the supply current in CMOS circuits. In this thesis, some parameters in Rouatbi's basic capacitance current model are modified firstly. Then, several equations about the parameters in Rouatbi's model are derived. Finally, a modified current model with considering the ramp input effect is presented to speed up the current estimation. In this proposed current model, the short-channel effects, input rise time, and circuit current are all taken into account. Experimental results show that the speed and correctness of current estimation are both improved.
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Chan, Chin-Tung, and 詹欽棟. "Design of RF CMOS Power Amplifiers using Power Combining Approach." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/65169271015920526583.
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碩士國立清華大學
電子工程研究所
101
Abstract The goal of the thesis is to design and implement RF power amplifiers in CMOS technology. The thesis consists of three parts. The first part introduces the basics of power amplifier theories and some common design techniques. In the second part, three power amplifiers (PAs) are designed for 24-GHz systems and implemented in a LP 90-nm CMOS technology. The first PA adopts high efficient transformers to improve maximum power-added-efficiency (PAE). This PA achieves a measured saturated output power (P_sat) of 15.2 dBm, an output 1-dB compression point (P_1dB) of 10.7 dBm, a power-added-efficieny (PAE) of 17.4%, and a linear gain of 10.5 dB at 25 GHz, with a chip size of 0.975 × 0.71 〖mm〗^2. The second PA utilizes flip-chip configuration to assist heat dissipation. This PA achieves a simulated P_sat of 13.4 dBm, a P_1dB of 11.3 dBm, a PAE of 12.7%, and a linear gain of 10.3 dB at 24 GHz, with a chip size of 0.82 × 0.71 〖mm〗^2. Finally, the third K-band PA with the proposed adaptive-bias technique is fabricated. According to the simulation, the proposed PA consumes 367 mW at quiescent state and offers 20.5% PAE at the P_1dB. The PA achieves a simulated P_sat of 22.3 dBm, a P_1dB of 20.5 dBm, a PAE of 24.9%, and a linear gain of 23.4 dB at 24 GHz with the chip size of 1 × 0.74 〖mm〗^2. In the third part, a 77-GHz PA is implemented in a LP 90-nm CMOS technology. The PA achieves a measured P_sat of 13.2 dBm, a P_1dB of 7.6 dBm, a PAE of 2.4% , and a linear gain of 2.4 dB at 77 GHz. The chip size is only 0.63 × 0.5 〖mm〗^2 including all of the testing pads. The simulation results agrees well with the measurement results for the PAs. In addition, all of the PAs demonstrate high performance compared with the prior arts of the CMOS PAs operating at the frequencies at 24 GHz and 77 GHz. Index Terms –CMOS, Power amplifier, K-band, W-band, RF amplifier, Monolithic microwave integrated circuit (MMIC).
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Lu, Chun-Wei, and 盧鈞瑋. "Design of 2.4GHz CMOS linearized Power Amplifier with power control." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/51544684000610690090.
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碩士長庚大學
電子工程研究所
93
Today’s power amplifiers are implemented in GaAs, HBT, LDMOS, and BiCMOS technologies. However, more and more communication system is fabricated in CMOS technology. For this reason, a single chip transceiver includes an integrated CMOS power amplifier. In this work, design and implementation of a power amplifier are described. This paper presents a 2.4GHz CMOS linearized power amplifier with variable output power fabricated in TSMC 0.18μm 1P6M CMOS process. The PA has linear power gain of 17.54dB, output P1dB of 13.64dBm and power added efficiency (PAE) of 32.86%, and linearized with multi-gate auxiliary transistor. And the controllable output power can reduce the effect to human causing by the EM wave.
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Nai, JI-Kang, and 能繼康. "Research of CMOS RF Power Amplifier with Power Efficiency Improvement." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/09750270580288803579.
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碩士國立臺灣大學
電信工程學研究所
104
In this thesis, the theory of switchmode power amplifier (PA) is implemented in the design of CMOS RF power amplifier. The aim of the design is to improve the efficiency of power amplifier while keeping high out output power. A 5 GHz class-F-1 mode power amplifier based on transformer using the TSMC 180-nm CMOS process is presented first. In this design, the conventional output matching networks of LC-tank are replaced by the transformer with a shunt capacitor to increase the power density. The measured result shows 13.2-dB small signal gain, and 25.4-dBm saturation power (Psat) and 41% peak power added efficiency (PAE). While the output power at 1-dB compression point (OP1dB) is 24.6 dBm, and the PAE at OP1dB is 35%. Then a power amplifier works from 2.8 to 6 GHz is also designed using 180-nm CMOS process. The output matching network of the proposed PA achieves wideband fundamental matching and 2nd and 3rd harmonic impedance matching to improve the efficiency simultaneously. The measured result shows 10.4-to-13.4-dB small signal gain, and 20.8-to-22.1-dBm Psat, and 37-44% peak PAE. In the meanwhile the OP1dB is 20.3-21.4 dBm, and the PAE at OP1dB is 32-38%.
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Moreira, Alfredo do Vale Ferreira. "Estudo comparativo de multiplicadores CMOS Low-Power." Dissertação, 2009. http://hdl.handle.net/10216/60406.
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Moreira, Alfredo do Vale Ferreira. "Estudo comparativo de multiplicadores CMOS Low-Power." Master's thesis, 2009. http://hdl.handle.net/10216/60406.
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Tseng-Hsin, Chiu. "A CMOS 2.4GHz Class-E Power Amplifier." 2003. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611295360.
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Cheng-Chang, Huang, and 黃成昌. "Low-Power CMOS Continuous-Time Filter Design." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/46848689851680571071.
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碩士大同工學院
電機工程研究所
86
Design considerations for low-power continuous-time current-mode filters are presented in the thesis. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and a MOSFET gate capacitance. Integrator excess phase shift is reduced by using balanced signals path, and open-loop gain is increased by using low-voltage cascode amplifiers. Replacing the ideal current source with temperature-independent current bias generator, the unity gain of the integrator will not vary with process and temperature. Consequently, the filter need not be tuned. The lowpass prototypes provided 100KHz-2MHz tunable bandwidth. For ladder filters derived from doubly terminated LC prototypes, HSPICE simulations predict a -3dB bandwidth of 470 KHz for a fifth-order Butterworth low-pass filter. Power dissipation is 17.6 uW/pole with 1.6 V power supply.
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Chen, Ming-Jia, and 陳明家. "Design of Low Power CMOS Prescaler Chip." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/20120048650580766118.
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碩士國立勤益科技大學
電子工程系
99
In modern communication systems, the frequency synthesizer is one of the most important circuits. The maximum frequency of a synthesizer is limited by the frequency divider and voltage-controlled oscillator (VCO). The characteristics of frequency divider dominate the performance of frequency synthesizer. We propose two new types of dual-modulus 2/3 dividers. In addition, a 1/2/3 divider modular with programmable capability is improved in this thesis. First, a low-power 2/3 divider Type-1 is designed to reduce in charge sharing. The measured results show that the experimental Type-1 chip has advantages of low voltage and low power consumption. Another design, 2/3 divider Type-2 reduces power consumption by using D-Flip-flop of dynamic floating input techniques. The post-simulation results show that power consumption is lower than Type-1 design especially for low-voltage operation. Finally, 1/2/3 divider modular with programmable capability is improved in reductions of transistor number and chip area. We had realized a 4/5 divider and 16/17 divider by composed of several 2/3 dividers in cascaded. The all simulations and chip implementations are based on TSMC 0.18-m CMOS technology.
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Oliveira, Daniel José Azevedo. "CMOS-RF power amplifier for wireless communications." Dissertação, 2009. http://hdl.handle.net/10216/66786.
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