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Journal articles on the topic 'CMOS power'

Author: Grafiati

Published: 4 June 2021

Last updated: 12 February 2022

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1

GABARA, THAD. "PULSED LOW POWER CMOS." International Journal of High Speed Electronics and Systems 05, no. 02 (June 1994): 159–77. http://dx.doi.org/10.1142/s0129156494000097.

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A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipolar, diodes, JFETs are not required to generate this low power capability; (4) the Conventional CMOS process is used to fabricate the circuit; (5) the same physical layout can be used either as a PPS CMOS circuit or as a Conventional CMOS circuit; (6) the device count is the same as that of Conventional CMOS; (7) PPS CMOS uses quasistatic logic levels; (8) capacitive coupling is used to store and restore the contents of a memory cell; (9) the parasitic diodes of the MOS devices are used to improve the noise margin of the circuit; (10) PPS CMOS can easily hold a static state and have the same low power dissipation properties of data inactive Conventional CMOS.

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2

Ren, Zhixiong, Kefeng Zhang, Xiaofei Chen, and Zhenglin Liu. "Scalable CMOS power combiner." Electronics Letters 50, no. 6 (March 2014): 431–32. http://dx.doi.org/10.1049/el.2013.3611.

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3

Blair, G. M. "Designing low-power digital CMOS." Electronics & Communication Engineering Journal 6, no. 5 (October 1, 1994): 229–36. http://dx.doi.org/10.1049/ecej:19940505.

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4

Niknejad, Ali M., Debopriyo Chowdhury, and Jiashu Chen. "Design of CMOS Power Amplifiers." IEEE Transactions on Microwave Theory and Techniques 60, no. 6 (June 2012): 1784–96. http://dx.doi.org/10.1109/tmtt.2012.2193898.

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5

Chandrakasan, A. P., S. Sheng, and R. W. Brodersen. "Low-power CMOS digital design." IEEE Journal of Solid-State Circuits 27, no. 4 (April 1992): 473–84. http://dx.doi.org/10.1109/4.126534.

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6

Frank, D. J. "Power-constrained CMOS scaling limits." IBM Journal of Research and Development 46, no. 2.3 (March 2002): 235–44. http://dx.doi.org/10.1147/rd.462.0235.

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7

Azeredo Leme, C., I. Filanovsky, and H. Baltes. "CMOS stabilised DC power source." Electronics Letters 28, no. 12 (1992): 1153. http://dx.doi.org/10.1049/el:19920728.

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8

Ismail, A. M., and A. M. Soliman. "Low-power CMOS current conveyor." Electronics Letters 36, no. 1 (2000): 7. http://dx.doi.org/10.1049/el:20000129.

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9

El-Moursy, Magdy A., and Eby G. Friedman. "Resistive Power in CMOS Circuits." Analog Integrated Circuits and Signal Processing 41, no. 1 (October 2004): 5–11. http://dx.doi.org/10.1023/b:alog.0000038278.71500.0c.

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10

Haldi, P., G. Liu, and A. M. Niknejad. "CMOS compatible transformer power combiner." Electronics Letters 42, no. 19 (2006): 1091. http://dx.doi.org/10.1049/el:20061585.

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11

Bae, Jongsuk, Junghyun Ham, Haeryun Jung, Wonsub Lim, Sooho Jo, and Youngoo Yang. "Design of Two-Stage CMOS Power Amplifier." Journal of Korean Institute of Electromagnetic Engineering and Science 25, no. 9 (September 30, 2014): 895–902. http://dx.doi.org/10.5515/kjkiees.2014.25.9.895.

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12

Jeon, Woochul, and John Melngailis. "CMOS and post-CMOS on-chip microwave pulse power detectors." Solid-State Electronics 50, no. 6 (June 2006): 951–58. http://dx.doi.org/10.1016/j.sse.2006.05.011.

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13

Nebhen, Jamel, Julien Dubois, Sofiene Mansouri, and Dominique Ginhac. "Low-noise and low power CMOS photoreceptor using split-length MOSFET." Journal of Electrical Engineering 70, no. 6 (December 1, 2019): 480–85. http://dx.doi.org/10.2478/jee-2019-0081.

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Abstract This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply voltage, achieves a noise floor of 2μV/⎷Hz within the frequency range from 1 Hz to 10 kHz. The current consumption of the CMOS photoreceptor is 541 nA. This paper shows the need for the design of phototransduction circuit at low voltage, low noise and how these constraints are reflected in the design of CMOS vision sensor.

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14

Ryu, Hyunsik, Ilku Nam, Dong-Ho Lee, and Ockgoo Lee. "CMOS Power Amplifier Using Mode Changeable Autotransformer." Journal of the Institute of Electronics and Information Engineers 51, no. 4 (April 25, 2014): 59–65. http://dx.doi.org/10.5573/ieie.2014.51.4.059.

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15

Deng, An-Chang. "Power Estimation and Power Noise Analysis for CMOS Circuits." Journal of Circuits, Systems and Computers 07, no. 01 (February 1997): 17–30. http://dx.doi.org/10.1142/s0218126697000036.

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Power consumption is a primary concern for today's IC designers. However, determining an IC's power consumption is a difficult task, as consumption varies according to input stimulus conditions. This paper will focus on (1) the principal phenomena involved in the power consumption of CMOS circuits, (2) a brief survey of power estimation techniques, and (3) the effect of power-supply noise on circuit performance plus possible solutions to this problem.

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16

Song, Ming Xin, Shan Shan Wang, and Guo Dong Sun. "CMOS Low Power Ring VCO Design." Advanced Materials Research 981 (July 2014): 70–73. http://dx.doi.org/10.4028/www.scientific.net/amr.981.70.

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A design project of voltage controlled oscillator which is the central component of the low voltage phase locked loop (PLL) is proposed in this paper. The VCO adopted the folding differential voltage controlled oscillator.Simulation results in Cadence Hspice indicate that the VCO proposed behaves in good linearity, simple structure, small phase noise.The frequency range from 125 to 787 MHz, the power consumption of this oscillator is only 6mW at central frequency is 480MHz with 3V power supply.

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17

Kado, Yuichi, Takakuni Douseki, Yasuyuki Matsuya, and Tsuneo Tsukahara. "Ultralow-power CMOS/SOI Circuit Technology." IEEJ Transactions on Electronics, Information and Systems 126, no. 6 (2006): 725–29. http://dx.doi.org/10.1541/ieejeiss.126.725.

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18

Kalyani, P. "Low Power Design for CMOS Circuits." CVR Journal of Science & Technology 03, no. 1 (December 1, 2012): 29–31. http://dx.doi.org/10.32377/cvrjst0306.

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19

ElDeib, Ahmed, and Roshdy AbdelRassoul. "Power minimization in CMOS RF mixers." International Conference on Electrical Engineering 6, no. 6 (May 1, 2008): 1–12. http://dx.doi.org/10.21608/iceeng.2008.34312.

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20

Fisher, J. A. "A high-performance CMOS power amplifier." IEEE Journal of Solid-State Circuits 20, no. 6 (December 1985): 1200–1205. http://dx.doi.org/10.1109/jssc.1985.1052459.

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21

Chunhong Chen and Zheng Li. "A low-power CMOS analog multiplier." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 2 (February 2006): 100–104. http://dx.doi.org/10.1109/tcsii.2005.857089.

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22

Walling, Jeffrey, and David Allstot. "Pulse-Width Modulated CMOS Power Amplifiers." IEEE Microwave Magazine 12, no. 1 (February 2011): 52–60. http://dx.doi.org/10.1109/mmm.2010.939304.

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23

Hajimiri, Ali. "Next-Generation CMOS RF Power Amplifiers." IEEE Microwave Magazine 12, no. 1 (February 2011): 38–45. http://dx.doi.org/10.1109/mmm.2010.939321.

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24

Zele, R. H., and D. J. Allstot. "Low-power CMOS continuous-time filters." IEEE Journal of Solid-State Circuits 31, no. 2 (1996): 157–68. http://dx.doi.org/10.1109/4.487992.

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25

Lopez-Martin, A. J., J. Ramírez-Angulo, R. G. Carvajal, and L. Acosta. "Power-efficient class AB CMOS buffer." Electronics Letters 45, no. 2 (2009): 89. http://dx.doi.org/10.1049/el:20092270.

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26

Baggini, B., F. Maloberti, and G. Palmisano. "Accurate low-power CMOS autozeroed comparator." Electronics Letters 28, no. 10 (May 7, 1992): 916–18. http://dx.doi.org/10.1049/el:19920581.

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27

Nagendra, C., R. M. Owens, and M. J. Irwin. "Power-delay characteristics of CMOS adders." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 3 (September 1994): 377–81. http://dx.doi.org/10.1109/92.311649.

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28

Avedillo, M. J., E. Jiménez, J. M. Quintana, and A. Rueda. "Low-power CMOS threshold-logic gate." Electronics Letters 31, no. 25 (December 7, 1995): 2157–59. http://dx.doi.org/10.1049/el:19951471.

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29

Jiang, Ching-Lin. "4613959 Zero power CMOS redundancy circuit." Microelectronics Reliability 27, no. 2 (January 1987): 397. http://dx.doi.org/10.1016/0026-2714(87)90319-2.

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30

Yi, Shu Chung. "A Low Power CMOS Temperature Sensor." Applied Mechanics and Materials 284-287 (January 2013): 1729–33. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.1729.

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This Paper Proposed a Low-power Smart Temperature Sensor. the Sensor Consisted of a PTAT Circuit, and a Ring Oscillator. the Current of the PTAT Circuit Was Used to Drive the Ring Oscillator which Generates a Temperature Related Signal. the Sensor Was Implemented by the TSMC CMOS 0.35 µm 2P4M Digital Process. the Core Aµµrea Is only 1105.59 µm2. the Power Consumption Is aboutµ 159.15 nw. the Linearity between the Output Frequency and Temperature Is Marked by R-square Rule. the Value of the Linearity Is 0.991 during the Temperature Range. the Proposed Sensor Required only One Supply Voltage. the Core Area Was Small. Therefore, the Sensor Was Suitable for Embedded in any Circuit that Required Temperature Monitoring.

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31

Kado, Yuichi, Takakuni Douseki, Yasuyuki Matsuya, and Tsuneo Tsukahara. "Ultralow-power CMOS/SOI circuit technology." Electrical Engineering in Japan 162, no. 3 (2007): 38–43. http://dx.doi.org/10.1002/eej.20543.

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32

El-Sabban, A. A. F., and H. F. Ragai. "Design of power-controlled class1 Bluetooth CMOS power amplifier." International Journal of Electronics 95, no. 3 (March 2008): 265–74. http://dx.doi.org/10.1080/00207210701828010.

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33

Feng, Wu-Shiung, Chin-I. Yeh, and Min-Zhi Zhou. "3.1–10.6 GHz UWB low-power CMOS power amplifier." International Journal of Electronics Letters 1, no. 2 (June 2013): 87–95. http://dx.doi.org/10.1080/21681724.2013.817021.

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34

LIN, HUNG-YI, and YEN-TAI LAI. "DESIGN OF LOW POWER TWO-PHASE CMOS BUFFER FOR LARGE CAPACITIVE LOADING APPLICATIONS." Journal of Circuits, Systems and Computers 22, no. 02 (February 2013): 1250092. http://dx.doi.org/10.1142/s0218126612500922.

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In this paper, a low power two-phase CMOS buffer with short-circuit power elimination and charge reuse for non-speed-critical large capacitive loading applications is proposed. The short-circuit power eliminating circuit is designed to remove the short-circuit current at the buffer's output, which accounts for the largest portion of the short-circuit power dissipation of the CMOS buffer. The charge reuse circuit is used to reduce the output dynamic power dissipation of the two-phase buffer. Moreover, the overall power dissipation of the proposed buffer is further decreased by optimizing the number of tapered stages and the values of tapered factors in the tapered chains of the short-circuit power eliminating circuit. In order to validate the efficiency of the proposed design, theoretical analysis and simulations with various capacitive loads are conducted using TSMC 0.18-μm 1P6M and UMC advanced 90-nm 1P9M CMOS technologies. The results show that the power dissipation of the proposed two-phase CMOS buffer is 8.6% lower than that of the conventional two-phase CMOS tapered buffer. The power-delay product of the proposed buffer is 2.7% smaller than that of the conventional tapered buffer.

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35

Li, Zhichao, Shiheng Yang, Samuel B. S. Lee, and Kiat Seng Yeo. "A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology." Electronics 9, no. 12 (December 20, 2020): 2198. http://dx.doi.org/10.3390/electronics9122198.

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For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (Psat) of 20.7 dBm, a peak PAE of 22.4%, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.

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36

Hussain, Inamul, and Saurabh Chaudhury. "CNFET Based Low Power Full Adder Circuit for VLSI Applications." Nanoscience & Nanotechnology-Asia 10, no. 3 (June 17, 2020): 286–91. http://dx.doi.org/10.2174/2210681209666190220122553.

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Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.

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37

Xu, Ni, Woogeun Rhee, and Zhihua Wang. "Semidigital PLL Design for Low-Cost Low-Power Clock Generation." Journal of Electrical and Computer Engineering 2011 (2011): 1–9. http://dx.doi.org/10.1155/2011/235843.

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This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

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38

Birla, Shilpi, Sudip Mahanti, and Neha Singh. "Leakage reduction technique for nano-scaled devices." Circuit World 47, no. 1 (May 29, 2020): 97–104. http://dx.doi.org/10.1108/cw-12-2019-0195.

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Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology. Design/methodology/approach Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices. Findings This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology. Originality/value All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

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39

Tiwari, Ayush. "Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 14, 2021): 962–66. http://dx.doi.org/10.22214/ijraset.2021.35065.

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Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

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40

Meyer, Joseph, Reza Moghimi, and Noah Sturcken. "Package Voltage Regulators: The Answer for Power Management Challenges." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000438–43. http://dx.doi.org/10.4071/2380-4505-2019.1.000438.

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Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

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41

Wu, Yang Bo, Jian Ping Hu, and Hong Li. "Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes." Advanced Materials Research 108-111 (May 2010): 625–30. http://dx.doi.org/10.4028/www.scientific.net/amr.108-111.625.

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In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

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42

Pan, James N. "Chromatic and Panchromatic Nonlinear Optoelectronic CMOSFETs for CMOS Image Sensors, Laser Multiplexing, Computing, and Communication." MRS Advances 5, no. 37-38 (2020): 1965–74. http://dx.doi.org/10.1557/adv.2020.273.

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AbstractTraditionally, CMOS transistors are for low power, high speed, and high packing density applications. CMOS is also commonly used as power regulating devices, and light sensors (CCD or CMOS image sensors). In this paper, we would like to introduce Photonic CMOS as a light emitting device for optical computing, ASIC, power transistors, and ultra large scale integration (ULSI). A Photonic CMOS Field Effect Transistor is fabricated with a low-resistance laser or LED in the drain region, and multiple photon sensors in the channel / well regions. The MOSFET, laser, and photon sensors are fabricated as one integral transistor. With embedded nonlinear optical films, the Photonic CMOSFETs have the capability of detecting and generating focused laser beams of various frequencies to perform optical computing, signal modulation, polarization, and multiplexing for digital / analog processing and communication.

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43

Birla, Shilpi. "Variability aware FinFET SRAM cell with improved stability and power for low power applications." Circuit World 45, no. 4 (November 4, 2019): 196–207. http://dx.doi.org/10.1108/cw-12-2018-0098.

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Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits. Design/methodology/approach In this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. Findings The cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384 mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed. Research limitations/implications The FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used. Practical implications SRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array. Social implications The cell can be used for SRAM memory for low power consumptions. Originality/value The work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

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44

Anusha, N., and T. Sasilatha. "Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies." Journal of Computational and Theoretical Nanoscience 13, no. 10 (October 1, 2016): 6999–7008. http://dx.doi.org/10.1166/jctn.2016.5660.

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Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS with mandatory keeper architectures in ultra submicron range are analyzed. A comparative analysis of Power dissipation and area of the keeper architectures employed in dynamic CMOS in different lower nanometer such as 120 nm, 90 nm, 70 nm and 50 nm is analyzed.

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Vidhyadharan, Abhay Sanjay, and Sanjay Vidhyadharan. "Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications." World Journal of Engineering 18, no. 5 (March 26, 2021): 750–59. http://dx.doi.org/10.1108/wje-08-2020-0367.

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Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

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Bellizia, Davide, Riccardo Della Sala, and Giuseppe Scotti. "SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks." Cryptography 5, no. 3 (June 28, 2021): 16. http://dx.doi.org/10.3390/cryptography5030016.

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With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the correlation between the static power and the secret keys was introduced more than ten years ago, and, since then, several successful key recovery experiments have been reported. These results clearly demonstrate that attacks exploiting static power (AESP) represent a serious threat for cryptographic systems implemented in nanometer CMOS technologies. In this work, we analyze the effectiveness of the Standard Cell Delay-based Precharge Logic (SC-DDPL) style in counteracting static power side-channel attacks. Experimental results on an FPGA implementation of a compact PRESENT crypto-core show that the SC-DDPL implementation allows a great improvement of all the security metrics with respect to the standard CMOS implementation and other state-of-the-art countermeasures such as WDDL and MDPL.

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Wu, Xiang, and Fang Ming Deng. "A Capacitive Humidity Sensor for Low-Cost Low-Power Application." Applied Mechanics and Materials 556-562 (May 2014): 1847–51. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1847.

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This paper presents a capacitive humidity sensor in CMOS technology. The humidity sensor element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication cost. The sensor interface employs a fully-digital architecture based on phase locked loop, which results in low pow dissipation. The proposed humidity sensor is fabricated in TSMC 0.18μm CMOS process and the chip occupies an area of 0.05mm2. The measurement result shows that the sensor value exhibits good linearity within the range of 10-90%RH and the interface circuit consumes only 1.05μW at 0.5V supply voltage.

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Lee, Changhyun, and Changkun Park. "Design methodology for a switching-mode RF CMOS power amplifier with an output transformer." International Journal of Microwave and Wireless Technologies 8, no. 3 (September 24, 2015): 471–77. http://dx.doi.org/10.1017/s1759078715001415.

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In this study, we propose a design methodology for a switching-mode RF CMOS power amplifier with an output transformer. For a given supply voltage, output power, and target efficiency, the initial values of the transistor size, output inductance, and capacitance can be sequentially determined during the design of the power amplifier. The breakdown voltage of the power transistor is considered in the design methodology. To prove the feasibility of the proposed design methodology, we provide the design example of a 2.4-GHz switching-mode CMOS power amplifier with 180-nm RF CMOS technology. From the measured results, the feasibility of the proposed design methodology is proved.

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LIAO, HAIFANG, WAYNE WEI-MING DAI, and RUI WANG. "A NEW CMOS DRIVER MODEL FOR TRANSIENT ANALYSIS AND POWER DISSIPATION ANALYSIS." International Journal of High Speed Electronics and Systems 07, no. 02 (June 1996): 269–85. http://dx.doi.org/10.1142/s0129156496000116.

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While most transient analysis techniques of interconnect networks ignore the nonlinearity of the driving gates, most CMOS driver models do not take into account the distributed loads. In this paper, we propose a new CMOS driver model which can handle distributed-lumped loads for transient analysis and power dissipation analysis. The output current of the CMOS driver is represented by a linear-quadratic-exponential piecewise model, taking into account the slope of the input signal, nonlinear effects of the driver and interconnect effects of the load. The CMOS transient leakage (short-circuit) current, thus short-circuit power dissipation, can be accurately evaluated. The model provides accuracy comparable to that of SPICE3e2 with one or two orders of magnitude less computing time.

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Hasan, A. F., S. A. Z Murad, K. N. Abdul Rani, F. A. Bakar, and T. Z. A. Zulkifli. "Study of CMOS power amplifier design techniques for ka-band applications." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (February 1, 2019): 808. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp808-817.

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<span>This paper reviews of high efficiency CMOS power amplifiers (PAs) in millimeter (mm) wave Ka - Band applications. The study is focused on the challenges in designing PA especially in GHz frequencies inclusive of high gain, good input and output matching, efficiency, linearity, low group delay and low power consumption. Several works on CMOS PA from year 2009 to 2018 are discussed in this paper. Recent developments of CMOS PAs are examined and a comparison of the performance criteria of various techniques is presented.</span>

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