Relevant bibliographies by topics / CMOS process

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'CMOS process'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 June 2025

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Journal articles on the topic "CMOS process"

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Yu, Ting, Ben Xian Peng, and Feng Qi Yu. "Absolute Pressure Sensor Based on Standard CMOS Process." Advanced Materials Research 875-877 (February 2014): 2238–42. http://dx.doi.org/10.4028/www.scientific.net/amr.875-877.2238.

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A CMOS compatible absolute pressure sensor with extend floating gate is developed with simple circuitry to realize high sensitivity, linearity, and manufacturability. The pressure sensitive membrane formation is based on the standard CMOS process with simple metal sacrificial layer removal step, which is very cost-efficient and fully CMOS compatible, enabling monolithic integration of circuitry. ANSYS and SPICE simulation results show that the proposed sensor can worked properly under 500K Pa, and the square sensing membrane of 100x100 μm 2 shows a good linearity over a pressure change ranging from 5 Pa to 500K Pa.
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Uchino, T., P. Ashburn, Y. Kiyota, and T. Shiba. "A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling." IEEE Transactions on Electron Devices 51, no. 1 (2004): 14–19. http://dx.doi.org/10.1109/ted.2003.820643.

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JOUVET, N., M. A. BOUNOUAR, S. ECOFFEY, et al. "RECENT DEVELOPMENTS ON 3D INTEGRATION OF METALLIC SET ONTO CMOS PROCESS FOR MEMORY APPLICATION." International Journal of Nanoscience 11, no. 04 (2012): 1240024. http://dx.doi.org/10.1142/s0219581x12400248.

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This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.
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Linares Aranda, Mónico, W. Calleja Arriaga, A. Torres Jacome, and C. R. Báez Álvarez. "A modular and generic monolithic integrated MEMS fabrication process." Superficies y Vacío 30, no. 3 (2017): 30–39. http://dx.doi.org/10.47566/2017_syv30_1-030030.

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A modular and generic, monolithic integrated MEMS fabrication process is presented to integrate microelectronics (CMOS) with mechanical microstructures (MEMS). The proposed monolithic integrated fabrication process is designed using an intra-CMOS approach (to fabricate the mechanical microstructures into trenches without the need of planarization techniques) and a CMOS module (to fabricate the electronic devices) with a 3 ?m length as minimum feature. The microstructures module is made up to three polysilicon layers, and aluminum as electrical interconnecting material. From simulation results, using the SILVACO® suite (Athena and Atlas frameworks), no significant degradation on the CMOS performance devices was observed after MEMS manufacturing stage; however, the thermal budget of the modules plays a crucial role, because it set the conditions for obtaining the complete set of devices fabricated near their optimal point. Finally, to evaluate and to support the development of the proposed integrated MEMS process, a modular test chip that includes electrical test structures, mechanical test structures, interconnection reliability test structures and functional micro-actuators, was also designed.
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Haond, M., M. T. Basso, E. deCoster, J. Guelen, and C. Lair. "Developing a 0.18-micron CMOS process." IEEE Micro 19, no. 5 (1999): 16–22. http://dx.doi.org/10.1109/40.798105.

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Hallam, P., P. J. Mather, and M. Brouwer. "CMOS process independent propagation delay macromodelling." Electronics Letters 31, no. 9 (1995): 702. http://dx.doi.org/10.1049/el:19950476.

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Pichler, P., A. Burenkov, J. Lorenz, C. Kampen, and L. Frey. "Future challenges in CMOS process modeling." Thin Solid Films 518, no. 9 (2010): 2478–84. http://dx.doi.org/10.1016/j.tsf.2009.09.150.

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Yu, Le, Yaozu Guo, Haoyu Zhu, Mingcheng Luo, Ping Han, and Xiaoli Ji. "Low-Cost Microbolometer Type Infrared Detectors." Micromachines 11, no. 9 (2020): 800. http://dx.doi.org/10.3390/mi11090800.

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The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.
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Shawkat, Mst Shamim Ara, Mohammad Habib Ullah Habib, Md Sakib Hasan, Mohammad Aminul Haque, and Nicole McFarlane. "Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes." International Journal of High Speed Electronics and Systems 27, no. 03n04 (2018): 1840018. http://dx.doi.org/10.1142/s0129156418400189.

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A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.
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Zhang, Chenyu, Nairui Hu, and Zhaoyang Liu. "The Simulation of the Terahertz Modulator by CMOS Process." Journal of Physics: Conference Series 2478, no. 6 (2023): 062038. http://dx.doi.org/10.1088/1742-6596/2478/6/062038.

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Abstract The paper introduced the simulation of the terahertz modulator in complementary metal-oxide-semiconductor (CMOS) process. The modulator is composed of a metal split-ring resonator (SRR), CMOS, semiconductor dielectric layer and silicon substrate. The modulator can make different electromagnetic response to the transmitted terahertz wave between the connection state and the disconnection state of the gap in the SRR, which could be achieved by connecting CMOS in the gap. At 0.31THz, the simulation results show that the amplitude modulation depth of the modulator reached 28.8%. When the simulation keeped the modulator system in resonating state, the transmission coefficient was about 0.0018, while the conductive had reached 0.2895. If the design can pass the experimental verification in the future, it can make some references for further exploration of the high-speed and high modulation depth of the terahertz amplitude modulator.
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Dissertations / Theses on the topic "CMOS process"

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Buttar, Alistair George. "CMOS process simulation." Thesis, University of Edinburgh, 1986. http://hdl.handle.net/1842/13282.

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Price, David T. "N-Well CMOS process integration /." Online version of thesis, 1992. http://hdl.handle.net/1850/11261.

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Di, Pede Luigi. "A 1 V low-power CMOS process." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0007/MQ34130.pdf.

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Chung, Chih-Ping. "Setting CMOS environment for VLSI design." Ohio : Ohio University, 1989. http://www.ohiolink.edu/etd/view.cgi?ohiou1182433560.

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Müller, Thomas. "An industrial CMOS process family for integrated silicon sensors /." [S.l.] : [s.n.], 1999. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=13463.

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Qu, Hongwei. "Development of DRIE CMOS-MEMS process and integrated accelerometers." [Gainesville, Fla.] : University of Florida, 2006. http://purl.fcla.edu/fcla/etd/UFE0015676.

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Gettings, Karen Mercedes González-Valentín. "Study of CMOS process variation by multiplexing analog characteristics." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40499.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.<br>Includes bibliographical references (p. 149-152).<br>Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. This thesis addresses this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a scan chain approach combined with low-leakage and low-variation switches, and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices. Front end of line (FEOL) test structures include transistors of different sizes, number of polysilicon fingers, polysilicon fingers proximity, and orientation, for both NMOS and PMOS MOSFETs. Back end of line (BEOL) test structures include parasitic coupling, plane to plane and crossover capacitances, measured using a charge-based capacitive measurement (CBCM) methodology integrated with switches in the scan chain. The testing of the designed test chip has proven successful for both device and interconnect test structures.<br>(cont.) Different layout practices in both NMOS and PMOS transistors are seen to result in significant differences in mean and standard deviation of measured output current, with 95% confidence or more. The FEOL structure analysis shows strong dependencies between layout practices: orientation offers a consistent but opposite offset in NMOS and PMOS transistors and variation increases for gate lengths split among fingers. Variation due to sizing follows Pelgrom's model, showing that variation increases for smaller gate lengths and widths, in both NMOS and PMOS transistors. Threshold voltage extraction and variation analysis also demonstrate how variation increases for smaller features. BEOL capacitances were extracted and sub-femto Farad changes were detected for capacitive test structures. Spatial analysis reveals a large die-to-die trend in device performance. The parameter extraction and variation analyses made possible by the variation test chip enable the identification of likely variation sources, quantification of circuit impact and sensitivity, and specification of layout practices for variation minimization.<br>by Karen Mercedes González-Valentín Gettings.<br>Ph.D.
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Wilson, David. "Characterisation of bipolar parasitic transistors for CMOS process control." Thesis, University of Edinburgh, 1992. http://hdl.handle.net/1842/11585.

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In integrated circuit manufacture, in particular, quality assurance, QA, is increasing rapidly in importance and in this research methods are developed and assessed which will assist with this. A review of current IC manufacturing is presented and CMOS technology shown to be dominant with BiCMOS seen to be a growth area. The role of Statistical Process Control, SPC, and the end for QA is also reviewed. This thesis addresses the problem and has defined some new techniques for the process control of a standard CMOS process. The approach is a novel one employing the concept of parasitic bipolar transistor test structures as a process control tool for present day CMOS circuits and, even more importantly, for BiCMOS devices. Test chip design and manufacture for the project are presented and the techniques proposed include: a) characterisation of parasitic JFETs to provide well depth information electrically b) the use of parasitic lateral bipolar transistors to estimate the sideways diffusion component associated with MOS transistors fabricated in a CMOS process c) the use of parasitic bipolar test structures to evaluate CMOS process uniformity. They provide useful parameters for processcontrol and, in some cases, have even been demonstrated to be more sensitive to CMOS process non-uniformities than those extracted from MOS devices themselves. Also process control information for today'sCMOS processes and an insight into the control of future BiCMOS processes.
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Bethi, Shiva Sai. "A Temperature and Process Insensitive CMOS Only Reference Current Generator." University of Akron / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=akron1416406367.

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Gurcan, Zeki B. "0.18 [mu]m high performance CMOS process optimization for manufacturability /." Online version of thesis, 2005. http://hdl.handle.net/1850/5197.

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Books on the topic "CMOS process"

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M, Pimbley J., ed. Advanced CMOS process technology. Academic Press, 1989.

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Prall, Kirk. CMOS Plasma and Process Damage. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-89029-1.

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G, Buehler Martin, ed. End-of-fabrication CMOS process monitor. National Aeronautics and Space Administration, 1990.

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G, Buehler Martin, ed. End-of-fabrication CMOS process monitor. National Aeronautics and Space Administration, 1990.

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Zjajo, Amir. Stochastic Process Variation in Deep-Submicron CMOS. Springer Netherlands, 2014. http://dx.doi.org/10.1007/978-94-007-7781-1.

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Pede, Luigi Di. A 1 V low power CMOS process. National Library of Canada, 1998.

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Magierowski, Sebastian Claudiusz. A PMOS transistor for a low-power 1 V CMOS process. National Library of Canada = Bibliothèque nationale du Canada, 1999.

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Madrid, Philip E. Device design and process window analysis of a deep submicron CMOS VLSI technology. Addison-Wesley, 1992.

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Tsu-Jae, King, Materials Research Society Meeting, and Symposium on CMOS Front-End Materials and Process Technology (2003 : San Francisco, Calif.), eds. CMOS front-end materials and process technology: Symposium held April 22-24, 2003, San Francisco, California, U.S.A. Materials Research Society, 2003.

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Andrei, Pavlov. CMOS SRAM circuit design and parametric test in nano-scaled technologies: Process-aware SRAM design and test. Springer, 2008.

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Book chapters on the topic "CMOS process"

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Abbas, Karim. "CMOS Process." In Handbook of Digital CMOS Technology, Circuits, and Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37195-1_7.

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Bernstein, Kerry, Keith M. Carrig, Christopher M. Durham, et al. "Process Variability." In High Speed CMOS Design Styles. Springer US, 1999. http://dx.doi.org/10.1007/978-1-4615-5573-5_1.

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Yue, Xicai, and Emmanuel M. Drakakis. "Monitoring of Stem Cell Culture Process Using Electrochemical Biosensors." In CMOS Biomicrosystems. John Wiley & Sons, Inc., 2011. http://dx.doi.org/10.1002/9781118016497.ch11.

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Prall, Kirk. "Process Damage Test Structures." In CMOS Plasma and Process Damage. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-89029-1_11.

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Prall, Kirk. "Signatures of Process Damage." In CMOS Plasma and Process Damage. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-89029-1_4.

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Prall, Kirk. "Technology-Specific Process Damage." In CMOS Plasma and Process Damage. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-89029-1_8.

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Prall, Kirk. "Inline Process Damage Measurements." In CMOS Plasma and Process Damage. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-89029-1_10.

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Prall, Kirk. "Common Sources of Process Damage." In CMOS Plasma and Process Damage. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-89029-1_9.

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Prall, Kirk. "Electrical Signatures of Process Damage." In CMOS Plasma and Process Damage. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-89029-1_5.

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Prall, Kirk. "Metallic Defects." In CMOS Plasma and Process Damage. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-89029-1_15.

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Conference papers on the topic "CMOS process"

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Rizzo, Anthony, Eric Thornton, Tuan Vo, et al. "Low-Loss Aluminum Nitride Waveguides in a 300 mm CMOS Foundry Process." In CLEO: Science and Innovations. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/cleo_si.2024.stu4e.3.

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We demonstrate low-loss aluminum nitride waveguides fabricated using a standard silicon photonics process flow in a CMOS foundry. The material’s wide transparency and χ(2) nonlinearity can extend silicon photonics to novel visible wavelength applications.
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Madhvapathy, Sarika, Panagiotis Zarkos, Danielius Kramnik, and Vladimir Stojanović. "Ring Resonator Based Ultrasound Detection in a Zero-Change 45nm CMOS-SOI Process." In CLEO: Applications and Technology. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/cleo_at.2024.ath4b.3.

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We present an ultra-dense row of silicon microring resonators used as optical ultrasound sensors in a high-volume monolithic electronics-photonics CMOS platform, achieving an average (maximum) intrinsic sensitivity of 34.25fm/kPa (38.22fm/kPa) at 5MHz.
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Buehler, M. G., L. W. Linholm, V. C. Tyree, et al. "CMOS Process Monitor." In Proceedings of the IEEE International Conference on Microelectronic Test Structures. IEEE, 1988. http://dx.doi.org/10.1109/icmts.1988.672954.

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Chiou, Jing-Hung, Ching-Liang Dai, Jen-Yi Chen, and Michael S. C. Lu. "A Novel Maskless Post-CMOS Bulk Micromachining Process." In ASME 2003 International Mechanical Engineering Congress and Exposition. ASMEDC, 2003. http://dx.doi.org/10.1115/imece2003-41721.

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This work describes a new post-CMOS (Complementary Metal Oxide Semiconductor) bulk micromachining process for fabrication of various microstructures. The important feature of the post-CMOS process is the use of wet etching without an addition mask, to form various microstructures and deep cavities in the silicon substrate. The post-CMOS process starts with wet etching to remove sacrificial layers, which are stacked layers of metals and vias, to expose the silicon substrate. Then, KOH or TMAH solution is employed to etch the silicon substrate to form various deep cavities and suspended structures. Many suspended structures, which include beams, bridges and plates, are fabricated using the standard 0.35-μm SPFM (Single Polysilicon Four Metal) CMOS process and the post-CMOS process. Experimental results reveals that a plate with an area of 200×200 μm2, a bridge with a length of 300μm, and various beams with lengths from 100-μm to 400-μm suspended on a deep cavity were fabricated successfully.
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Andriukaitis, D., R. Anilionis, and T. Kersys. "LOCOS CMOS process simulation." In 28th International Conference on Information Technology Interfaces, 2006. IEEE, 2006. http://dx.doi.org/10.1109/iti.2006.1708530.

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Ding, L. Y., T. Wang, Y. C. Hu, W. P. Shih, S. S. Lu, and P. Z. Chang. "CMOS-compatible electrochemical process for RF CMOS inductors." In TRANSDUCERS 2009 - 2009 International Solid-State Sensors, Actuators and Microsystems Conference. IEEE, 2009. http://dx.doi.org/10.1109/sensor.2009.5285624.

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Imbrea, Damian. "A CMOS standard-process sensor." In 2015 International Symposium on Signals, Circuits and Systems (ISSCS). IEEE, 2015. http://dx.doi.org/10.1109/isscs.2015.7203928.

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Haas, J., K. Au, L. C. Martin, T. L. Portlock, and T. Sakurai. "High voltage CMOS LCD driver using low voltage CMOS process." In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56755.

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Agarwal, Kanak, and Sani Nassif. "Characterizing Process Variation in Nanometer CMOS." In 2007 44th ACM/IEEE Design Automation Conference. IEEE, 2007. http://dx.doi.org/10.1109/dac.2007.375195.

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Vinet, F., M. Chevallier, J. C. Guibert, and Ch Pierrat. "0.6µm CMOS Technology Using Desire Process." In 1989 Microlithography Conferences, edited by Elsa Reichmanis. SPIE, 1989. http://dx.doi.org/10.1117/12.953056.

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Reports on the topic "CMOS process"

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Rau, Jerry. PR-542-163745-R01 Defining Close Metal Object Detection Capabilities of MFL ILI Tools. Pipeline Research Council International, Inc. (PRCI), 2017. http://dx.doi.org/10.55274/r0011422.

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There is a need to understand Magnetic Flux Leakage (MFL) in-line inspection data and determine if it distinguishes whether a Close Metal Object (CMO) is an adjacent pipeline or independent metallic article. There have been failures associated with CMOs both in contact and in close proximity with the pipeline, specifically water lines. With the knowledge gained on the sensitivity of MFL technology to detect such objects, a process could be developed to identify those CMOs which may be a hazard to the pipeline and prioritize them for evaluation. This report has a related webinar. ?
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Kroeger, R. A., W. N. Johnson, R. L. Kinzer, et al. Charge Sensitive Preamplifier and Pulse Shaper using CMOS process for Germanium Spectroscopy. Defense Technical Information Center, 1994. http://dx.doi.org/10.21236/ada464517.

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Marshall, Janet C., M. Parameswaran, Mona E. Zaghloul, and Michael Gaitan. Methodology for the computer-aided design of silicon micromachined devices in a standard CMOS process. National Institute of Standards and Technology, 1992. http://dx.doi.org/10.6028/nist.ir.4845.

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MYERS, DAVID R., JEFFREY R. JESSING, OLGA B. SPAHN, and MARTY R. SHANEYFELT. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99). Office of Scientific and Technical Information (OSTI), 2000. http://dx.doi.org/10.2172/750886.

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Li, Honghai, Lihwa Lin, Cody Johnson, et al. A revisit and update on the verification and validation of the Coastal Modeling System (CMS) : report 1--hydrodynamics and waves. Engineer Research and Development Center (U.S.), 2022. http://dx.doi.org/10.21079/11681/45444.

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This is the first part of a two-part report that revisits and updates the verification and validation (V&amp;V) of the Coastal Modeling System (CMS). The V&amp;V study in this part of the report focuses on hydrodynamic and wave modeling. With the updated CMS code (Version 5) and its latest graphical user interface, the Surface-water Modeling System (Version 13), the goal of this study is to revisit some early CMS V&amp;V cases and assess some new cases on model performance in coastal applications. The V&amp;V process includes the comparison and evaluation of the CMS output against analytical solutions, laboratory experiments in prototype cases, and field cases in and around coastal inlets and navigation projects. The V&amp;V results prove that the basic physics incorporated are represented well, the computational algorithms implemented are accurate, and the coastal processes are reproduced well. This report provides the detailed descriptions of those test simulations, which include the model configuration, the selection of model parameters, the determination of model forcing, and the quantitative assessment of the model and data comparisons. It is to be hoped that, through the V&amp;V process, the CMS users will better understand the model’s capability and limitation as a tool to solve real-world problems.
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Harriss, Lydia, and Andrew Stretton. Access to critical materials. Parliamentary Office of Science and Technology, 2019. http://dx.doi.org/10.58248/pn609.

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Critical materials (CMs) are key to UK manufacturing, including for the aerospace, automotive, energy and chemical sectors, which rely on materials typically extracted and processed abroad. CMs are vital components of several emerging technologies, including electric vehicles, renewable energy infrastructure such as wind turbines, and digital technologies such as computers and smartphones. The UK imports most of its CMs and faces international competition for key resources. This POSTnote looks at the demand and supply of CMs in the UK and ways of improving supply security.
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Zaghloul, M., D. Novotny, V. Tyree, J. I. Pi, C. Pi��, and W. Hansford. Realizing suspended structures on chips fabricated by CMOS foundry processes through the MOSIS service. National Institute of Standards and Technology, 1994. http://dx.doi.org/10.6028/nist.ir.5402.

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Li, Honghai, Mitchell Brown, Lihwa Lin, et al. Coastal Modeling System user's manual. Engineer Research and Development Center (U.S.), 2024. http://dx.doi.org/10.21079/11681/48392.

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The Coastal Modeling System (CMS) is a suite of coupled 2D numerical models for simulating nearshore waves, currents, water levels, sediment transport, morphology change, and salinity and temperature. Developed by the Coastal Inlets Research Program of the US Army Corps of Engineers, the CMS provides coastal engineers and scientists a PC-based, easy-to-use, accurate, and efficient tool for understanding of coastal processes and for designing and managing of coastal inlets research, navigation projects, and sediment exchange between inlets and adjacent beaches. The present technical report acts as a user guide for the CMS, which contains comprehensive information on model theory, model setup, and model features. The detailed descriptions include creation of a new project, configuration of model grid, various types of boundary conditions, representation of coastal structures, numerical methods, and coupled simulations of waves, hydrodynamics, and sediment transport. Pre- and post-model data processing and CMS modeling procedures are also described through operation within a graphic user interface—the Surface- water Modeling System.
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9

Holzenthal, Elizabeth, and Bradley Johnson. Comparison of run-up models with field data. Engineer Research and Development Center (U.S.), 2024. https://doi.org/10.21079/11681/49470.

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Run-up predictions are inherently uncertain, owing to ambiguities in phase-averaged models and inherent complexities of surf and swash-zone hydrodynamics. As a result, different approaches, ranging from simple algebraic expressions to computationally intensive phase-resolving models, have been used in attempt to capture the most relevant run-up processes. Studies quantifiably comparing these methods in terms of physical accuracy and computational speed are needed as new observation technologies and models become available. The current study tests the capability of the new swash formulation of the Coastal Modeling System (CMS) to predict 1D run-up statistics (R2%) collected during an energetic 3-week period on sandy dune-backed beach in Duck, North Carolina. The accuracy and speed of the debut CMS swash formulation is compared with one algebraic model and three other numerical models. Of the four tested numerical models, the CSHORE model computed the results fastest, and the CMS model results had the greatest accuracy. All four numerical models, including XBeach in surfbeat and nonhydrostatic modes, yielded half the error of the algebraic model tested. These findings present an encouraging advancement for phase-averaged coastal models, a critical step towards rapid prediction for near-time deterministic or long-term stochastic guidance.
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10

Ostersetzer-Biran, Oren, and Jeffrey Mower. Novel strategies to induce male sterility and restore fertility in Brassicaceae crops. United States Department of Agriculture, 2016. http://dx.doi.org/10.32747/2016.7604267.bard.

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Abstract Mitochondria are the site of respiration and numerous other metabolic processes required for plant growth and development. Increased demands for metabolic energy are observed during different stages in the plants life cycle, but are particularly ample during germination and reproductive organ development. These activities are dependent upon the tight regulation of the expression and accumulation of various organellar proteins. Plant mitochondria contain their own genomes (mtDNA), which encode for rRNAs, tRNAs and some mitochondrial proteins. Although all mitochondria have probably evolved from a common alpha-proteobacterial ancestor, notable genomic reorganizations have occurred in the mtDNAs of different eukaryotic lineages. Plant mtDNAs are notably larger and more variable in size (ranging from 70~11,000 kbp in size) than the mrDNAs in higher animals (16~19 kbp). Another unique feature of plant mitochondria includes the presence of both circular and linear DNA fragments, which undergo intra- and intermolecular recombination. DNA-seq data indicate that such recombination events result with diverged mitochondrial genome configurations, even within a single plant species. One common plant phenotype that emerges as a consequence of altered mtDNA configuration is cytoplasmic male sterility CMS (i.e. reduced production of functional pollen). The maternally-inherited male sterility phenotype is highly valuable agriculturally. CMS forces the production of F1 hybrids, particularly in predominantly self-pollinating crops, resulting in enhanced crop growth and productivity through heterosis (i.e. hybrid vigor or outbreeding enhancement). CMS lines have been implemented in some cereal and vegetables, but most crops still lack a CMS system. This work focuses on the analysis of the molecular basis of CMS. We also aim to induce nuclear or organellar induced male-sterility in plants, and to develop a novel approach for fertility restoration. Our work focuses on Brassicaceae, a large family of flowering plants that includes Arabidopsis thaliana, a key model organism in plant sciences, as well as many crops of major economic importance (e.g., broccoli, cauliflower, cabbage, and various seeds for oil production). In spite of the genomic rearrangements in the mtDNAs of plants, the number of genes and the coding sequences are conserved among different mtDNAs in angiosperms (i.e. ~60 genes encoding different tRNAs, rRNAs, ribosomal proteins and subunits of the respiratory system). Yet, in addition to the known genes, plant mtDNAs also harbor numerous ORFs, most of which are not conserved among species and are currently of unknown function. Remarkably, and relevant to our study, CMS in plants is primarily associated with the expression of novel chimericORFs, which likely derive from recombination events within the mtDNAs. Whereas the CMS loci are localized to the mtDNAs, the factors that restore fertility (Rfs) are identified as nuclear-encoded RNA-binding proteins. Interestingly, nearly all of the Rf’s are identified as pentatricopeptide repeat (PPR) proteins, a large family of modular RNA-binding proteins that mediate several aspects of gene expression primarily in plant organelles. In this project we proposed to develop a system to test the ability of mtORFs in plants, which are closely related to known CMS factors. We will induce male fertility in various species of Brassicaceae, and test whether a down-relation in the expression of the recombinantCMS-genes restores fertility, using synthetically designed PPR proteins.
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