To see the other types of publications on this topic, follow the link: CMOS process.
Dissertations / Theses on the topic 'CMOS process'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'CMOS process.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Buttar, Alistair George. "CMOS process simulation." Thesis, University of Edinburgh, 1986. http://hdl.handle.net/1842/13282.
Full text
2
Price, David T. "N-Well CMOS process integration /." Online version of thesis, 1992. http://hdl.handle.net/1850/11261.
Full text
3
Di, Pede Luigi. "A 1 V low-power CMOS process." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0007/MQ34130.pdf.
Full text
4
Chung, Chih-Ping. "Setting CMOS environment for VLSI design." Ohio : Ohio University, 1989. http://www.ohiolink.edu/etd/view.cgi?ohiou1182433560.
Full text
5
Müller, Thomas. "An industrial CMOS process family for integrated silicon sensors /." [S.l.] : [s.n.], 1999. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=13463.
Full text
6
Qu, Hongwei. "Development of DRIE CMOS-MEMS process and integrated accelerometers." [Gainesville, Fla.] : University of Florida, 2006. http://purl.fcla.edu/fcla/etd/UFE0015676.
Full text
7
Gettings, Karen Mercedes González-Valentín. "Study of CMOS process variation by multiplexing analog characteristics." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40499.
Full textAbstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.<br>Includes bibliographical references (p. 149-152).<br>Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. This thesis addresses this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a scan chain approach combined with low-leakage and low-variation switches, and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices. Front end of line (FEOL) test structures include transistors of different sizes, number of polysilicon fingers, polysilicon fingers proximity, and orientation, for both NMOS and PMOS MOSFETs. Back end of line (BEOL) test structures include parasitic coupling, plane to plane and crossover capacitances, measured using a charge-based capacitive measurement (CBCM) methodology integrated with switches in the scan chain. The testing of the designed test chip has proven successful for both device and interconnect test structures.<br>(cont.) Different layout practices in both NMOS and PMOS transistors are seen to result in significant differences in mean and standard deviation of measured output current, with 95% confidence or more. The FEOL structure analysis shows strong dependencies between layout practices: orientation offers a consistent but opposite offset in NMOS and PMOS transistors and variation increases for gate lengths split among fingers. Variation due to sizing follows Pelgrom's model, showing that variation increases for smaller gate lengths and widths, in both NMOS and PMOS transistors. Threshold voltage extraction and variation analysis also demonstrate how variation increases for smaller features. BEOL capacitances were extracted and sub-femto Farad changes were detected for capacitive test structures. Spatial analysis reveals a large die-to-die trend in device performance. The parameter extraction and variation analyses made possible by the variation test chip enable the identification of likely variation sources, quantification of circuit impact and sensitivity, and specification of layout practices for variation minimization.<br>by Karen Mercedes González-Valentín Gettings.<br>Ph.D.
8
Wilson, David. "Characterisation of bipolar parasitic transistors for CMOS process control." Thesis, University of Edinburgh, 1992. http://hdl.handle.net/1842/11585.
Full textAbstract:
In integrated circuit manufacture, in particular, quality assurance, QA, is increasing rapidly in importance and in this research methods are developed and assessed which will assist with this. A review of current IC manufacturing is presented and CMOS technology shown to be dominant with BiCMOS seen to be a growth area. The role of Statistical Process Control, SPC, and the end for QA is also reviewed. This thesis addresses the problem and has defined some new techniques for the process control of a standard CMOS process. The approach is a novel one employing the concept of parasitic bipolar transistor test structures as a process control tool for present day CMOS circuits and, even more importantly, for BiCMOS devices. Test chip design and manufacture for the project are presented and the techniques proposed include: a) characterisation of parasitic JFETs to provide well depth information electrically b) the use of parasitic lateral bipolar transistors to estimate the sideways diffusion component associated with MOS transistors fabricated in a CMOS process c) the use of parasitic bipolar test structures to evaluate CMOS process uniformity. They provide useful parameters for processcontrol and, in some cases, have even been demonstrated to be more sensitive to CMOS process non-uniformities than those extracted from MOS devices themselves. Also process control information for today'sCMOS processes and an insight into the control of future BiCMOS processes.
9
Bethi, Shiva Sai. "A Temperature and Process Insensitive CMOS Only Reference Current Generator." University of Akron / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=akron1416406367.
Full text
10
Gurcan, Zeki B. "0.18 [mu]m high performance CMOS process optimization for manufacturability /." Online version of thesis, 2005. http://hdl.handle.net/1850/5197.
Full text
11
Ross, Kyle Gene. "Distributed amplifier circuit design using a commercial CMOS process technology." Thesis, Montana State University, 2006. http://etd.lib.montana.edu/etd/2006/ross/RossK0806.pdf.
Full text
12
Wu, Dongping. "Novel concepts for advanced CMOS : Materials, process and device architecture." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3805.
Full textAbstract:
<p>The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.</p><p>High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO<sub>2</sub>and Al<sub>2</sub>O<sub>3</sub>as well as their mixtures are investigated assubstitutes for the traditionally used SiO<sub>2</sub>in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.</p><p>A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.</p><p><b>Key words:</b>CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.</p>
13
Jeon, Jeongmin. "Integrated UHF CMOS power amplifiers in silicon on insulator process." Diss., Manhattan, Kan. : Kansas State University, 2008. http://hdl.handle.net/2097/983.
Full text
14
Shedabale, Santosh. "Statistical Modelling of Process Variations in CMOS Devices and Circuits." Thesis, University of Newcastle Upon Tyne, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.506597.
Full text
15
Meng, Huaiyu. "Towards integrated QPSK transceiver on zero-change CMOS foundry process." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/93779.
Full textAbstract:
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 127-136).<br>In recent years, the demand for Internet bandwidth increases while the unit price of bandwidth decreases. To keep up with the trend, more cost-eective optical telecommunication links are required. Due to the limited amount of optical fibers and wave- length range, increasing spectral eciency is a desirable approach. Advance modulation scheme, such as quadrature phase-shift keying (QPSK), is a possible solution. Another limitation is energy consumption. Power density within telecommunication data centers are regulated by law in consideration of ambient temperature and noise level. Therefore, optical transceivers with higher energy eciency is desired. Traditional transceivers use III-V chips for photonic components and CMOS chips for electronic circuits. Monolithic integration of photonic and electronic components helps removing energy consumption for inter-chip communication and hence increase overall energy eciency. In this thesis, a QPSK transceiver in zero-change CMOS process is proposed. Research is focused on three photonic components: 90 degree hybrids, poly-silicon photodetectors and QPSK modulators. Hybrids are used to mix QPSK-modulated signal and local oscillators with four equally-spaced phase delays. Multi-mode interferometers (MMI) are designed for this purpose. Best devices provides intensity imbalance around 1 dB and phase error around 10. For poly-silicon photodetectors, sub-bandgap defect states are used for electron-hole pair generation. A ring-resonant structure is used to enhance absorption and reduce footprint. Best devices have quantum eciency around 3.5% and dark current less than 60 nA under 25V reverse bias. The 3 dB frequency is around 1.2 GHz. Finally, double-coupled ring resonators with feed through waveguides are used for QPSK modulators. Carrier injection changes the resonance condition and provides phase shift. With the development of these devices, the path towards a monolithic QPSK transceiver in CMOS becomes clear.<br>by Huaiyu Meng.<br>S.M.
16
Hildreth, Scott A. "Statistical SPICE parameter extraction for an N-Well CMOS process /." Online version of thesis, 1995. http://hdl.handle.net/1850/12177.
Full text
17
Beck, Riley D. "High Voltage Analog Design in a Standard Digital CMOS Process." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd1092.pdf.
Full text
18
Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.
Full text
19
Sun, Da Peng. "Process compensated CMOS temperature sensor exploiting piecewise base recombination current." Thesis, University of Macau, 2018. http://umaclib3.umac.mo/record=b3950680.
Full text
20
Magierowski, Sebastian Claudiusz. "A PMOS transistor for a low-power 1 V CMOS process." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ28847.pdf.
Full text
21
Lu, Yuanlin. "Power and performance optimization of static CMOS circuits with process variation." Auburn, Ala., 2007. http://repo.lib.auburn.edu/07M%20Dissertations/LU_YUANLIN_28.pdf.
Full text
22
Davey, William Mark. "High-k dielectric stacks for integration into an advanced CMOS process." Thesis, University of Liverpool, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.526811.
Full text
23
Lei, Yi-Shu Vivian 1979. "Post assembly process development for Monolithic OptoPill integration on silicon CMOS." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28548.
Full textAbstract:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.<br>Includes bibliographical references (leaves 108-110).<br>Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that enables the volume production of high performance optoelectronic integrated circuits (OEICs). This thesis focuses on the development of post-assembly processes and technologies, in which InGaAs/InP P-i-N photodiodes were integrated as long wavelength photodetectors with an optical clock receiver circuit. Fabrication procedures, challenges experienced, and results accomplished are presented for each process step including the formation of alloyed and non-alloyed ohmic contacts on n-type and p-type InGaAs contact layers, active area definition by dry-etching InGaAs/InP with ECR-enhanced RIE, BCB passivation and planarization, via opening by dry-etching BCB with RIE, and top contact metallization. In conjunction, an InP-based test heterostructure was fabricated into discrete photodiodes. Decoupling the fabrication and benchmarking of III-V photonic device from the Si-CMOS electronic circuit allowed for the independent electrical and optical characterization of the photodetectors. Measurements and analysis of the P-i-N photodiodes will assist the forthcoming analysis of the final OEIC. Preliminary results and discussions of the calibration sample are presented in this thesis.<br>by Yi-Shu Vivian Lei.<br>S.M.
24
Moron, Guerra José. "Design of Sub-THz heterodyne receivers in 65 nm CMOS process." Thesis, Lille 1, 2014. http://www.theses.fr/2014LIL10053/document.
Full textAbstract:
Le but de cette thèse est d'explorer les opportunités de design au-delà des fréquences millimétriques en se rapprochant le plus possible de la bande THz en technologie CMOS. L’application spécifique est la détection hétérodyne pour l'imagerie THz. Sachant qu’on vise des fréquences autour de 280 GHz et on travaille avec la technologie CMOS 65 nm, les composant réalisés fonctionnent 80 GHz au-dessus de la fréquence de coupure fmax des transistors utilisés. En termes de réalisation on a développé deux oscillateurs à verrouillage par injection sous-harmonique fonctionnant autour de 280 GHz. La fréquence d’injection de chaque oscillateur est d’environ 47 GHz (1/6 de la fréquence de sortie). Afin de produire des oscillations au-delà de fmax, des techniques de génération harmonique ont été utilisées (push-push, triple-push, etc). Les oscillateurs génèrent des signaux de – 19 et – 14 dBm de puissance à 280 GHz. Chaque composant a été utilisé comme oscillateur local pour des récepteurs hétérodynes fonctionnant à la même fréquence. Ces récepteurs n’ont pas de LNA au début de la chaîne à cause des faibles fréquences de coure néanmoins ils utilisent des mélangeurs passifs afin de pouvoir multiplier des signaux au-delà des limites. Les deux récepteurs développés ont un gain de conversion de – 6 dB et ont des figures de bruit (NF) de 36 et 30 dB. La version la plus performante du récepteur (30 dB de NF) a été intégrée avec une antenne développée par le Labsticc afin de pouvoir réaliser des images Sub-THz avec la détection hétérodyne<br>The main goal of this thesis is to explore design opportunities beyond the millimeter wave frequencies and to get as close as possible to the THz band using CMOS technologies. The main application is the heterodyne detection for THz imaging. The cut-off frequencies ft/fmax of the used process (65 nm CMOS) are 150/205 GHz, the chosen operation frequency of the developed systems is 280 GHz which means that the circuits developed during this thesis operate at least 80 GHz beyond their fmax cut-off frequency. Two 280 GHz sub-harmonic injection locked oscillators were developed, the injection frequency corresponds to one sixth of the ouput frequency. In order to generate oscillations beyond fmax, harmonic boost techniques are used such as the push-push and triple push techniques. The output power of the oscillators are - 19 and - 14 dBm at 280 GHz. Both components were used as local oscillators for two heterodyne receivers operating around the same frequency. In order to down-covert the Sub-THz signal, a passive resistive mixer is used; this kind of circuit allows mixing beyond the active transistor limits. Also there is no LNA at the begining of the Rx chain since the cut-off frequencies are very low and there will be no gain for amplification at 280 GHz. The conversion gain of both receivers is - 6 dB however the NF's are 36 dB and 30 dB. The best receiver (30 dB) is co-integrated with an antenna (developed by Labsticc) using the same process allowing heterodyne detection THz imaging
25
Lang, Radek. "Vysokofrekvenční oscilátor v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221110.
Full textAbstract:
This project focus to desing an on-chip oscillator in function as a clock generator. Frequency stability of the oscillator is affected by supply voltage, temperature and process variations. The aim is to propose a clock generator with sufficient frequency stability, low power consumption and a small chip area. This work deals with the types of oscillators and their basic building blocks suitable for our application. It also deals with the study and design options of temperature and process compensation circuit generating the current control, which provides the frequency stabilization of the output signal.
26
Yousaf, Malik Muzammil. "CMOS Power Amplifier for IEEE 802.11g/n standard (2.4GHz) in 65nm process." Thesis, Linköpings universitet, Institutionen för systemteknik, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-62172.
Full textAbstract:
Today, the mobile communication systems can be found everywhere due to thelow cost and high degree integration level which is achievable with CMOS. Theuser can use a number of applications using only one device. The transmitteris one of the main blocks in communication systems for transmitting the signal,where the RF power a mplifier (PA) amplifies the RF signal to the r equiredoutput power so that signal can reach the r eceiver. Nowadays mostly transmitteremploys such modulation schemes which have high data rate and to amplify suchsignals, a linear PA is required. The efficiency of the PA should also be high, sothat it can provide high output power to load without consuming much poweritself.This thesis work describes the “CMOS Power Amplifier for IEEE 802.11g/nstandard (2.4GHz) in 65nm process”. The PA is a two stage amplifier biasedin Class AB mode with LC type input matching. The inter-stage matching iscarried out by the RF choke of the driver stage and the input capacitance of thepower stage. The output of the PA is power matched to the load. A linearizingtechnique is implemented to make PA more linear. The simulation results showsthat the designed PA gives 1dB compression point of +23.36dBm, a gain of26.82dB, a power added efficiency of 30%, a linear current of 122.30mA providing18dBm power to load and saturated output power of 24.45dBm.
27
Okobiah, Oghenekarho. "Exploring Process-Variation Tolerant Design of Nanoscale Sense Amplifier Circuits." Thesis, University of North Texas, 2010. https://digital.library.unt.edu/ark:/67531/metadc67942/.
Full textAbstract:
Sense amplifiers are important circuit components of a dynamic random access memory (DRAM), which forms the main memory of digital computers. The ability of the sense amplifier to detect and amplify voltage signals to correctly interpret data in DRAM cells cannot be understated. The sense amplifier plays a significant role in the overall speed of the DRAM. Sense amplifiers require matched transistors for optimal performance. Hence, the effects of mismatch through process variations must be minimized. This thesis presents a research which leads to optimal nanoscale CMOS sense amplifiers by incorporating the effects of process variation early in the design process. The effects of process variation on the performance of a standard voltage sense amplifier, which is used in conventional DRAMs, is studied. Parametric analysis is performed through circuit simulations to investigate which parameters have the most impact on the performance of the sense amplifier. The figures-of-merit (FoMs) used to characterize the circuit are the precharge time, power dissipation, sense delay and sense margin. Statistical analysis is also performed to study the impact of process variations on each FoM. By analyzing the results from the statistical study, a method is presented to select parameter values that minimize the effects of process variation. A design flow algorithm incorporating dual oxide and dual threshold voltage based techniques is used to optimize the FoMs for the sense amplifier. Experimental results prove that the proposed approach improves precharge time by 83.9%, sense delay by 80.2% sense margin by 61.9%, and power dissipation by 13.1%.
28
Dupoiron, Camille. "Nouveaux paradigmes de capture d’images et traitements associés pour futurs SoC en nœuds CMOS nanométriques." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT100/document.
Full textAbstract:
Le sujet de thèse a pour objectif de revisiter le paradigme d'acquisition d'images dans les circuits intégrés pour le rendre robuste et scalable en technologies nanométriques (telles que le 28nm FDSOI). Ceci, afin de répondre aux contraintes d’imagerie imposée par des applications de type internet des objets. Dans ce cas, un système sur puce (SoC) hétérogène conçut en technologie avancée permettrait de répondre aux contraintes de consommation d’énergie. L’utilisation des imageurs standard actuels n’est alors pas compatible avec cette exigence à cause de leur consommation excessive et leur non compatibilité avec les technologies FDSOI 28nm. De plus, les ressources importantes de calcul numérique disponibles dans ces types de SoC couplées avec de nouveaux modes de captures d'images permettraient d’atteindre des niveaux de consommation d’énergie extrêmement bas tout en offrant la possibilité d’implémenter des algorithmes de traitement d’image complexes. Après une étude bibliographique sur les différentes méthodes d’acquisition d’image ainsi qu’une étude bibliographique sur les imageurs en technologies dites avancées pour l’imagerie et pour des applications basse consommation, il a été montré qu’il était nécessaire de numériser au plus tôt l’information lumineuse reçue par le capteur. C’est pourquoi le sujet a été orienté vers une architecture de type événementielle. L’architecture d’un capteur d’image événementiel avec traitement intelligent associé a été développée, en prenant en considération les contraintes liées à la technologie. Afin de définir ces contraintes, un circuit de test de pixel en FDSOI 28nm a été réalisé permettant d’évaluer la réponse électro-optique. Les pixels ont chacun des types et des tailles de photodiodes différentes afin de valider le type et la taille les plus efficaces. Deux architectures événementielles ont été étudiées durant cette thèse afin de répondre aux contraintes d’une implémentation en technologies FDSOI 28nm : une architecture de type « Time-to-first-Spike » (TTFS) avec un système d’inhibition et une architecture dite « multi-bus » utilisant les possibilités d’interconnections denses offertes par la technologie. Ces deux architectures visent à réduire le flot de données sortant ainsi que la consommation d’énergie. Les traitements associés à l’acquisition ont été validés par des simulations MATLAB émulant l’acquisition événementielle et les prétraitements. Ce système de vision extrait donc une carte binaire correspondant aux contrastes locaux en utilisant un principe d’inhibition par bloc. Cette architecture de traitement est basée sur le pixel TTFS (et son principe d’inhibition) en adaptant son implémentation. La carte binaire est extraite de manière synchrone ce qui permet d’éviter l’ajout de matériel lié à une implémentation purement événementielle. Cette carte binaire peut servir dans des applications telles que de la détection de mouvement, ou de la classification telles que la méthode des histogrammes des gradients (HoG) le permet. La carte binaire extraite se rapproche des motifs binaires locaux (LBP) qui sont des outils fréquemment utilisés dans la détection et la reconnaissance de visage. Une partie de la thèse a également été consacrée à l’exploitation des possibilités qu’offre la technologie FDSOI 28nm. Notamment des architectures pixels utilisant une photodiode sous le transistor ont été étudiées. Il a également été développé dix matrices de 3 par 3 pixels en intégration 3D séquentielle utilisant la technologie CoolCube™ du LETI<br>The goal of this thesis is to study new image acquisition paradigm in integrated vision circuits to enhance their robustness and scalability using nanometric technologies (such as the 28nm FDSOI) in order to satisfy the imaging constraints imposed by applications such as Internet of Things. In this case, a heterogeneous system-on-chip (SoC) designed in advanced technology would meet the energy consumption constraints. Using standard imagers is not compatible with this requirement because of their excessive power consumption and their architectures non-compatible with 28nm FDSOI technologies. In addition, in these SoC, significant available digital computational resources coupled with new image acquisition modes would allow ultra-low power consumption while providing the ability to implement complex image processing.After a bibliographic study on the state of the art on image acquisition methods and a study on imagers designed with advanced technologies and on low-power applications, it has been shown that it is necessary to quickly digitize light information received by the sensor (i.e. in the pixel). This is why the subject has been oriented towards an event-based vision sensor architecture.The architecture of an event-based image sensor with its associated smart processing has been developed, taking into account technology constraints. In order to define these constraints, a 28nm FDSOI pixel test circuit has been carried out to evaluate the electro-optical response. Each pixel has a different type and size of photodiodes in order to validate the most effective type and size.Two event-based architectures were studied during this thesis in order to fit with the constraints of an implementation in 28nm FDSOI technologies: a "Time-to-first-Spike" (TTFS) architecture with an inhibition system and an architecture called "multi-bus "using the dense interconnections possibilities offered by the technology. These two architectures aim to reduce the data throughput as well as energy consumption.The processing associated to the acquisition have been validated by MATLAB simulations emulating the event acquisition and pre-processing. This vision system therefore extracts a binary map corresponding to the local contrasts using block inhibition mechanism. This processing architecture is based on TTFS pixel (and its inhibition mechanism) with a dedicated pixel schematic. The binary map is extracted in a synchronous manner, thus avoiding hardware addition inherent to an AER (Adress Event Representation) implementation. This binary map can be used for applications such as motion detection, or classification such as histogram of gradient method (HoG). This extracted binary map approaches local binary patterns (LBP), which are frequently used tools in face detection and recognition.A part of this thesis has been dedicated also to the exploration of FDSOI 28nm capabilities in terms of pixel implementation. Notably, by studying pixels using a photodiode under the FDSOI transistor. It has also been developed ten 3 by 3 pixels matrices using 3D integration with LETI technology CoolCube™
29
Guidash, R. Michael. "Development of a modular 2-micron BiCMOS process from an existing 2-micron n-well CMOS process /." Online version of thesis, 1991. http://hdl.handle.net/1850/11234.
Full text
30
Duerden, Geoffrey. "The development of bipolar log-domain filters in a standard CMOS process /." Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=33967.
Full textAbstract:
Log-domain filters have emerged in recent years as a new and important class of continuous-time filter. The attractive features of these filters include their compact structure, their potential to run at high frequencies while operating from low power supplies, and their electronic tunability. At the heart of the log-domain filtering technique is the logarithmic/exponential relationship between voltage and current in a transistor. In this work, the development of log-domain filters in CMOS technology will be investigated. The lateral bipolar transistor, inherent to CMOS processes, will be used for this purpose.<br>A SPICE compatible model for a lateral PNP transistor, fabricated in 0.35mu CMOS technology, is presented. A log-domain integrator, which makes use of both lateral PNP transistors and MOSFET transistors operating in strong inversion, as well as a biquadratic low-pass log-domain filter and a third order elliptic low-pass log-domain filter, have each been designed and characterized in 0.35mu CMOS technology. Experimental results indicate that these filters are capable of operation at frequencies up to 10 MHz. For the elliptic filter operating at a bias current of 10 muA, the experimentally measured total harmonic distortion is -39.6 dB for an input current of 5 muA (a 50% current modulation index), the dynamic range is -34.1 dB, and the total power consumption is 183 muW/pole from a 2.5 V supply. These filters are capable of operating at significantly higher frequencies than CMOS log-domain filters described in the literature which make use of MOSFET transistors operating in weak inversion.
31
Echeruo, Ugonna (Ugonna Chukwudalu) 1974. "Enhanced methods for the design and test of CMOS process test vehicles." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46211.
Full textAbstract:
Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.<br>Includes bibliographical references (p. 127).<br>by Ugonna Echeruo.<br>S.B.and M.Eng.
32
Tsai, Meng-Hung, and 蔡孟宏. "Applications of CMOS MEMS Process Integration." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/21382880135893151049.
Full textAbstract:
碩士<br>國立彰化師範大學<br>機電工程學系<br>99<br>Abstract
The most favorite advantages of Complementary Metal-Oxide- Semiconductor (CMOS) are based on its standard material and fabrication and therefore it will make semiconductor manufacturers low costs and high-rate production. Nevertheless MEMS of CMOS fabrication has some drawbacks which limit its applications in sensors and actuators. Comparisons with most of the semiconductor technology, the CMOS fabrication will meet limitations and challenges. The first is that MEMS components need more complicated materials and layers. The second is that designing MEMS structure requires special fabrication processes and these processes are not in the original COMS processes.
In this thesis, we propose several advanced fabrication integrating with CMOS-compatible process. It will bring profits of standardized production and has the high performance and reliability of MEMS.
We use 0.35μm 2P4M CMOS IC compatible process and propose the new
post fabrication for COMS MEMS resonators, infrared absorption sensors and
CO gas sensors. Besides we investigate the sacrificial layer of sensors and
measure the properties of MEMS resonator, CO gas sensor and so on.
Key words： MEMS resonator, CO gas sensor, sacrificial layer
33
Yeh, Cheng-Hong, and 葉承泓. "New Cleaning Solution for Complete CMOS Process." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/69743425498484822207.
Full textAbstract:
碩士<br>國立清華大學<br>工程與系統科學系<br>89<br>In this thesis, we proposed a new advanced wet-chemical one-step cleaning process, which omits HPM step in RCA. A novel one-step cleaning solution had been developed for standard and pre-gate oxide cleaning to replace the conventional RCA two-sep cleaning recipe, which includes APM (or SC-1) and HPM (or SC-2) step. Tetra Methyl Ammonium Hydroxide (TMAH) and Ethylene Diamine Tetra Acetic acid (EDTA) were added into the RCA SC-1 cleaning solution to enhance cleaning efficiency. From the experimental results, the particle and metallic contaminations on the bare-Si wafer surface could be removed significantly by applying this novel one-step cleaning solution. The surface adsorption and double layer model could explain the surface behavior of TMAH solutions. Based on the model, the improvement on the particle, surface roughness and the metallic contaminants on the surface can be realized. It was observed that the electrical properties of MOSFET after cleaning with this novel solution were better than the conventional RCA cleaning. Besides, the cleaning method combining NH4OH, TMAH, EDTA and H2O2, at 60 °C for 5-min, shows the high performance on particle removal, metal cleaning, surface smoothness and electrical behavior. Hence, this novel one-step cleaning process is very promising for future large-size silicon wafer cleaning due to the advantages of time saving, cost down, and high performance.
34
Wang, Yu-Ting, and 王羽廷. "CMOS Process Compatible Visible-blind Ultraviolet Phototransistors." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/yd9raf.
Full textAbstract:
碩士<br>國立清華大學<br>光電工程研究所<br>106<br>With the rapid development of the IoT (Internet of Things) and smart devices, People pay more attention to and demand more need for high quality optical sensors. In recent years, tremendous progress has been reported with silicon based devices in visible range. For nonvisible range, such as in ultraviolet and Infrared region, wide bandgap material and III-V semiconductors are usually adopted, which is expensive and incompatible. Therefore, we can develop a silicon-based ultraviolet photodetector using a standard CMOS process. It can be easily integrated with the IC circuit and significantly reduce production costs.
In this thesis, we propose a new design and fabrication method of Al-SiO2-Al (metal-dielectric-metal structure) visible-blind ultraviolet Fabry-Pérot bandpass filter, integrated with the current gain increment interdigitated lateral bipolar phototransistors. We successfully demonstrate suppression of visible light with the highest responsivity 9.78E-2 (A/W) at wavelength of 350 nm.
35
Liu, Ying-Ting, and 劉映廷. "Fabrication of Infrared Thermal Emitters with Standard CMOS Process and MEMS Process." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/gf5bx4.
Full textAbstract:
碩士<br>國立臺灣科技大學<br>電子工程系<br>104<br>For the applications in infrared therapy and sensing, this thesis focuses on developing far infrared (FIR) thermal emitter devices, whose wavelength ranges from 4 ~ 12 μm. In order to manufacture thermal emitter, we utilize the polysilicon layer on silicon platform as the heating layer of the device structure. We try two platforms to fabricate FIR devices: standard CMOS foundry process and MEMS process. There are metal cross-shaped mesh filter in the FIR devices fabricated with the CMOS process, while there are two-dimensional photonic crystal structures in the MEMS devices. Devices on both platforms have periodic hole structures, which are designed to provide filtering effect in specific wavelength range. In addition to the narrowing of the emitted FIR spectrum, the periodic structure can have better confinement of the light emission direction.
The chip size of the CMOS integrated FIR emitters is 1.635 × 1.85 mm2 and the measured resistance is about 23 Ω for each device. The emitting power density of CMOS thermal emitters is measured by infrared photodetector and achieves 7 mW/cm2. The MEMS thermal emitters are designed to have peak wavelengths of 7.2 μm and 9.2 μm. The resitivity of the poly-Si layer is reduced with high doping concentration. The device size of the MEMS thermal emitters is 4.45 × 2 mm2, 4.45 × 2.4 mm2, and 4.45×2.8 mm2 respectively. The emitting power of the MEMS FIR light source can exceed 0.349 mW, and the emitting power density can reach 3.21 mW/cm2. According to the measured FIR spectrum, the wavelength filtering effect by using different periodic structures is not obvious by the FTIR measurement; and this requires further investigation.
36
Liu, Yu-Chih, and 劉育智. "Residual Stress Extraction Based on CMOS Standard Process." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/02451342613302997572.
Full textAbstract:
碩士<br>國立清華大學<br>動力機械工程學系<br>97<br>Recently, using CMOS(complementary metal oxide semiconductor) standard process fabricates MEMS (Micro-electromechanical System) device has been popularly. Integrating CMOS with MEMS can reduce the area of device, batch production and decrease the cost of production. However, the residual stress of thin film caused structure unpredictable deformation. Therefore, it is necessary to know residual stress of CMOS standard process thin film for designer.
This study design a number of cantilever structures according to CMOS design rules. These cantilever structures are deposited by different thin film. The residual stress of thin film caused the cantilever structures out-of-plane deformation. According to appropriate analytical method, the curvature of each cantilever structures can be predicted and the residual stress of CMOS standard process thin film can be extracted. Eventually, we can build up database of CMOS standard process thin film residual stress. The database can provides reference for designer that want to use CMOS standard process.
37
Hsieh, Cheng-Han, and 謝承翰. "Design of Temperature Sensor by CMOS-MEMS Process." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/05793761101211725245.
Full textAbstract:
碩士<br>國立暨南國際大學<br>電機工程學系<br>102<br>In this thesis, a design of a temperature sensor with micro cavity structure is presented for enhancing the absorptivity of incident IR energy. A variety of micro cavity structures with different aperture dimension and metal layers, as well as the incident angle and wavelength, are investigated and analyzed by ZEMAX. The micro cavity structure is fabricated in TSMC 0.18μm 1P6M CMOS-MEMS process provided by CIC. For a unit structure size of 14μm*14μm*8μm, simulation results show the improvement on absorptivity is 10% for oblique incident when compared with vertical incident; likewise, using deeper aperture also can improve absorptivity. Besides, adding lens can centralized light source toavoid reflection on top metal and to reduce the energy wasting.
38
Cavadas, Henrique Manuel Dias. "Process and Temperature Compensation of CMOS Ring Oscillators." Master's thesis, 2016. https://hdl.handle.net/10216/101348.
Full textAbstract:
In order to compensate RO's process, temperature and voltage variations (PVT) several CMOS effects have been studied such as VT sensing and Zero Temperature Coefficient (ZTC). A single-ended RO topology was analysed taking into consideration theoretical studies, PVT behavior and sensitivity to control and supply voltage. The techniques used to obtain these characterizations helped to obtain, organize and classify data in a efficient and scalable manner. The modified false-position method was implemented to characterize the RO PVT behavior efficiently for a given target oscillation frequency, allowing to explore different RO's and specific transistor influence. For classification a coefficient of determination, pronounced R squared, was implemented allowing to know the goodness of fit of a line for instance RO's control voltage, and find straight, parallel and evenly spaced lines. Analysis of the supply and control voltage sensitivity to a variation was made allowing good error prediction and a clear way for correctly knowing how to compensate variations. An ideal topology was developed for matching two sets of those lines with similar features on different circuits, containing gain, offset and coefficient of temperature.The final topology includes two Bandgap voltage references, a simple VT extractor, a Differential Amplifier and a single-end RO.
39
Bhatnagar, Mayank. "Implementing single electron device in standard CMOS process /." 2008. http://proquest.umi.com/pqdweb?did=1597619851&sid=3&Fmt=2&clientId=10361&RQT=309&VName=PQD.
Full text
40
Chen, Hui-Ling, and 陳慧菱. "A 2.4GHz PLL designed by 0.35um CMOS Process." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/50205773325885175146.
Full textAbstract:
碩士<br>中華大學<br>電機工程學系(所)<br>99<br>In many circuits, PLL “Phase Locked Loops” plays an important role in a high speed output clock to follow the slow input clock. Examples of application that uses PLL include clock and data recovery, delay locked loops, clock synthesis, and synchronization. In this thesis, our PLL is locked at 2.4GHz. By combining a VCO,which is a ring oscillator composed of 3-stage delay cell、a TSPC typePFD、a divided-by-16 frequency divider and a DC-balanced output, we obtain a low jitter performance.
The PLL have been designed and fabricated in a 0.35um TSMC CMOS Mixed Signal technology .The chip area is567 μm *672 μm. The VCO output frequency is 2400MHz. The supply voltage is 3V. The performance of peak to peak jitter is 2ps at 2.4GHz.
41
Yu, Hao-Hsiang, and 游皓翔. "W-band Phase Shifter Design in CMOS process." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t5d9bb.
Full textAbstract:
碩士<br>國立交通大學<br>電子研究所<br>106<br>Architecture for digital-control phase shifters is introduced in this thesis. The implementation of the phase shifter in W-band integrated circuits is discussed. The operational principles of the phase shifter and the characteristics of the sub-circuits are examined. Two processes, TSMC 65nm-CMOS and TSMC 40nm-CMOS, are proposed to fabricate the phase shifter. The phase shifter fed with three-bit digital signals in time sequence can offers 32 phase delay outputs within the range from 0˚ to 360˚ in a step of 11.25˚. A broadband receiver comprising the phase shifter, a mixer, a tripler, and an IF amplifier was designed and fabricated in a single chip through the 40nm-version process. The receiver offers tunable phase delays and simultaneous down-conversion for the signals. This result demonstrates the feature of high integration of the proposed phase shifter. At the end, based on the fabrication results of the phase shifters by the two proposed processes, the advantages and disadvantages of their characteristics and associated sub-circuit structures are discussed.
42
Wu, Chung-Han, and 吳宗翰. "CMOS MEMS PZT Inkjet Head Process and Design." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/k2zsry.
Full textAbstract:
碩士<br>國立臺北科技大學<br>機電整合研究所<br>93<br>This reach disclosed a method to manufacture the nano inkjet head using wafer-level fabrication process. First, use CMOS process technology on the wafer to make sub-micro jet hole, cavities, and micro-channel on the same side of the wafer. Next etch away the silicon-dioxide to get nanojet hole, cavities and micro-channel. Sputter non-wettable material around the nanojet hole to help nano-liquid ejection easily. Finally, align and bond nickel vibration membrane and piezoelectric thick film on the said silicon wafer to get the complete PZT nano-inkjet print head structure. Furthermore, the driving wave generator circuits can be designed simultaneously with the said nanojet and ring heater. Thus, a system-on-chip package nanojet print head can be obtained. Also a new refill-proof design of the said micro-channel is disclosed to aid stabilizing every ink ejection process.
43
Cavadas, Henrique Manuel Dias. "Process and Temperature Compensation of CMOS Ring Oscillators." Dissertação, 2016. https://hdl.handle.net/10216/101348.
Full textAbstract:
In order to compensate RO's process, temperature and voltage variations (PVT) several CMOS effects have been studied such as VT sensing and Zero Temperature Coefficient (ZTC). A single-ended RO topology was analysed taking into consideration theoretical studies, PVT behavior and sensitivity to control and supply voltage. The techniques used to obtain these characterizations helped to obtain, organize and classify data in a efficient and scalable manner. The modified false-position method was implemented to characterize the RO PVT behavior efficiently for a given target oscillation frequency, allowing to explore different RO's and specific transistor influence. For classification a coefficient of determination, pronounced R squared, was implemented allowing to know the goodness of fit of a line for instance RO's control voltage, and find straight, parallel and evenly spaced lines. Analysis of the supply and control voltage sensitivity to a variation was made allowing good error prediction and a clear way for correctly knowing how to compensate variations. An ideal topology was developed for matching two sets of those lines with similar features on different circuits, containing gain, offset and coefficient of temperature.The final topology includes two Bandgap voltage references, a simple VT extractor, a Differential Amplifier and a single-end RO.
44
Harish, B. P. "Process Variability-Aware Performance Modeling In 65 nm CMOS." Thesis, 2006. https://etd.iisc.ac.in/handle/2005/1080.
Full textAbstract:
With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation.
We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM).
To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets.
Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.
45
Harish, B. P. "Process Variability-Aware Performance Modeling In 65 nm CMOS." Thesis, 2006. http://hdl.handle.net/2005/1080.
Full textAbstract:
With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation.
We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM).
To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets.
Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.
46
Cao, Kaijian (Jane). "A chemical sensor design using a standard CMOS process." 2007. http://hdl.handle.net/1993/322.
Full textAbstract:
By integrating an electrochemical deposition process and a silicon chip manufacturing process, a chemical sensor based on a floating gate field-effect transistor was developed. The sensor was fabricated using the standard 0.35μm CMOS process with minimal post-processing. A pH-sensitive organic polymer was electrochemically deposited on the “pseudo” floating gate extension. This “pseudo” floating gate extension was an external area connected to the floating gate of the testing device. By monitoring the change of the current-voltage characteristics during exposure to the gas phase of the chemical aqueous solution, the sensor was shown to be feasible with a reasonable sensitivity.<br>May 2007
47
許世昕. "Low Dropout Regulator Automation Design in Nanometer CMOS Process." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/45987y.
Full text
48
Wang, Siang-Wei, and 王相為. "Millimeter-Wave Bandpass Filter Designs using Standard CMOS Process." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/78499983971577736753.
Full textAbstract:
碩士<br>國立彰化師範大學<br>電信工程研究所<br>98<br>The objective of this research is to design bandpass filters (BPF) which are to be realized using CMOS standard process and for applications in the unlicensed 40, 60, and 77-GHz millimeter-wave bands. In the first part of this thesis, a 40-GHz balanced BPF is proposed which consists of symmetrical feed lines and quarter-wavelength ( ) stepped-impedance resonators (SIRs). By properly arranging parts of the feed lines and SIRs in a parallel-coupled fashion, bandpass and bandstop characteristics can be achieved for differential-mode (DM) and common-mode (CM) operations, respectively. The designed balanced BPF is realized using TSMC 0.35-μm process and found to exhibit very good passband response (with -5.87 dB when operated differentially) and high CM rejection level (with -1.73 dB in CM operation).
In the second part of this thesis, a dual-band BPF composed of two electrical-coupled uniform-impedance resonators (UIRs) and a stub-loaded SIR (SLSIR) is designed and realized using TSMC 0.18-μm process. The two designated operating bands are cantered at 60 and 77 GHz, respectively. In this design, the use of two individual resonator types allow for design of flexible separation of these two working bands. The simulated results show that acceptable passband insertion losses (ILs) were obtained for these bands. Namely, the maximum IL is 4.2 dB for the 60-GHz band and 3 dB for the 77-GHz band. The minimum reflection losses (S11) for both bands are larger than 15 dB.
The designed BPFs in this research can be applied to commercially practical short range wireless communication systems. The design approaches presented in this research are expected to serve as a useful reference for millimeter-wave filter designers working in this and related fields.
49
HU, Chien-Yu, and 胡建煜. "Heat Conduction Type MEMS Accelerometer Design with CMOS Process." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/32279397423654588240.
Full textAbstract:
碩士<br>中華大學<br>機械與航太工程研究所<br>93<br>Accelerometer used the principle of the thermal expansion is an important research topic of Micro Electro Mechanical Systems, MEMS. Based upon the valid design, there is preferable frequency response, and high sensitivity is presented of accelerometer . In addition, the fabrication of accelerometer is compatible with the manufacture process of compensated metal oxide semiconductor (CMOS), which stands for the high competition on the cost. Accelerometer was investigated in last project.
Tanner tools, which is a kind of computer-assisted tools for the design of integrate circuit, and Micro Electro Mechanical Computer Assisted Designer IntelliSuite would be adopted on the design and analysis of accelerometer. Structure and shape model of accelerometer would be constructed in optimum design through the tools of Tanner and IntelliSuite. The motion behaviors of accelerometer would be investigated in depth.
50
Suresh, Manchala. "A Highly Linear CMOS Transconductance Amplifier in 180nm Process." Thesis, 2017. http://ethesis.nitrkl.ac.in/8823/1/2017_MT_MSuresh.pdf.
Full textAbstract:
The present work describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. In differential amplifier Harmonic distortion due to odd order harmonics because due to differential nature even order harmonics automatically cancel. In differential amplifier odd harmonics terms causes nonlinearity. In operational transconductance amplifier odd harmonics terms causes nonlinearity. Several techniques are there to improve the linearity of the operational Trans conductance amplifier one most of the most popular technique is source degeneration technique .Generally source degeneration techniques obtained by using resistors at the source this provides negative feedback .negative feedback reduces the gain as well as reduce nonlinearity terms. Another technique is attenuator followed by source degenerated differential amplifier .In this technique first stage is attenuator this attenuator gives linear attenuated differential output voltage severs as input to the source degenerated OTA. Using this technique we will get more linearity .another technique is nonlinearity cancellation technique. This technique implemented by using Balanced OTA current expression. . All these operational transconductors are designed and simulated 180nm process technology with 1.8V power supply. Using these techniques linear input range increases and third order harmonic distortion (HD3) is reduced.