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Journal articles on the topic 'CMOS process'

Author: Grafiati

Published: 4 June 2021

Last updated: 16 June 2025

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1

Yu, Ting, Ben Xian Peng, and Feng Qi Yu. "Absolute Pressure Sensor Based on Standard CMOS Process." Advanced Materials Research 875-877 (February 2014): 2238–42. http://dx.doi.org/10.4028/www.scientific.net/amr.875-877.2238.

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A CMOS compatible absolute pressure sensor with extend floating gate is developed with simple circuitry to realize high sensitivity, linearity, and manufacturability. The pressure sensitive membrane formation is based on the standard CMOS process with simple metal sacrificial layer removal step, which is very cost-efficient and fully CMOS compatible, enabling monolithic integration of circuitry. ANSYS and SPICE simulation results show that the proposed sensor can worked properly under 500K Pa, and the square sensing membrane of 100x100 μm 2 shows a good linearity over a pressure change ranging from 5 Pa to 500K Pa.

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2

Uchino, T., P. Ashburn, Y. Kiyota, and T. Shiba. "A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling." IEEE Transactions on Electron Devices 51, no. 1 (2004): 14–19. http://dx.doi.org/10.1109/ted.2003.820643.

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3

JOUVET, N., M. A. BOUNOUAR, S. ECOFFEY, et al. "RECENT DEVELOPMENTS ON 3D INTEGRATION OF METALLIC SET ONTO CMOS PROCESS FOR MEMORY APPLICATION." International Journal of Nanoscience 11, no. 04 (2012): 1240024. http://dx.doi.org/10.1142/s0219581x12400248.

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This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.

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4

Linares Aranda, Mónico, W. Calleja Arriaga, A. Torres Jacome, and C. R. Báez Álvarez. "A modular and generic monolithic integrated MEMS fabrication process." Superficies y Vacío 30, no. 3 (2017): 30–39. http://dx.doi.org/10.47566/2017_syv30_1-030030.

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A modular and generic, monolithic integrated MEMS fabrication process is presented to integrate microelectronics (CMOS) with mechanical microstructures (MEMS). The proposed monolithic integrated fabrication process is designed using an intra-CMOS approach (to fabricate the mechanical microstructures into trenches without the need of planarization techniques) and a CMOS module (to fabricate the electronic devices) with a 3 ?m length as minimum feature. The microstructures module is made up to three polysilicon layers, and aluminum as electrical interconnecting material. From simulation results, using the SILVACO® suite (Athena and Atlas frameworks), no significant degradation on the CMOS performance devices was observed after MEMS manufacturing stage; however, the thermal budget of the modules plays a crucial role, because it set the conditions for obtaining the complete set of devices fabricated near their optimal point. Finally, to evaluate and to support the development of the proposed integrated MEMS process, a modular test chip that includes electrical test structures, mechanical test structures, interconnection reliability test structures and functional micro-actuators, was also designed.

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Haond, M., M. T. Basso, E. deCoster, J. Guelen, and C. Lair. "Developing a 0.18-micron CMOS process." IEEE Micro 19, no. 5 (1999): 16–22. http://dx.doi.org/10.1109/40.798105.

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6

Hallam, P., P. J. Mather, and M. Brouwer. "CMOS process independent propagation delay macromodelling." Electronics Letters 31, no. 9 (1995): 702. http://dx.doi.org/10.1049/el:19950476.

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7

Pichler, P., A. Burenkov, J. Lorenz, C. Kampen, and L. Frey. "Future challenges in CMOS process modeling." Thin Solid Films 518, no. 9 (2010): 2478–84. http://dx.doi.org/10.1016/j.tsf.2009.09.150.

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8

Yu, Le, Yaozu Guo, Haoyu Zhu, Mingcheng Luo, Ping Han, and Xiaoli Ji. "Low-Cost Microbolometer Type Infrared Detectors." Micromachines 11, no. 9 (2020): 800. http://dx.doi.org/10.3390/mi11090800.

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The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.

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9

Shawkat, Mst Shamim Ara, Mohammad Habib Ullah Habib, Md Sakib Hasan, Mohammad Aminul Haque, and Nicole McFarlane. "Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes." International Journal of High Speed Electronics and Systems 27, no. 03n04 (2018): 1840018. http://dx.doi.org/10.1142/s0129156418400189.

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A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

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10

Zhang, Chenyu, Nairui Hu, and Zhaoyang Liu. "The Simulation of the Terahertz Modulator by CMOS Process." Journal of Physics: Conference Series 2478, no. 6 (2023): 062038. http://dx.doi.org/10.1088/1742-6596/2478/6/062038.

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Abstract The paper introduced the simulation of the terahertz modulator in complementary metal-oxide-semiconductor (CMOS) process. The modulator is composed of a metal split-ring resonator (SRR), CMOS, semiconductor dielectric layer and silicon substrate. The modulator can make different electromagnetic response to the transmitted terahertz wave between the connection state and the disconnection state of the gap in the SRR, which could be achieved by connecting CMOS in the gap. At 0.31THz, the simulation results show that the amplitude modulation depth of the modulator reached 28.8%. When the simulation keeped the modulator system in resonating state, the transmission coefficient was about 0.0018, while the conductive had reached 0.2895. If the design can pass the experimental verification in the future, it can make some references for further exploration of the high-speed and high modulation depth of the terahertz amplitude modulator.

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11

Parameswaran, M., Lj Ristic, A. C. Dhaded, H. P. Baltes, W. Allegretto, and A. M. Robinson. "Fabrication of microbridges in standard complementary metal oxide semiconductor technology." Canadian Journal of Physics 67, no. 4 (1989): 184–89. http://dx.doi.org/10.1139/p89-032.

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Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by first implementing a special layout design in an industrial digital CMOS process, followed by a postprocessing etching step.

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12

Marfungah, Siti, and Suartini Suartini. "The Position Of Commitment-Making Officials As Legal Subjects In Disputes Over Construction Service Agreements In Indonesian Courts." Eduvest - Journal of Universal Studies 4, no. 11 (2024): 10015–25. http://dx.doi.org/10.59188/eduvest.v4i11.1603.

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The role of the Commitment Making Officer (CMO) is crucial because they are responsible for the procurement process and contract implementation. However, disputes often occur regarding the CMO's legal position in the agreement. This study aims to examine in depth how courts in Indonesia view and regulate the legal position of CMO as a legal subject in the settlement of construction service agreement disputes. This study uses normative legal research methods with legislative and comparative approaches. The results showed that courts in Indonesia tend to position CMO as a legal subject that has significant responsibilities in construction service agreement disputes. CMOs are given the role of being responsible for the implementation of the contract and can be a party directly involved in dispute resolution in court. The analysis also reveals variations in the legal treatment of CMOs from case to case, highlighting the complexities in the interpretation and application of the relevant laws. Recommendations from this research include the need for further clarification in the legal regulations governing the position of CMOs, as well as the importance of better legal education regarding the responsibilities of CMOs in the context of construction service agreement disputes.

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13

Lv, Hongming, Huaqiang Wu, Jinbiao Liu, et al. "Inverted process for graphene integrated circuits fabrication." Nanoscale 6, no. 11 (2014): 5826–30. http://dx.doi.org/10.1039/c3nr06904d.

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14

Poehls, L. M. Bolzani, M. C. R. Fieback, S. Hoffmann-Eifert, et al. "Review of Manufacturing Process Defects and Their Effects on Memristive Devices." Journal of Electronic Testing 37, no. 4 (2021): 427–37. http://dx.doi.org/10.1007/s10836-021-05968-8.

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AbstractComplementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective production, will become infeasible below a certain feature size. In parallel, emerging applications including Internet-of-Things (IoT) and big data applications present high demands in terms of storage and computing capability, combined with challenging constraints in terms of size, power consumption and response latency. In this scenario, memristive devices have become promising candidates to complement the CMOS technology due to their CMOS manufacturing process compatibility, great scalability and high density, zero standby power consumption and their capacity to implement high density memories as well as new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause unique faulty behaviors that are not seen in CMOS, increasing significantly the complexity of test procedures. This paper provides a review about the manufacturing process of memristives devices, focusing on Valence Change Mechanism (VCM)-based memristive devices, and a comparative analysis of the CMOS and memristive device manufacturing processes. Moreover, this paper identifies possible manufacturing failure mechanisms that may affect these novel devices, completing the list of the already known mechanisms, and provides a discussion about possible faulty behaviors. Note that the identification of these mechanisms provides insights regarding the possible memristive devices’ defective behaviors, enabling to derive more accurate fault models and consequently, more suitable test procedures.

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15

Ki, Donghan, Minwoong Lee, Namho Lee, and Seongik Cho. "Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect." Electronics 12, no. 15 (2023): 3331. http://dx.doi.org/10.3390/electronics12153331.

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This study designed a radiation-hardened (RH) complementary metal oxide semiconductor (CMOS) logic circuit based on an RH variable-gate (V-gate) n-MOSFET that was resistant to the total ionizing dose (TID) effect and evaluated its tolerance to radiation. Among the different CMOS logic circuits, NOT, NAND, and NOR gates were designed using V-gate n-MOSFETs by employing layout transformation techniques and standard p-MOSFETs. Before the process design, we predicted the radiation damage using modeling and simulation techniques and validated the tolerance by conducting actual radiation tests after the process design. Furthermore, we implemented the CMOS logic circuit process design in a 0.18 µm CMOS bulk process. The actual radiation test applied a total cumulative radiation dose of 25 kGy at 5 kGy per hour in a high-level gamma-ray irradiation facility. Consequently, the resistance of the RH CMOS logic circuit based on the RH V-gate n-MOSFET to the TID effect was validated through experiments.

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16

Wakita, Kosuke, Eiichi Sano, Masayuki Ikebe, et al. "Design and Fabrication of Terahertz Detectors Based on 180-nm CMOS Process Technology." International Journal of High Speed Electronics and Systems 25, no. 03n04 (2016): 1640014. http://dx.doi.org/10.1142/s0129156416400140.

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A CMOS cascode amplifier, biased near the threshold voltage of a MOSFET, for terahertz direct detection is proposed. A CMOS terahertz imaging circuit (size: 250 × 180 ìm) is designed and fabricated on the basis of low-cost 180-nm CMOS process technology. The imaging circuit consists of a microstrip patch antenna, an impedance-matching circuit, and a direct detector. It achieves a responsivity of 51.9 kV/W at 0.915 THz and a noise equivalent power (NEP) of 358 pW/Hz1/2 at a modulation frequency of 31 Hz. NEP is estimated to be reduced to 42 pW/Hz1/2 at 100 kHz. These results suggest that cost-efficient terahertz imaging is possible in the near future.

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17

Perez, Maximiliano S., Betiana Lerner, Daniel E. Resasco, et al. "Carbon Nanotube Integration with a CMOS Process." Sensors 10, no. 4 (2010): 3857–67. http://dx.doi.org/10.3390/s100403857.

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18

BABA, Toshihiko. "Silicon Photonics Based on CMOS-Compatible Process." Review of Laser Engineering 42, no. 3 (2020): 223. http://dx.doi.org/10.2184/lsj.42.3_223.

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19

Swirhun, S. E., E. Sangiorgi, A. J. Weeks, R. M. Swanson, K. C. Saraswat, and R. W. Dutton. "A VLSI-Suitable Schottky-Barrier CMOS Process." IEEE Journal of Solid-State Circuits 20, no. 1 (1985): 114–22. http://dx.doi.org/10.1109/jssc.1985.1052283.

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20

Saha, Samar K. "Modeling Process Variability in Scaled CMOS Technology." IEEE Design & Test of Computers 27, no. 2 (2010): 8–16. http://dx.doi.org/10.1109/mdt.2010.50.

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21

Keane, John P., Chris H. Kim, Qunzeng Liu, and Sachin S. Sapatnekar. "Process and Reliability Sensors for Nanoscale CMOS." IEEE Design & Test of Computers 29, no. 5 (2012): 8–17. http://dx.doi.org/10.1109/mdt.2012.2211561.

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22

Mather, P. J., M. Brouwer, and P. Hallam. "CMOS-process-independent average power dissipation macromodelling." Electronics Letters 31, no. 16 (1995): 1337–38. http://dx.doi.org/10.1049/el:19950914.

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23

Daga, J. M., S. Turgis, and D. Auvergne. "Inverter delay modelling for submicrometre CMOS process." Electronics Letters 32, no. 22 (1996): 2070. http://dx.doi.org/10.1049/el:19961394.

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24

Parpia, Z., C. A. T. Salama, and R. A. Hadaway. "A CMOS-compatible high-voltage IC process." IEEE Transactions on Electron Devices 35, no. 10 (1988): 1687–94. http://dx.doi.org/10.1109/16.7374.

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25

Volz, C., and L. Blossfeld. "A high-performance bipolar/CMOS process-CIT2." IEEE Transactions on Electron Devices 35, no. 11 (1988): 1861–65. http://dx.doi.org/10.1109/16.7398.

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26

Swirhun, S. E., E. Sangiorgi, A. J. Weeks, R. M. Swanson, K. C. Saraswat, and R. W. Dutton. "A VLSI-suitable Schottky-barrier CMOS process." IEEE Transactions on Electron Devices 32, no. 2 (1985): 194–202. http://dx.doi.org/10.1109/t-ed.1985.21929.

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27

Lin, Wen, M. L. Chen, R. H. Doklan, and C. Y. Lu. "Dopant diffusion in poly gate CMOS process." Solid-State Electronics 32, no. 11 (1989): 965–69. http://dx.doi.org/10.1016/0038-1101(89)90157-3.

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28

Saul, P. H., D. W. Howard, and C. J. Greenwood. "VLSI process compatible 8 bit CMOS DAC." IEE Proceedings E Computers and Digital Techniques 132, no. 2 (1985): 99. http://dx.doi.org/10.1049/ip-e.1985.0014.

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29

Wenbin, Zhao, Chen Haifeng, Xiao Zhiqiang, Li Leilei, and Yu Zongguang. "W-plug via electromigration in CMOS process." Journal of Semiconductors 30, no. 5 (2009): 056001. http://dx.doi.org/10.1088/1674-4926/30/5/056001.

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30

Saul, P. H., D. W. Howard, and C. J. Greenwood. "VLSI process compatible 8 bit CMOS DAC." IEE Proceedings I Solid State and Electron Devices 132, no. 2 (1985): 99. http://dx.doi.org/10.1049/ip-i-1.1985.0021.

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31

Ng, W. T., and C. A. T. Salama. "A CMOS-compatible complementary SINFET HVIC process." IEEE Transactions on Electron Devices 38, no. 8 (1991): 1935–42. http://dx.doi.org/10.1109/16.119036.

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32

Roy, Avisek, Mehdi Azadmehr, Bao Q. Ta, Philipp Häfliger, and Knut E. Aasmundtveit. "Design and Fabrication of CMOS Microstructures to Locally Synthesize Carbon Nanotubes for Gas Sensing." Sensors 19, no. 19 (2019): 4340. http://dx.doi.org/10.3390/s19194340.

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Carbon nanotubes (CNTs) can be grown locally on custom-designed CMOS microstructures to use them as a sensing material for manufacturing low-cost gas sensors, where CMOS readout circuits are directly integrated. Such a local CNT synthesis process using thermal chemical vapor deposition (CVD) requires temperatures near 900 °C, which is destructive for CMOS circuits. Therefore, it is necessary to ensure a high thermal gradient around the CNT growth structures to maintain CMOS-compatible temperature (below 300 °C) on the bulk part of the chip, where readout circuits are placed. This paper presents several promising designs of CNT growth microstructures and their thermomechanical analyses (by ANSYS Multiphysics software) to check the feasibility of local CNT synthesis in CMOS. Standard CMOS processes have several conductive interconnecting metal and polysilicon layers, both being suitable to serve as microheaters for local resistive heating to achieve the CNT growth temperature. Most of these microheaters need to be partially or fully suspended to produce the required thermal isolation for CMOS compatibility. Necessary CMOS post-processing steps to realize CNT growth structures are discussed. Layout designs of the microstructures, along with some of the microstructures fabricated in a standard AMS 350 nm CMOS process, are also presented in this paper.

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33

Wong, Hei. "Abridging CMOS Technology." Nanomaterials 12, no. 23 (2022): 4245. http://dx.doi.org/10.3390/nano12234245.

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LIU, T. M., R. G. SWARTZ, and T. Y. CHIU. "HIGH PERFORMANCE ECL-BiCMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 04, no. 03 (1993): 283–99. http://dx.doi.org/10.1142/s0129156493000133.

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With the increasing maturity of conventional Bipolar-CMOS (BiCMOS) technologies, a new category of BiCMOS called "ECL-BiCMOS" or high performance BiCMOS technology has emerged. These ECL-BiCMOS technologies offer not only high density CMOS capability, but also feature high speed bipolar devices for emitter couple logic (ECL) and mixed analog/digital applications. Since many process requirements of advanced bipolar technology differ from those of CMOS, to fabricate high speed bipolar devices without compromising CMOS performance is the primary challenge. In this paper, we discuss key process integration issues and review various approaches. In particular, we describe a recently developed half-micron super self-aligned BiCMOS technology. Together with high density/high speed CMOS, multi-GHz communication bipolar circuit results are presented to show the potential of high performance BiCMOS technology.

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35

Weng, Chun Jen. "Etching Process Effects of CMOS Transistor Gate Manufacturing Nanotechnology Fabrication Integration." Applied Mechanics and Materials 83 (July 2011): 91–96. http://dx.doi.org/10.4028/www.scientific.net/amm.83.91.

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As the nanotechnology gate is scaling down, the fabrication technology of gate spacer for CMOS transistor becomes more critical in manufacturing processes. For CMOS technologies, sidewall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. A sidewall spacer patterning technology yields critical dimension variations of minimum-sized features much smaller than that achieved by optical Complementary Metal–Oxide–Semiconductor (CMOS) fabrication processes integration. The present study is to overcome the fabrication limitations and more particularly focus on etching processes integration on structural and formation processing for complementary metal oxide semiconductor nanofabrication process on gate spacer technology and electrical characteristics performance of nanotechnology gate structure were included. Based on the investigation of the etching effect and interface film variation on the electrical characteristics of the gate oxide on etching profile and their impacts on the sidewall transistor gate structure, a novel etching integration process for optimal controlled sidewall gate spacer fabrication was developed.

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36

Jonak-Auer, I., and S. Jessenig. "Processing of an Integrated Optical Sensor with Almost 100% Quantum Efficiency." Key Engineering Materials 644 (May 2015): 45–48. http://dx.doi.org/10.4028/www.scientific.net/kem.644.45.

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We report on a new fabrication process of integrated PIN photodetectors with very high quantum efficiencies into a 0.35μm CMOS process, including improved processing for bottom antireflective coating (BARC). The integration process is such that complete modularity of the CMOS process remains untouched by the implementation of the highly efficient photodetectors. Due to the fact that only two additional masks and one ion implantation step are necessary for the implementation of PIN photodetectors including BARC, this integration process also proves to be very cost effective. In-house processed p-doped intrinsic layers with EPI doping levels as low as 1∙1012/cm3 serve as CMOS base material. This is a doping level that major semiconductor vendors could not provide. With just one additional mask and ion implantation we provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photodetectors highly benefit from the low doping concentrations of the intrinsic EPI. Special surface protection techniques are performed to maintain the low doping concentrations of the substrate during the complete CMOS processing. To further enhance the photosensor’s quantum efficiency especially of photodetector arrays we present a new BARC process. With this new BARC process we can lower the dark current in photodiode arrays by at least one order of magnitude compared to currently established plasma-etch methods. The following photodiode parameters could be accomplished for 100x100μm2 single photodiodes with BARC: quantum efficiencies of 76%, 99.8% and 74% at wavelengths of 500nm, 675nm and 850nm, respectively, capacitances of 0.13pF and dark currents of 1.18pA for unbiased photodiodes.

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Tong, Yushang. "Simulation and optimization of metal gate CMOS process and circuit by TCAD." Journal of Physics: Conference Series 2634, no. 1 (2023): 012011. http://dx.doi.org/10.1088/1742-6596/2634/1/012011.

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Abstract The feature size of CMOS transistors is shrinking as the semiconductor industry and technology advance. This phenomenon will have significant research implications for how to change device performance and maintain good performance. As a result, this paper completed a design and simulation of the CMOS process flow using TCAD. It was discovered through a qualitative analysis of the simulation results that the transfer and input characteristics of NMOS transistors decrease proportionally with the scale factor.

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Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

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Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

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39

Zolnikov, Vladimir, Svetlana Evdokimova, Irina ZHuravlyeva, Elena Maklakova, and Anna Ilunina. "FEATURES OF THE TECHNOLOGICAL PROCESS OF MANUFACTURING SPACE-BASED MICROCHIPS USING CMOS KNS TECHNOLOGY." Modeling of systems and processes 13, no. 3 (2020): 53–58. http://dx.doi.org/10.12737/2219-0767-2020-13-3-53-58.

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The article deals with the technological process of manufacturing CMOS integrated circuits on KNS (silicon on sapphire) structures for space purposes. The technology is based on an n-type CMOS process with one level of polysilicon and two levels of metal. The components of the technological process are analyzed. The sequence of the technological process and its features are given. An example of a description of one of the elements is considered.

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40

Kempf, P., R. Hadaway, and J. Kolk. "Complementary metal oxide semiconductor compatible high-voltage transistors." Canadian Journal of Physics 65, no. 8 (1987): 1003–8. http://dx.doi.org/10.1139/p87-161.

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The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

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41

Jeong, Sang-Hun, Nam-Ho Lee, Min-Woong Lee, and Seong-Ik Cho. "Analysis of Radiation Effects in CMOS 0.18um Process Unit Devices." Transactions of The Korean Institute of Electrical Engineers 66, no. 3 (2017): 540–44. http://dx.doi.org/10.5370/kiee.2017.66.3.540.

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Wang, Wei, Xiaoyuan Bao, Li Chen, Ting Chen, Guanyu Wang та Jun Yuan. "High photon detection efficiency single photon avalanche diode in 0.18 μm standard CMOS process". Modern Physics Letters B 31, № 17 (2017): 1750193. http://dx.doi.org/10.1142/s0217984917501937.

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This paper proposed a single photon avalanche diodes (SPADs) designed with 0.18 [Formula: see text] standard CMOS process. One of the major challenges in CMOS SPADs is how to raise the low photon detection efficiency (PDE). In this paper, the device structure and process parameters of the CMOS SPAD are optimized so as to improve PDE properties which have been investigated in detail. The CMOS SPADs are designed in p+/n-well/deep n-well (DNW) structure with the p-sub and the p-well guard ring (GR). The simulation results show that with the p-well GR, the quantum efficiency (QE) is about 80% with the breakdown voltage of 12.7 V, the unit responsivity is as high as 0.38 A/W and the PDE of 51% and 53% is obtained when the excess bias is at 1 V and 2 V, respectively. The dark count rate (DCR) is 6.2 kHz when bias voltage is 14 V. With the p-sub GR, the breakdown voltage is 13 V, the unit responsivity is up to 0.26 A/W, the QE is 58%, the PDE is 33% and 37% at excess bias of 1 V and 2 V, respectively. The DCR is 3.4 kHz at reverse bias voltage of 14 V.

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Li, Mingzhe. "A Method for Reducing Offset in CMOS Operational Amplifiers." Applied and Computational Engineering 128, no. 1 (2025): 37–42. https://doi.org/10.54254/2755-2721/2025.20230.

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In the development of integrated circuits, operational amplifiers are indispensable basic units CMOS operational amplifiers are the core components in analog integrated circuits, which are widely used in signal acquisition, data processing, communications and other fields. components in analog integrated circuits, which are widely used in signal acquisition, data processing, communications and other fields, and their performance has a direct impact on the accuracy and stability of the entire system. With the continuous development of electronic technology, CMOS operational amplifiers play a vital role. operational amplifiers play a vital role in many fields. However, the misalignment problem has been one of the key factors affecting the performance of However, the misalignment problem has been one of the key factors affecting the performance of CMOS operational amplifiers. This paper introduces the basic principles of CMOS operational amplifiers, thoroughly studies the phenomenon of CMOS operational amplifiers' misalignment. This paper introduces the basic principles of CMOS operational amplifiers, thoroughly studies the phenomenon of CMOS operational amplifiers' misalignment, the definition and sources of the misalignment voltage and its effects, and analyzes the main reasons for its generation, including device mismatch, process deviation, and so on. In this paper, we summarize several methods to reduce distortion from dynamic distortion elimination technology and design and process optimization, which can effectively reduce the distortion voltage of CMOS op amps. The main dynamic misalignment elimination techniques are chopping and auto-zeroing, as well as a special form of auto-zeroing, i.e., correlation dual- sampling technique. Design and process optimization includes two methods of device selection and matching optimization and circuit topology design.

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KANG, XIAOXU, QINGYUN ZUO, CHAO YUAN, SHOUMIAN CHEN, and YUHANG ZHAO. "LOW STRESS TaN THIN FILM DEVELOPMENT FOR MEMS/SENSOR ELECTRODE APPLICATION." Journal of Circuits, Systems and Computers 22, no. 09 (2013): 1340017. http://dx.doi.org/10.1142/s0218126613400173.

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TaN \ Ta is the excellent material against copper diffusion, and is widely used as Cu diffusion barrier in Complementary Metal-Oxide-Semiconductor (CMOS) Back End of Line ( Cu -BEOL) process. Due to its good electrical and thermal property, TaN is also evaluated as electrode material for Micro-Electro-Mechanical Systems (MEMS)/sensor application. In this work, CMOS compatible MEMS based bolometer process with post-interconnect CMOS-MEMS single chip integration scheme was developed on 200 mm standard CMOS Cu BEOL, and TaN thin film was used as key electrode material in micro-bridge structure. The micro-bridge structure, with sensing resistor on surface of the micro-bridge, forms a resonant cavity for IR absorption. There are only several layers of thin film on the micro-bridge, and stress of the electrode layer play very important role to determine the performance of the micro-bridge. Additionally sheet resistance of TaN electrode should be controlled at around 377 Ohm/SQ to match the free space impedance, which is much higher than CMOS baseline process. Low stress and high resistivity TaN film was developed with thickness of 200 Å and compressive stress of about 900 MPa as best condition. From the electrical and physical data, the optimized TaN film process can well match this application.

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Dave, Marshnil, Maryam Shojaei Baghini, and Dinesh Kumar Sharma. "A process and temperature compensated current reference circuit in CMOS process." Microelectronics Journal 43, no. 2 (2012): 89–97. http://dx.doi.org/10.1016/j.mejo.2011.11.008.

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Zaziabl, Adam. "A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS Process". International Journal of Electronics and Telecommunications 56, № 4 (2010): 411–16. http://dx.doi.org/10.2478/v10177-010-0055-7.

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A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS ProcessDemand of modern measurement systems in submicron CMOS process introduced new challenges in design of low power high frequency clock generation systems. Technical possibilities for clock generation using classical oscillator based on a quartz filter is limited to tens of megahertz. Thus, 1 GHz clock generation is not possible without a frequency multiplier system. It is difficult to achieve, because in submicron process, where the integration of analog and digital blocks poses serious challenges. The proposed solution is a low power charge pump phase-locked loop (CPPLL) with the center frequency of 1 GHz. It combines various modern circuit techniques, whose main aim is to lower power consumption, which is below 800 μW for the whole PLL, while maintaining good noise properties, where the jitter rms is 8.87 ps. The proposed phase-locked loop is designed in 0.18 μm CMOS process.

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GABARA, THAD. "PULSED LOW POWER CMOS." International Journal of High Speed Electronics and Systems 05, no. 02 (1994): 159–77. http://dx.doi.org/10.1142/s0129156494000097.

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A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipolar, diodes, JFETs are not required to generate this low power capability; (4) the Conventional CMOS process is used to fabricate the circuit; (5) the same physical layout can be used either as a PPS CMOS circuit or as a Conventional CMOS circuit; (6) the device count is the same as that of Conventional CMOS; (7) PPS CMOS uses quasistatic logic levels; (8) capacitive coupling is used to store and restore the contents of a memory cell; (9) the parasitic diodes of the MOS devices are used to improve the noise margin of the circuit; (10) PPS CMOS can easily hold a static state and have the same low power dissipation properties of data inactive Conventional CMOS.

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Yang, Lung-Jieh, Reshmi Waikhom, Horng-Yuan Shih, and Yi-Kuen Lee. "Foundry Service of CMOS MEMS Processes and the Case Study of the Flow Sensor." Processes 10, no. 7 (2022): 1280. http://dx.doi.org/10.3390/pr10071280.

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The complementary metal-oxide-semiconductor (CMOS) process is the main stream to fabricate integrated circuits (ICs) in the semiconductor industry. Microelectromechanical systems (MEMS), when combined with CMOS electronics to form the CMOS MEMS process, have the merits of small features, low power consumption, on-chip circuitry, and high sensitivity to develop microsensors and micro actuators. Firstly, the authors review the educational CMOS MEMS foundry service provided by the Taiwan Semiconductor Research Institute (TSRI) allied with the United Microelectronics Corporation (UMC) and the Taiwan Semiconductor Manufacturing Company (TSMC). Taiwan’s foundry service of ICs is leading in the world. Secondly, the authors show the new flow sensor integrated with an instrumentation amplifier (IA) fabricated by the latest UMC 0.18 µm CMOS MEMS process as the case study. The new flow sensor adopted the self-heating resistive-thermal-detector (RTD) to sense the flow speed. This self-heating RTD half-bridge alone gives a normalized output sensitivity of 138 µV/V/(m/s)/mW only. After being integrated with an on-chip amplifier gain of 20 dB, the overall sensitivity of the flow sensor was measured and substantially improved to 1388 µV/V/(m/s)/mW for the flow speed range of 0–5 m/s. Finally, the advantages of the CMOS MEMS flow sensors are justified and discussed by the testing results.

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Yelamarthi, Kumar, and Chien-In Henry Chen. "Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations." VLSI Design 2010 (March 7, 2010): 1–13. http://dx.doi.org/10.1155/2010/230783.

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The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool.

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Dehlinger, Dietrich, Benjamin Sullivan, Sadik Esener, Dalibor Hodko, Paul Swanson, and Michael J. Heller. "Automated Combinatorial Process for Nanofabrication of Structures Using Bioderivatized Nanoparticles." JALA: Journal of the Association for Laboratory Automation 12, no. 5 (2007): 267–76. http://dx.doi.org/10.1016/j.jala.2007.05.006.

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A fully automated electronic microarray control system (Nanochip 400 System) was used to carry out a combinatorial process to determine optimal conditions for fabricating higher order three-dimensional nanoparticle structures. Structures with up to 40 layers of bioderivatized nanoparticles were fabricated on a 400-test site CMOS microarray using the automated Nanochip 400 System. Reconfigurable electric fields produced on the surface of the CMOS microarray device actively transport, concentrate, and promote binding of 40 nm biotin- and streptavidin-derivatized nanoparticles to selected test sites on the microarray surface. The overall fabrication process including nanoparticle reagent delivery to the microarray device, electronic control of the CMOS microarray and the optical/fluorescent detection, and monitoring of nanoparticle layering are entirely controlled by the Nanochip 400 System. The automated nanoparticle layering process takes about 2 minutes per layer, with 10–20 seconds required for the electronic addressing and binding of nanoparticles, and roughly 60 seconds for washing. The addressing and building process is monitored by changes in fluorescence intensity as each nanoparticle layer is deposited. The final multilayered 3D structures are about 2 μm in thickness and 55 μm in diameter. Multilayer nanoparticle structures and control sites on the microarray were verified by SEM analysis.

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