Academic literature on the topic 'CMOS technology'

The metal-oxide-semiconductor field effect transistor (MOSFET) has been scaling down aggressively over many technology nodes in order to follow Moore's Law predictions. Strain engineering to the device channel can modify the band structure and so enhance carrier mobility. It has widely been incorporated to improve device performance. Novel modelling techniques, including strain effects, are necessarily required. The electrical characteristics of semiconductor hav9r.their origin in energy band structure. In this thesis, a new semi-analytical model is developed lor describing the energy band structure under strain conditions. Furthermore, the band parameters of the SiGe heterojunction are generalised for different combinations of Ge fractions. Those results can be used to understand and to model the transport properties of carriers and the variation of threshold voltage measured from strained Si MOSFETs. The calculated band parameters are then entered into a newly developed model to calculate the threshold voltage variation in strained Si MOSFETs having a dual channel architecture. Finally, understanding the strain effects on the band structure is extended to the modelling of strained-induced variation of carrier mobility using the piezoresistance concept. The overviews of each main-result chapter in this thesis are given below: In Chapter 3, model using the original k'p method for the energy dispersion of holes in the inversion layer of p-MOSFETs is complicated and demands extensive computational resource. Those are the reasons why the development of simulations for p-MOSFETs lagged behind their n-MOSFET counterpart. In this work, the band structure for holes in an inversion layer is dramatically simplified using a new semi-analytical model. It is described by novel non-parabolic and anisotropic expressions such that the overall computational complexity is significantly reduced compared to a fully numerical treatment. Here, the band parameters are also generalised for different Ge fractions in a SiJ-xGexfilm grown on a relaxed SiJ.yGeyvirtual substrate. In Chapter 4, an analytical model of threshold voltage for globally strained SiiSiGe CMOS devices using a dual channel architecture is developed. A model to calculate threshold voltage is developed which includes effects of device geometry, material properties, such as band parameters and permittivity, and channel and substrate doping concentrations. The threshold voltage roll-off due to short channel effects is included using the voltage-doping transformation. The proposed model is validated in agreement with simulations and experiments. It provides a physical insight for the variation of threshold voltage for both n- and p-MOSFETs having a dual channel architecture and it can be generalised to apply to single channel devices also. In Chapter 5, the conventional piezoresistance model has commonly been used to describe mobility enhancement for low levels of process induced strain in CMOS technology. However, many reports show it failing at the high levels of stress needed for future technology generations. This is because approximations made are only valid for very low stress levels. The piezomobility formulation removes an approximation assumed in the commonly-used piezoresistance model and improves its accuracy to much higher stress regimes while retaining its simplicity. The validity of the new formulation is demonstrated for Monte Carlo simulations of mobility, nMOSFETs, pMOSFETs, and nanowires in stress regimes where the commonly-used piezoresistance model has previously been reported to fail.

Un des défis majeurs de l’Internet des Objets et, plus généralement, des tous les réseaux de capteurs sans fils, c’est l’alimentation de chaque nœud connecté. La solution la plus commune est d’équiper chaque dispositif d’une batterie mais cela introduit plusieurs contraintes, qui mettent en question la faisabilité de cette approche sur le long terme (durée de vie limité, couts de gestion élevé, empreinte écologique).Cette thèse développe une possible solution basée sur la transmission sans-fils de l’énergie. Un récupérateur d’énergie RF, composé d’une antenne, un redresseur haute-fréquence et un convertisseur élévateur, est présenté. Ce système permet de récupérer les ondes électromagnétiques et de produire une tension continue en sortie, qui peut être utilisé pour alimenter des microcontrôleurs ou des capteurs. L’absence d’une batterie interne augmente la flexibilité globale, surtout pour les situations où le remplacement n’est pas possible (ex. dispositifs implantés, nombre élevé de nœuds, milieux dangereux). Une étude approfondie sur les redresseur intégrés ultra-haute-fréquence de type Schottky et MOS a été mené ; plusieurs topologies ont été analysées et optimisées. De plus, l’utilisation d’un convertisseur élévateur a été envisagée, dans le but d’accroitre la tension en sortie ; une première version discrète et puis une plus compacte version intégrée, ont été abordées et testées. Ces développements ont permis d’aboutir à un récupérateur complet, potentiellement capable d’alimenter un microcontrôleur du commerce<br>One of the challenges of the Internet of Things and, more in general, of every wireless sensor network is to provide electrical power to every single one of its smart nodes. A typical solution uses batteries but various major concerns reduce the long-term feasibility of this approach (limited lifetime, maintenance and replacement costs, and environmental footprint).This thesis develops a possible solution based on the wireless transmission of power. A complete RF harvester composed of an antenna, a UHF rectifier and a step-up voltage converter is presented. This system captures electromagnetic waves and converts them to a stable DC voltage to supply power to common logic circuits like microcontrollers and sensors. The lack of an internal battery provides an extended flexibility, especially when its replacement is not a viable option (ex. implanted devices, large number of nodes, dangerous environments, etc.). An in-depth study of integrated Schottky and CMOS UHF rectifiers is carried out; various topologies and optimizations are analyzed. Moreover, the use of an additional step-up converter is proposed in order to increase the system output voltage; an early discrete implementation and a final, more compact, integrated version are discussed and tested. These developments lead to a complete system capable of potentially powering an application with an off-the-shelf microcontroller

Referências de tensão são blocos fundamentais em uma série de aplicações de sinais mistos e de rádio frequência, como por exemplo, conversores de dados, PLL's e conversores de potência. A implementação CMOS mais usada para referências de tensão é o circuito Bandgap devido sua alta previbilidade, e baixa dependência em relação à temperatura e tensão de alimentação. Este trabalho estuda aplicação de Referência de Tensão Bandgap. O princípio, as topologias tradicionalmente usadas para implementar este método e as limitações que essas arquiteturas sofrem são investigadas. Será também apresentada uma pesquisa das questões recentes envolvendo alta precisão, operação com baixa tensão de alimentação e baixa potência, e ruído de saída para as referências Bandgap fabricadas em tecnologias submicrométricas. Além disso, uma investigação abrangente do impacto causado pelo o processo da fabricação e do ruído no desempenho da referência é apresentada. Será mostrado que o ruído de saída pode limitar a precisão dos circuitos Bandgap e seus circuitos de ajuste. Para desenvolver nosso trabalho, três Referências Bandgap foram projetadas utilizando o processo IBM 7RF 0.18 micra com uma tensão de alimentação de 1.8V. Também foram projetados os leiautes desses circuitos para prover informações pósleiaute extraídos e resultados de simulação elétrica. Este trabalho provê uma discussão de algumas topologias e das práticas de projeto para referências Bandgap.<br>A Voltage Reference is a pivotal block in several mixed-signal and radio-frequency applications, for instance, data converters, PLL's and power converters. The most used CMOS implementation for voltage references is the Bandgap circuit due to its highpredictability, and low dependence of the supply voltage and temperature of operation. This work studies the Bandgap Voltage References (BGR). The most relevant and the traditional topologies usually employed to implement Bandgap Voltage References are investigated, and the limitations of these architectures are discussed. A survey is also presented, discussing the most relevant issues and performance metrics for BGR, including, high-accuracy, low-voltage and low-power operation, as well as the output noise of Bandgap References fabricated in submicrometer technologies. Moreover, a comprehensive investigation on the impact of fabrication process effects and noise on the reference voltage is presented. It is shown that output noise can limit the accuracy of the BGR and trim circuits. To support and develop our work, three BGR´s were designed using the IBM 0.18 Micron 7RF process with a supply voltage of 1.8 V. The layouts of these circuits were also designed to provide post-extracted layout information and electrical simulation results. This work provides a comprehensive discussion on the structure and design practices for Bandgap References.

<p>The development and implementation of a metal gate technology (alloy, compound, or silicide) into metal-oxide-semiconductor field effect transistors (MOSFETs) is necessary to extend the life of planar CMOS devices and enable further downscaling. This thesis examines possible metal gate materials for improving the performance of the gate stack and discusses process integration as well as improved electrical and physical measurement methodologies, tested on capacitor structures and transistors. </p><p>By using reactive PVD and gradually increasing the N₂/Ar flow ratio, it was found that the work function (on SiO₂) of the TiN_x and ZrN_x metal systems could be modulated ~0.7 eV from low near nMOS work functions to high pMOS work functions. After high-temperature anneals corresponding to junction activation, both metals systems reached mid-gap work function values. The mechanisms behind the work function changes are explained with XPS data and discussed in terms of metal gradients and Fermi level pinning due to extrinsic interface states.</p><p>A modified scheme for improved Fowler-Nordheim tunnelling is also shown, using degenerately doped silicon substrates. In that case, the work functions of ALD/PVD TaN were accurately determined on both SiO₂ and HfO₂ and benchmarked against IPE (Internal Photoemission) results. KFM (Kelvin Force Microscopy) was also used to physically measure the work functions of PVD TiN and Mo deposited on SiO₂; the results agreed well with <i>C-V</i> and <i>I-V</i> data.</p><p>Finally, an appealing combination of novel materials is demonstrated with ALD TiN/Al₂O₃/HfAlO_x/Al₂O₃/strained-SiGe surface channel pMOS devices. The drive current and transconductance were measured to be 30% higher than the Si reference, clearly demonstrating increased mobility and the absence of polydepletion. Finally, using similarly processed transistors with Al₂O₃ dielectric instead, low-temperature water vapour annealing was shown to improve the device characteristics by reducing the negative charge within the ALD Al₂O₃.</p>

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.<br>Includes bibliographical references (p. 133-140).<br>by Mark Albert Armstrong.<br>Ph.D.