Relevant bibliographies by topics / CMOS technology scaling

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'CMOS technology scaling'

Author: Grafiati
Published: 4 June 2021
Last updated: 7 February 2022

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Journal articles on the topic "CMOS technology scaling"

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Kocanda, Piotr, and Andrzej Kos. "Energy losses and DVFS effectiveness vs technology scaling." Microelectronics International 32, no. 3 (August 3, 2015): 158–63. http://dx.doi.org/10.1108/mi-01-2015-0008.

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Purpose – This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS). Design/methodology/approach – Using analytical equations and Spice models of various technologies, energy losses are calculated and effectiveness of DVS and DFS is evaluated for every technology. Findings – Test showed that new dedicated technology for low static energy consumption can be as economical as older technologies. The dynamic voltage and frequency scaling are most effective when there is a dominance of dynamic energy losses in circuit. In case when static energy losses are comparable to dynamic energy losses, use of dynamic voltage frequency scaling can even lead to increased energy consumption. Originality/value – This paper presents complete analysis of energy losses in CMOS circuits and effectiveness of mentioned methods of energy conservation in CMOS circuits in six different technologies.
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Nowak, E. J. "(Invited) Advanced CMOS Scaling and FinFET Technology." ECS Transactions 50, no. 9 (March 15, 2013): 3–16. http://dx.doi.org/10.1149/05009.0003ecst.

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Jacob, Ajey P., Ruilong Xie, Min Gyu Sung, Lars Liebmann, Rinus T. P. Lee, and Bill Taylor. "Scaling Challenges for Advanced CMOS Devices." International Journal of High Speed Electronics and Systems 26, no. 01n02 (February 17, 2017): 1740001. http://dx.doi.org/10.1142/s0129156417400018.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.
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Shahidi, Ghavam G. "Chip Power Scaling in Recent CMOS Technology Nodes." IEEE Access 7 (2019): 851–56. http://dx.doi.org/10.1109/access.2018.2885895.

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Ioannou, D. E. "Scaling limits and reliability of SOI CMOS technology." Journal of Physics: Conference Series 10 (January 1, 2005): 1–6. http://dx.doi.org/10.1088/1742-6596/10/1/001.

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Dettmer, R. "Softly, softly [CMOS scaling advances by subthreshold technology]." IEE Review 51, no. 9 (September 1, 2005): 26–30. http://dx.doi.org/10.1049/ir:20050902.

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Anis, M., M. Allam, and M. Elmasry. "Impact of technology scaling on CMOS logic styles." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 49, no. 8 (August 2002): 577–88. http://dx.doi.org/10.1109/tcsii.2002.805631.

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Hon-Sum Wong. "Technology and device scaling considerations for CMOS imagers." IEEE Transactions on Electron Devices 43, no. 12 (1996): 2131–42. http://dx.doi.org/10.1109/16.544384.

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Nowak, Matt, and Brian Henderson. "Can High Density 3D Through Silicon Stacking Replace Lithography-Driven CMOS Scaling as the Engine for the Semiconductor Industry?" Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 000458–75. http://dx.doi.org/10.4071/2011dpc-ta12.

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High density 3D Through Silicon Stacking (TSS) offers opportunities for form factor miniaturization, cost reduction, and performance and energy improvement for advanced semiconductor systems. We will explore the value propositions for TSS compared to CMOS scaling to consider if TSS could replace lithography-driven CMOS scaling as the engine for the semiconductor industry. TSS can provide major reduction in volume form factor compared to 2D CMOS scaling. As the industry moves to advanced lithography and complex device structures at 16nm and below, the cost improvement resulting from CMOS scaling is expected to diminish. The cost reduction opportunities of TSS compared to traditional System on Chip (SOC) solutions enabled by lithography-driven CMOS scaling will be explored. The realized technology value propositions are strongly dependent on the specific system architecture and application. Architectural and software innovation enabled by HD 3D TSS and Architectural Pathfinding could provide an additional vector for continuing the improvements from semiconductor miniaturization.
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Maimon, J., and N. Haddad. "Overcoming scaling concerns in a radiation-hardened CMOS technology." IEEE Transactions on Nuclear Science 46, no. 6 (1999): 1686–89. http://dx.doi.org/10.1109/23.819139.

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Dissertations / Theses on the topic "CMOS technology scaling"

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Chaves, Romero Ferney Alveiro. "Study and Modeling of Multi‐ Gate Transistors in the Context of CMOS Technology Scaling." Doctoral thesis, Universitat Autònoma de Barcelona, 2012. http://hdl.handle.net/10803/96232.

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L’escalat dels transistors MOSFET convencionals ha portat a aquests dispositius a la nanoescala per incrementar tant les seves prestacions com el nombre de components per xip. En aquest process d’escalat, els coneguts “Short Channel Effects” representen una forta limitació. La forma més efectiva de suprimir aquests efectes i aixi estendre l’ús del MOSFET convencional, és la reducció del gruix de l’òxid de porta i l’augment de la concentració de dopants al canal. Quan el gruix d’òxid de porta es redueix a unes quantes capes atòmiques, apareix l’efecte túnel mecano-quàntic d’electrons, produint un gran augment en els corrents de fuita, perjudicant la normal operació dels MOSFETs. Això ha fet obligatori l’ús de materials d’alta permitivitat o materials high-κ en els dielèctrics de porta. Tot i les solucions proposades, la reducció de les dimensiones físiques del MOSFET convencional no pot ser mantinguda de forma indefinida i per mantenir la tendència tecnològica s’han suggerit noves estructures com ara MOSFETs multi-porta de cos ultra-prim. En particular, el MOSFET de doble porta és considerat com una estructura multi-porta prometedora per les seves diverses qualitats i avantatges en l’escalat. Aquesta tesi s’enfoca en la modelització de dispositius MOSFET de doble porta i, en particular, en la modelització del corrent túnel de porta que afecta críticamente al consum de potència del transistor. Primerament desenvolupem un model quàntic compacte tant per al potencial electrostàtic com per a la càrrega elèctrica en el transistor de doble-porta simètric amb cos no dopat. Després, aquest model quàntic s’utilitza per proposar un model analític compacte per al corrent túnel directe amb SiO2 com dielèctric de porta, primerament, i després amb una doble capa composta de SiO2 com a capa interfacial i un material “high-κ”. Finalment se desenvolupa un mètode precís per calcular el corrent túnel de porta. El mètode es basa en l’aplicació de condicions de frontera absorbents i, més especificament, en el mètode PML. Aquesta tesi està motivada per les recomanacions fetes pel “International Technology Roadmap of Semiconductors” (ITRS) sobre la necessitat existent de modelatge i simulació d’estructures semiconductores multi-porta.
The scaling of the conventional MOSFETs has led these devices to the nanoscale to increase both the performance and the number of components per chip. In this process, the so-called “Short Channel Effects” have arisen as a limiting factor. To extend the use of the bulk MOSFETs, the most effective ways of suppressing such effects are the reduction of the gate oxide thickness and increasing of the channel doping concentration. When the gate oxide thickness is reduced to a few atomic layers, quantum mechanical tunneling is responsible of a huge increase in the gate leakage current impairing the normal operation of MOSFETs. This has made mandatory the use of high permittivity materials or high-κ as gate dielectrics. Despite the proposed solutions, reduction of the physical dimensions of the conventional MOSFETs cannot be maintained. To keep the technological trend, new MOSFET structures have been suggested such as ultra-thin body Multi-Gate MOSFETs. In particular, the Double-Gate MOSFETs is considered as a promising MG structure for its several qualities and advantages in scaling. This thesis focuses on the modeling of Double-Gate MOSFET and, in particular, on the modeling of the gate leakage current critically affecting the power consumption. First we develop a compact quantum model for both the electrostatic potential and the electric charge in symmetric double-gate MOSFET with undoped thin body. Then, this quantum model is used to propose an analytical compact model for the direct tunnelling current with SiO2 as gate dielectric, firstly, and later assuming a dual layer consisting of a SiO2 interfacial layer and a high-κ material. Finally, an accurate method for the calculation of the gate tunnelling current is developed. It is based on Absorbing Boundary Conditions techniques and, more specifically, on the Perfectly Mached Layer (PML) method. This thesis is motivated by the recommendations given by the “International Technology Roadmap of Semiconductors” (ITRS) about the need for the modeling and simulation of multi-gate semiconductor structures.
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Elabd, Salma. "Analytical and Experimental Study of Wide Tuning Range Low Phase Noise mm-Wave LC-VCOs." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461251044.

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Kruth, Andre Konrad [Verfasser]. "The impact of technology scaling on integrated analogue CMOS RF front-ends for wireless applications / vorgelegt von Andre Konrad Kruth." 2008. http://d-nb.info/992069122/34.

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Bower, Fred. "Technology Impacts of CMOS Scaling on Microprocessor Core Design for Hard-Fault Tolerance in Single-Core Applications and Optimized Throughput in Throughput-Oriented Chip Multiprocessors." Diss., 2010. http://hdl.handle.net/10161/2391.

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The continued march of technological progress, epitomized by Moore’s Law provides the microarchitect with increasing numbers of transistors to employ as we continue to shrink feature geometries. Physical limitations impose new constraints upon designers in the areas of overall power and localized power density. Techniques to scale threshold and supply voltages to lower values in order to reduce power consumption of the part have also run into physical limitations, exacerbating power and cooling problems in deep sub-micron CMOS process generations. Smaller device geometries are also subject to increased sensitivity to common failure modes as well as manufacturing process variability.

In the face of these added challenges, we observe a shift in the focus of the industry, away from building ever–larger single–core chips, whose focus is on reducing single–threaded latency toward a design approach that employs multiple cores on a single chip to improve throughput. While the early multicore era utilized the existing single–core designs of the previous generation in small numbers, subsequent generations have introduced cores tailored to multicore use. These cores seek to achieve power-efficient throughput and have led to a new emphasis on throughput-oriented computing, particularly for Internet workloads, where the end-to-end computational task is dominated by long–latency network operations. The ubiquity of these workloads makes a compelling argument for throughput–oriented designs, but does not free the microarchitect fully from latency demands of common workloads in enterprise and desktop application spaces.

We believe that a continued need for both throughput–oriented and latency–sensitive processors will exist in coming generations of technology. We further opine that making effective use of the additional transistors that will be available may require different techniques for latency–sensitive designs than for throughput–oriented ones, since we may trade latency or throughput for the desired attribute of a core in each of the respective paradigms.

We make three major contributions with this thesis. Our first contribution is a fine–grained fault diagnosis and deconfiguration technique for array structures, such as the ROB, within the microprocessor core. We present and evaluate two variants of this technique. The first variant uses an existing fault detection and correction technique whose scope is the processor core execution pipeline to ensure correct processor operation. The second variant integrates fault detection and correction into the array structure itself to provide a self–contained, fine–grained, fault detection, diagnosis, and repair technique.

In our second contribution, we develop a lightweight, fine–grained fault diagnosis mechanism for the processor core. In this work, we leverage the first contribution's methods to provide deconfiguration of faulty array elements. We additionally extend the scope of that work to include all pipeline circuitry from instruction issue to retirement.

In our third and final contribution, we focus on throughput–oriented core data cache design. In this work, we study the demands of the throughput–oriented core running a representative workload and then propose and evaluate an alternative data cache implementation that more closely matches the demands of the core. We then show that a better–matched cache design can be exploited to provide improved throughput under a fixed power budget.

Our results show that typical latency–sensitive cores have sufficient redundancy to make finegrained hard–fault tolerance an affordable alternative for hardening complex designs. Our designs suffer little or no performance loss when no faults are present and retain nearly the same performance characteristics in the presence of small numbers of hard faults in protected structures. In our study of the latency–sensitive core, we have shown that SRAM–based designs have low latencies that end up providing less benefit to a throughput–oriented core and workload than a better–fitted data cache composed of DRAM. The move from a high–power, fast technology to a lower–power, slower technology allows us to increase L1 data cache capacity, which is a net benefit for the throughput–oriented core.


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"Technology Impacts of CMOS Scaling on Microprocessor Core Design for Hard-Fault Tolerance in Single-Core Applications and Optimized Throughput in Throughput-Oriented Chip Multiprocessors." Diss., 2010. http://hdl.handle.net/10161/2391.

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Zhang, Heng. "High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8609.

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The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.
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Book chapters on the topic "CMOS technology scaling"

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Abbas, Karim. "Scaling." In Handbook of Digital CMOS Technology, Circuits, and Systems, 411–38. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37195-1_10.

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He, Gang, Zhaoqi Sun, Mao Liu, and Lide Zhang. "Scaling and Limitation of Si-Based CMOS." In High-k Gate Dielectrics for CMOS Technology, 1–29. Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2012. http://dx.doi.org/10.1002/9783527646340.ch1.

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Figueiredo, Monica, and Rui L. Aguiar. "A Study on CMOS Time Uncertainty with Technology Scaling." In Lecture Notes in Computer Science, 146–55. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-95948-9_15.

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Dey, S., and S. K. Banerjee. "Silicon MOSFETs for ULSI: Scaling CMOS to Nanoscale." In Comprehensive Semiconductor Science and Technology, 52–83. Elsevier, 2011. http://dx.doi.org/10.1016/b978-0-44-453153-7.00008-0.

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Wong, Hei, Takamasa Kawanago, Kuniyuki Kakushima, and Hiroshi Iwai. "High-κ Dielectric Scaling for Nano-CMOS Technology." In Integrated Nanodevice and Nanosystem Fabrication, 125–79. Jenny Stanford Publishing, 2017. http://dx.doi.org/10.1201/9781315181257-4.

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Ferreira, Pietro M., Hao Cai, and Lirida Naviner. "Reliability Aware AMS/RF Performance Optimization." In Advances in Computer and Electrical Engineering, 28–54. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-6627-6.ch002.

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Reliability has become an important issue in the continuously CMOS technology scaling down. The exploration of the technology limits using classic performance optimization techniques and leads to the best trade-off for the area, power consumption, and speed. Nevertheless, such key characteristics have been degraded in a context of continuous use and stressful environment. Thus, circuit reliability emerges as a design criterion for AMS/RF performance optimization. Aiming a design for reliability, this chapter presents an overview of CMOS unreliable phenomena. Reliability-aware methodologies for circuit design, simulation, and optimization are reviewed. The authors focus in particular on large and complex systems, providing circuit design insights to achieve a reliability specification from system-level to transistor-level. They highlight the more sensitive building blocks in CT S? modulator and demonstrate how performance is affected by unreliable phenomena. A system-level direct-conversion RF front-end design is described in top-down approach. Electrical simulations are presented with 65 nm CMOS technology.
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Madhavi, B. K., and Rajendra Prasad Somineni. "Low Power, High Performance CNTFET-Based SRAM Cell Designs." In Advances in Computer and Electrical Engineering, 93–128. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1393-4.ch006.

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The main objective of this chapter is to provide high-performance, low-power solutions for VLSI system designers. As technology scales down to 32nm and below, the present CMOS technology has to face the scaling limit, such as the increased leakage power, SCEs, and so on. To overcome these limits, the researchers have experimented on other technologies, among which a CNT technology-based device called CNTFET has been evaluated as one of the promising replacements to CMOS technology. In any digital systems, memory is an integral part, and it is also the largest constituent. SRAM is a widely used memory. In today's ICs, SRAM is going to occupy 60-70% of the total chip area. In this connection, this chapter describes the design of CNTFET-based 6T SRAM cell using circuit-level leakage reduction techniques, named sleep transistor, forced stack, data-retention sleep transistor, and stacked sleep.
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Shahid, Arsalan, Saad Arif, Muhammad Yasir Qadri, and Saba Munawar. "Power Optimization Using Clock Gating and Power Gating." In Innovative Research and Applications in Next-Generation High Performance Computing, 1–20. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-5225-0287-6.ch001.

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The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system components level are proposed by the research community such as clock gating, operand isolation, memory splitting, power gating, dynamic voltage and frequency scaling, etc. This chapter reviews advancements in the dynamic power optimization techniques like clock gating and power gating. This chapter also reviews some architectures and optimization techniques that have been developed for greater power reduction without any significant performance degradation or area cost.
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Kumar, Sunil, and Balwinder Raj. "Simulations and Modeling of TFET for Low Power Design." In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 640–67. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-8823-0.ch021.

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In Complementary Metal-Oxide-Semiconductor (CMOS) technology, scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past four decades. However, as the technology advancement on nanometer scale regime for the purpose of building ultra-high density integrated electronic computers and extending performance, CMOS devices are facing fundamental problems such as increased leakage currents, large process parameter variations, short channel effects, increase in manufacturing cost, etc. The new technology must be energy efficient, dense, and enable more device function per unit area and time. There are many novel nanoscale semiconductor devices, this book chapter introduces and summarizes progress in the development of the Tunnel Field-Effect Transistors (TFETs) for low power design. Tunnel FETs are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current. Tunnel FETs avoid the limit 60mv/decade by using quantum-mechanical Band-to-Band Tunneling (BTBT).
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Bala, Shashi, Mamta Khosla, and Raj Kumar. "CNTFET-Based Memory Design." In Advances in Computer and Electrical Engineering, 16–36. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1393-4.ch002.

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As the feature size of device has been scaling down for many decades, conventional CMOS technology-based static random access memory (SRAM) has reached its limit due to significant leakage power. Therefore, carbon nanotube field effect transistor (CNTFET) can be considered most suitable alternative for SRAM. In this chapter, the performance and stability of CNTFET-based SRAM cells have been analyzed. Numerous figures of merit (FOM) (e.g., read/write noise margin, power dissipation, and read/write delay) have been considered to analyze the performance of CNTFET-based. The static power consumption in CNTFET-based SRAM cell was compared with conventional complementary metal oxide semiconductor (CMOS)-based SRAM cell. Conventional CNTFET and tunnel CNTFET-based SRAMs have also been considered for comparison. From the simulation results, it is observed that tunnel CNTFET SRAM cells have shown improved FOM over conventional CNTFET 6T SRAM cells without losing stability.
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Conference papers on the topic "CMOS technology scaling"

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Zhibin Ren, K. T. Schonenberg, V. Ontalus, I. Lauer, and S. A. Butt. "CMOS gate height scaling." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734471.

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Rao, K. V., Chi-Nung Ni, Fareen Adeni Khaja, Xuebin Li, Shashank Sharma, Raymond Hung, Michael Chudzik, et al. "NMOS contact engineering for CMOS scaling." In 2015 15th International Workshop on Junction Technology (IWJT). IEEE, 2015. http://dx.doi.org/10.1109/iwjt.2015.7467093.

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Horowitz, Mark. "Scaling, Power, and the Future of CMOS Technology." In 2008 66th Annual Device Research Conference (DRC). IEEE, 2008. http://dx.doi.org/10.1109/drc.2008.4800711.

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Tyagi, S., C. Auth, I. Ban, P. Chang, R. Chau, T. Ghani, C.-H. Jan, et al. "Future device scaling - Beyond traditional CMOS." In 2009 2nd International Workshop on Electron Devices and Semiconductor Technology (IEDST). IEEE, 2009. http://dx.doi.org/10.1109/edst.2009.5166098.

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Mocuta, A., P. Weckx, S. Demuynck, D. Radisic, Y. Oniki, and J. Ryckaert. "Enabling CMOS Scaling Towards 3nm and Beyond." In 2018 IEEE Symposium on VLSI Technology. IEEE, 2018. http://dx.doi.org/10.1109/vlsit.2018.8510683.

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Wong, H. S. Philip, Lan Wei, and Jie Deng. "The future of CMOS scaling - parasitics engineering and device footprint scaling." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734460.

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Jansson, Jussi-Pekka, Pekka Keranen, Juha Kostamovaara, and Andrea Baschirotto. "CMOS technology scaling advantages in time domain signal processing." In 2017 IEEE International Instrumentation and Measurement Technology Conference (I2MTC). IEEE, 2017. http://dx.doi.org/10.1109/i2mtc.2017.7969659.

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Ryckaert, J., M. H. Na, P. Weckx, D. Jang, P. Schuddinck, B. Chehab, S. Patli, et al. "Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!" In 2019 IEEE International Electron Devices Meeting (IEDM). IEEE, 2019. http://dx.doi.org/10.1109/iedm19573.2019.8993631.

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Cao, Q. "Carbon Nanotube Transistor Technology for Scaling Beyond Si CMOS." In 2016 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2016. http://dx.doi.org/10.7567/ssdm.2016.j-3-01.

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Chang, M. C. Frank. ""Impact of CMOS Scaling on RFIC Designs"." In 2007 IEEE International Workshop on Radio-Frequency Integration Technology. IEEE, 2007. http://dx.doi.org/10.1109/rfit.2007.4444017.

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